DETAILED ACTION
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
This Office Action is in response to the communication filed on 4/25/2025.
Claim 1 is pending for consideration.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Priority
Acknowledgment is made of applicant’s claim for foreign priority under 35 U.S.C. 119 (a)-(d).
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 4/25/2025 is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Specification
The lengthy specification has not been checked to the extent necessary to determine the presence of all possible minor errors. Applicant’s cooperation is requested in correcting any errors of which applicant may become aware in the specification.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1 is rejected under 35 U.S.C. 102(a)(1) as being anticipated by HOROWITZ et al. (WO 2018010794) (hereinafter HORO).
Regarding claim 1, HORO discloses a method for securely processing digital information, including the following steps, performed by a secure element including a secure processor, and at least one internal memory and a code associating unit, both external to the secure processor (HORO: Fig. 5a and page 17 lines 1-32):
- loading the digital information from an external memory into the at least one internal memory of the secure element (HORO: page 16 lines 5-32 and page 18 lines 5-32, “when a data write operation is initiated by an entity, to-be-written data (i.e. first data) and an ID of the entity that provides the first data are written into the memory.”… “The to-be-written data includes one or more data bits cells(units), for example, one data bits cell may be 8 data bits or 64 data bits or 128 data bits.”);
- at the code associating unit, segmenting the digital information into words of digital information (HORO: pages 17-19 lines 5-35, “When a data write operation is initiated by a VM on a memory address, the memory address and a VM ID of the VM performing the write may be stored in a cache, a buffer or a register of the computing system 50, such as the processor core, as shown in Fig.5a. The checksum module is configured to calculate one or more ECC bits value from the to-be- written data and a VM ID of the VM, such as by using XOR computation or any other ECC generation algorithm”), generating error-detection codes or error-correction codes from said words of digital information and associating said error-detection codes or error-correction codes with the corresponding words in the at least one internal memory (HORO: pages 17-19 lines 5-35, “The checksum module is configured to calculate one or more ECC bits value from the to-be-read data and a VM ID of the VM”);
- transferring the words of digital information and the associated error-detection codes or error-correction codes from the at least one internal memory to the secure processor (HORO: pages 18-19 lines 1-35, “one or more data bits cells and one or more ECC bits are written to the memory 502 in one to one correspondence. In other words, the memory 502 may stores one or more memory cells and one or more ECC bits which are one to one correspondence/association with the one or more memory cells.”);
- in the secure processor, verifying the words of digital information based on the associated error-detection codes or error-correction codes before processing the digital information contained in said words (HORO: pages 17-19 lines 1-35, “The comparator is configured to compare one or more calculated ECC bits value with one or more ECC bits value that stored with the to-be-read data in the memory 502, and to generate a machine check exception, MCE signal if the calculated ECC bits value is inconsistent with the stored ECC bits value, so that a VMM or an operating system kernel is invoked to perform an exception function in response to the MCE signal.”).
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to TRANG T DOAN whose telephone number is (571)272-0740. The examiner can normally be reached Monday-Friday 7-4 ET.
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/TRANG T DOAN/Primary Examiner, Art Unit 2431
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