DETAILED ACTION
Allowable Subject Matter
Claims 4, and 6-20 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1-3 and 5 are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Zheng (US Pub: 2022/0157233 A1).
As to claim 1, Zheng discloses a pixel drive circuit (i.e. as seen in figure 1 embodiment of Zheng, the active matrix display driving system uses the input driving element 5 to control the pixel circuit AA) (see Fig. 1, [0070-0073]), comprising:
a plurality of columns of pixel units arranged in a row direction (i.e. as seen in figure 1 the plurality of column is seen in AA as seen in the data line connected column structures in a row direction) (see Fig. 1, [0071-0072]);
a plurality of data lines spaced apart from one another and extending in a column direction (i.e. the plurality of data line is seen in figure 1 D_1, D_2 … Dm) (see Fig. 1, [0071-0072]), wherein each of the plurality of data lines is electrically connected to one column of pixel units (i.e. as seen in figure 1 the plurality of data line is electrically connected to one column of pixel unit via the MUX structure) (see Fig. 1, [0071-0072]);
a plurality of source drive lines, wherein the number of source drive lines is less than the number of data lines (i.e. as seen in figure 1 the source drive line at INPUT is less than data line in the multiplexed connections) (see Fig. 1, [0071-0072]); and
a plurality of switch assemblies (i.e. the element 5 with the MUX structure) (see Fig. 1, [0071-0073]), wherein a first connection end of each of the plurality of switch assemblies is electrically connected to at least one of the plurality of data lines (i.e. the D1 connection is seen to connect to S1 data line for the first column) (see Fig. 1, [0070-0072]), a second connection end of each of the plurality of switch assemblies is electrically connected to one of the plurality of source drive lines (i.e. the second end of the INPUT line which is a source drive line) (see Fig. 1, [0070-0072]), and at least two of the plurality of data lines are electrically connected to a same source drive line through different switch assemblies (i.e. as the as seen in figure 1 the D1 and D2 lines are connected to the source INPUT line via two different switch assembly mux 1 and mux 3) (see Fig. 1, [0070-0072]).
As to claim 2, Zheng teaches the pixel drive circuit of claim 1, wherein each of the plurality of source drive lines is electrically connected to at least two of the plurality of data lines in adjacent columns (i.e. as seen in figure 1 the D1 and D2 data line is connected to the source line) (see Fig. 1, [0070-0073]).
As to claim 3, Zheng teaches the pixel drive circuit of claim 2, wherein the plurality of switch assemblies comprise a first sub-switch and a second sub-switch, a second connection end of the first sub-switch and a second connection end of the second sub-switch are electrically connected to a same source drive line, and a first connection end of the first sub-switch and a first connection end of the second sub-switch are electrically connected to two of the plurality of data lines in adjacent columns, respectively (i.e. as seen in figure 1 the system of Zheng shows the sub-switch MUX which connects the plurality of data line to a single source line) (see Fig. 1, [0070-0072]).
As to claim 5, Zheng teaches the pixel drive circuit of claim 1, wherein each of the plurality of source drive lines is configured to provide a plurality of data voltages during a row scanning period (i.e. as seen in figure 5 the INPUT source driving is seen to be an AC signal with a plurality of voltage value during the driving phase) (see Fig. 5, [0119-0120]), and the plurality of data voltages are respectively supplied to different data lines through on-off of the plurality of switch assemblies (i.e. as seen in figure 1-5 the different data lines are control though the on-off of the MUX switch signal which applies the plurality of data voltage to the data lines respectively) (see Fig. 1-5, [0119-0120]).
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. The prior art Hosoyachi et al. (US Pub: 2022/0013543 A1) is cited to teach another type of display method which has multiplexed data line connected to the column source lines in figures 1-3 embodiments.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to CALVIN C. MA whose telephone number is (571)270-1713. The examiner can normally be reached 8:00AM-5:00PM.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Benjamin C. Lee can be reached on 571-272-2963. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/CALVIN C MA/Primary Examiner, Art Unit 2693 February 21, 2026