DETAILED ACTION
Status of Application
The Preliminary Amendment filed 06/30/2025 has been entered.
Claims 17-28 are pending in the present application.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 20 and 26 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
The term “large number” in claims 20 and 26 is a relative term which renders the claim indefinite. The term “large number” is not defined by the claim, the specification does not provide a standard for ascertaining the requisite degree, and one of ordinary skill in the art would not be reasonably apprised of the scope of the invention. It is unclear what value constitutes a “large” number, since two readers can have different interpretations of “large.”
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 17, 22, 23, and 28 23 is/are rejected under 35 U.S.C. 103 as being unpatentable over Biles et al (hereinafter Biles), US 20060095720 A1, in view of McGhee et al (hereinafter McGhee), US 20120257626 A1.
Referring to claims 17 and 23, taking claim 17 as exemplary, Biles discloses a method for computing hash values for digital inputs, comprising:
dividing an algorithm [fig. 7A, “SEQUENCE 1”] into a number of discrete sequential computational steps in a specific order, from a first computational step to a last computational step [fig. 7A, discrete sequential computational steps comprising ADD, AND, SUB];
coupling a number of slice processing units (SPUs), equal to the number of discrete sequential computational steps, in an ordered stack [fig. 8, three SPUs 810, 820, 830], and configuring each SPU to receive a digital input, perform one of the discrete sequential computational steps and to output a digital value as a result of the discrete computational step performed [FIG. 8, paragraph 89, “The four inputs to the first level are 842, 844, 846 and 848 and two of these inputs are used to feed values from r0 and r1 to the first-level functional unit 810”… the output of the ADD operation should be supplied as an input to the second-level functional unit 820 (the examiner notes that there is a typographical error in paragraph 89, where Biles refers to “AND operation” which should read as “ADD operation”)…”The output of the logical AND performed by functional unit 820 is supplied as one input to the third-level functional unit 830, which is configured to perform a subtraction”…”The final result of the subgraph operation emerges from output terminal 850”];
wherein the first SPU in the ordered stack [fig. 8, element 810] receives a digital value from an input port [fig. 8, input ports 842, 844, 846, 848; paragraph 89, “The four inputs to the first level are 842, 844, 846 and 848 and two of these inputs are used to feed values from r0 and r1 to the first-level functional unit 810”], performs the first discrete computational step in the specific order [fig. 8, performing an ADD computational step], and outputs a result of the first computational step as an input to the second SPU in the ordered stack [paragraph 89, fig. 8, the output of the ADD operation should be supplied as an input to the second-level functional unit 820 (the examiner notes that there appears to be a typographical error in paragraph 89, where Biles refers to “AND operation” which should read as “ADD operation”)], each SPU in order in the ordered stack performs a discrete computational step according to the order of the discrete computational steps [fig. 8, performing ADD computational step first, computing the AND second, performing subtraction step third], passing a result to the next SPU in the ordered stack [fig. 8, paragraph 89, “The output of the logical AND performed by functional unit 820 is supplied as one input to the third-level functional unit 830, which is configured to perform a subtraction”] and the last SPU in the ordered stack performs the last computational step and outputs a digital value to an output port [fig. 8, paragraph89, ”The output of the logical AND performed by functional unit 820 is supplied as one input to the third-level functional unit 830, which is configured to perform a subtraction”…”The final result of the subgraph operation emerges from output terminal 850”].
Biles does not explicity disclose a Hash algorithm.
However, McGhee discloses a Hash algorithm [paragraphs 40-41, “It is further noted that any desired hash algorithm could be used”; “If desired, a non-cryptographic MurmurHash-type hash algorithm can be used and can be split into multiple 16-bit hash processes”].
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to utilize the teachings of McGhee in the method of Biles to implement, a Hash algorithm, in order to lead to fewer hash collisions problems and thereby improve overall performance in avoiding false duplicate packet indications [McGhee, paragraph 40].
Referring to claims 22 and 28, taking claim 22 as exemplary, the modified Biles discloses the method of claim 17 comprising selecting the hash algorithm as a SHA- 256 algorithm [McGhee, paragraphs 40-41, “It is further noted that any desired hash algorithm could be used”].
Claim(s) 18-19 and 24-25 is/are rejected under 35 U.S.C. 103 as being unpatentable over Biles, in view of McGhee, as applied to claims 17 and 23 above, and further in view of Kakui et al (hereinafter Kakui), US 20090235223 A1.
Referring to claims 18 and 24, taking claim 18 as exemplary, the modified Biles does not explicitly disclose the method of claim 17, further comprising operating the ordered stack in a cyclic mode, inputting a new digital value to the first SPU and outputting a digital value from the last SPU in each turn of the cycle.
However, Kakui discloses operating the ordered stack in a cyclic mode, inputting a new digital value to the first SPU and outputting a digital value from the last SPU in each turn of the cycle [paragraph 45, In this case, the hardware model successively inputs a series of input values every clock cycle…and thereafter, successively outputs a series of output values corresponding to the series of input values every clock cycle. For example…When inputting a fourth input value (input data 4), the hardware model outputs an output value (processing result data) corresponding to the first input value (input data 1). Then, when inputting a fifth input value (input data 5), the hardware model outputs an output value (processing result data) corresponding to the second input value (input data 2)].
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to utilize the teachings of Kakui in the method of the modified Biles to implement, operating the ordered stack in a cyclic mode, inputting a new digital value to the first SPU and outputting a digital value from the last SPU in each turn of the cycle, in order to shorten time for designing [Kakui, paragraph 6].
Referring to claims 19 and 25, taking claim 19 as exemplary, the modified Biles discloses the method of claim 18, wherein a hash value for the first input is output after a number of cycles at least equal to the number of SPUs [Biles, FIG. 8, paragraph 89, ”The final result of the subgraph operation emerges from output terminal 850”; McGhee, paragraphs 40-41; Kakui, paragraph 45, For example…When inputting a fourth input value (input data 4), the hardware model outputs an output value (processing result data) corresponding to the first input value (input data 1). Then, when inputting a fifth input value (input data 5), the hardware model outputs an output value (processing result data) corresponding to the second input value (input data 2); hence the combined Biles discloses outputting a hash result after at least three cycles (equal to the number of SPUs) since the result is only computed after the final SPU in the stack computes the result].
Claim(s) 20 and 26 is/are rejected under 35 U.S.C. 103 as being unpatentable over Biles, in view of McGhee, in view of Kakui, as applied to claims 19 and 25 above, and further in view of Kakaiya et al (hereinafter Kakaiya), US 20190042329 A1.
Referring to claims 20 and 26, taking claim 20 as exemplary, the modified Biles disclose the method of claim 19, comprising a further step of organizing the inputs into a sequential stream, and producing hash values an entity by streaming the digital inputs into the first SPU and capturing the outputs from the last SPU [Biles, FIG. 8, paragraph 89; McGhee, paragraphs 40-41; Kakui, paragraph 45].
The modified Biles does not explicitly disclose preparing a digital input for a large number of discrete entities.
However, Kakaiya discloses preparing a digital input for a large number of discrete entities [paragraph 37, “software-level entities (sometimes referred to collectively as “task offloading modules” that offload tasks to programmable accelerator device 100)”; entities offloading tasks/preparing inputs to accelerator].
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to utilize the teachings of Kakaiya in the method of the modified Biles to implement, preparing a digital input for a large number of discrete entities, in order to provide improved speeds, latency, power efficiency, and flexibility for end-to-end cloud computing, networking, storage, artificial intelligence, autonomous driving, virtual reality, augmented reality, gaming, and other data-centric applications [Kakaiya, paragraph 3].
Claim(s) 21 and 27 is/are rejected under 35 U.S.C. 103 as being unpatentable over Biles, in view of McGhee, as applied to claims 17 and 23 above, and further in view of Suga et al (hereinafter Suga), US 20240296249 A1.
Referring to claims 21 and 27, taking claim 21 as exemplary, the modified Biles discloses the method of claim 17 further comprising operating the SPU stack with a general purpose computer [Biles, paragraph 55].
The modified Biles does not explicitly disclose retrieving input values from random-access memory (RAM) and storing hash values in RAM associated with input values.
However, Suga discloses retrieving input values from random-access memory (RAM) and storing hash values in RAM associated with input values [paragraph 201; fig. 12].
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to utilize the teachings of Suga in the method of the modified Biles to implement, retrieving input values from random-access memory (RAM) and storing hash values in RAM associated with input values, in order to reduce processing load and maintain integrity of data [Suga, paragraph 44].
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure:
Deering, US 4754412, discloses passing results to SPUs in an order [fig. 1].
Totsuka, US 7644255 B2, discloses data processing circuits 120 and passing results down the pipeline [fig. 2].
Any inquiry concerning this communication or earlier communications from the examiner should be directed to FARLEY J ABAD whose telephone number is (571)270-3425. The examiner can normally be reached Mon-Fri 8:30 AM - 7 PM.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Idriss Alrobaye can be reached at (571) 270-1023. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/Farley Abad/ Primary Examiner, Art Unit 2181
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