DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Specification
The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed.
The following title is suggested: A resonant CLL-type isolated topology with a high-frequency planar transformer.
The lengthy specification has not been checked to the extent necessary to determine the presence of all possible minor errors. Applicant’s cooperation is requested in correcting any errors of which applicant may become aware in the specification.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim(s) 12 - 13 are rejected under 35 U.S.C. 102(a)(1) and (a)(2) as being anticipated by Li et al (US Pub. No. 2025/0105730 A1); (hereinafter Li).
Regarding claim 12, Li [e.g., Fig. 2] discloses a system [e.g., bidirectional isolated high voltage DC-DC converter (200)], comprising: a low-voltage switching circuit comprising a first port of the system [e.g., ports 291 and 292]; a transformer [e.g., transformer T1 (263)], having: a first winding connected to the low-voltage switching circuit [e.g., terminal 3 and 4], and a second winding [e.g. terminal 1 and 2]; a high-voltage switching circuit comprising a second port of the system and being connected to the second winding [e.g., ports 221 and 222]; and an inductance-capacitance tank circuit comprising a resonant capacitor on a first side of the transformer [e.g., Crs 265], and a resonant inductor on a second side of the transformer [e.g., Lrp 262], the second side being different from the first side [e.g., two separate sides].
Regarding claim 13, Li [e.g., Fig. 2] discloses wherein the resonant capacitor is on a low-voltage side of the transformer [e.g., capacitors Crs connected to ports 291 (+135VDC), 292], and the resonant inductor is on a high-voltage side of the transformer [e.g., resonant inductor Lrp connected to ports 221 (800VDC) and 222 (800VDC)].
Claim(s) 19 – 20 are rejected under 35 U.S.C. 102(a)(1) and (a)(2) as being anticipated by Mallik et al (US Pub. No. 2023/0387816 A1); (hereinafter Mallik).
Regarding claim 19, Mallik [e.g., Figs. 1 and 20] discloses a method [e.g., method of controlling CLLC converter], comprising: selecting a circuit parameter or control parameter for a dc-to-dc converter [e.g., regulated voltage (DVo), p. 0130 recites “As shown in FIG. 20, the iterative process 2000 begins by defining the design specification, which include the desired resonant frequency (fr), the desired rated power (P0), the desired input and output voltage (Vin, V0), and the desired target efficiency (η) at 2002.”], the selecting comprising: calculating an operating current or an operating voltage for the dc-to-dc converter using an enhanced generalized harmonic approximation analysis [e.g., -- refer to Fig. 20 --, calculates voltage regulation (DVo), p. 0008 recites “performing an iterative design process that considers a gain versus operational frequency trend, an input impedance analysis, a soft-switching criteria for primary and secondary bridges, and voltage regulation constraints; and outputting the winding configuration based on the iterative design process.”].
Regarding claim 20, Mallik [e.g., Figs. 1 and 20] discloses wherein: the dc-to-dc converter [e.g., CLLC converter] comprises: a low-voltage switching circuit comprising a first port of the dc-to-dc converter [e.g., S5 – S8 with respective port supplying Vo]; a transformer [e.g., transformer formed by windings 124 and 126], having: a first winding connected to the low-voltage switching circuit [e.g., winding 126], and a second winding [e.g., winding 124]; a high-voltage switching circuit comprising a second port of the dc-to-dc converter and being connected to the second winding [e.g., winding 124 connected to switches S1 – S4 supplying Vin via respective port]; and an inductance-capacitance tank circuit comprising a resonant capacitor on a first side of the transformer [e.g., capacitor Cp (108)], and a resonant inductor on a second side of the transformer [e.g., inductor Ls (106) connected on secondary side]; the method comprises selecting a circuit parameter for the dc-to-dc converter [e.g., selects multiple parameters, p. 130 recites “The design specifications are iteratively modified in a CLLC converter analysis and design phase, where various parameters, including optimum value of turns ratio (n), tank current (Ip and Is), active component losses (conduction and switching losses), and loss budget for resonant tank, are adjusted and various features, ….”].; the circuit parameter is a parameter selected from the group consisting of the capacitance of the resonant capacitance, the inductance of the resonant inductor, the inductance of a magnetizing inductance of the transformer, the number of turns of the first winding, and the number of turns of the second winding [e.g., parameter selected from multiple optimum tank parameters, p. 0130 recites “The design specifications are iteratively modified in a CLLC converter analysis and design phase, where various parameters, including optimum value of turns ratio (n), tank current (Ip and Is), active component losses (conduction and switching losses), and loss budget for resonant tank, are adjusted and various features, including gain versus operational frequency trend analysis (G vs f), gain gradient formulation (dG/df ), input impedance analysis (Zin), ZVS criteria for primary side bridge (Ip<0 during turn-on, SR criteria for secondary side bridge (Is˜0 during turn-off, and voltage regulation (ΔV0), are determined, at 2004. From the iteratively modified specification parameters, the target optimum tank parameters {Lm, Lp, Ls, Cp, Cs} and the magnetic core selection are determined while adhering to volumetric considerations at 2006. From the core dimensions, the selection of winding configuration based on IPC 2221 are determined with trade-offs with PCB fabrication parameters and airgaps at 2008.”]; the selecting comprises optimizing an objective function subject to a constraint [e.g., p. 0130 recites “From the modeling, simulations, and verification, determinations are made to determine if the tank parameters satisfy desired criteria, including grain gradient, ZVS and SR constraints, voltage regulation, and losses under the provided magnetics loss budget at 2012.”]; the objective function is based on an efficiency of the dc-to-dc converter [e.g., p. 0107 recites “However, it is important to understand the implication of each configuration on the performance of the CLLC converter and understand the specifics behind choosing the most optimal one for enhanced efficiency and gain modulation. In that context, factors like ZVS criteria, winding losses and its frequency dependency, resultant gain, and physical constraints play a major role, as described in this section.”]; and the constraint constrains the dc-to-dc converter to operate with zero-voltage switching [e.g., p. 0130 recites “From the modeling, simulations, and verification, determinations are made to determine if the tank parameters satisfy desired criteria, including grain gradient, ZVS and SR constraints, voltage regulation, and losses under the provided magnetics loss budget at 2012. If the desired criteria are satisfied, then the optimum winding configuration is determined at 2014. If not, other winding configuration are tested where the magnetic design process with a different core is repeated at 2016. If there are other possible winding configurations, then the magnetic design process progresses back to 2018.”].
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim(s) 1, 9 and 11 are rejected under 35 U.S.C. 103 as being unpatentable over Krause et al (US Pub. No. 2021/0175793 A1); (hereinafter Krause).
Regarding claim 1, Krause [e.g., Figs. 1 – 8] discloses a system [e.g., battery/transformer system], comprising: a low-voltage switching circuit comprising a first port of the system [e.g., QS1 – QS4 connected to port corresponding to V2DC]; a transformer [e.g., Tr1], having: a first winding connected to the low-voltage switching circuit [e.g., first winding connected to port supplying V2DC], and a second winding [e.g., winding connected to port supplying V1DC]; and a high-voltage switching circuit comprising a second port of the system and being connected to the second winding [e.g., QP1 – QP4 connected to port corresponding to V1DC], wherein: the system is capable, for a first set of control parameter values [e.g., -- refer to Fig. 7 -- control values corresponding to time interval T2-T3, p. 0060 recites “In this time interval T2-T3, the secondary-side switch QS2 is open and QS1 is conductive, and the switch QS4 remains conductive (such that, analogously to the first time interval T0-T1, the clamping capacitor Cclamp is discharged again—only the current flows through the secondary winding of the transformer Tr1 in the opposite direction. In this way, analogously to the first time interval T0-T1, a current is induced on the primary side, which flows in the opposite direction as in the first time interval T0-T1. The smoothing capacitor C1DC is charged again by means of this current—specifically at least via the body diodes of the two primary-side switches QP1 and QP4, which can also be conductive to reduce losses. At time T3, the voltage on the clamping capacitor Cclamp has dropped again to almost zero.”], of transmitting power from the first port to the second port [e.g., transmitting power from port supplying V2DC to port supplying V1DC], with an efficiency of at least 90% [e.g., p. 0052 recites “For example, to charge a smoothing capacitor C1DC with a capacitance of 2 mF to an assumed voltage of the primary battery 12 of 475V, about 225 kJ of energy is required. Assuming an efficiency of 90%, the capacitance of the clamping capacitor Cclamp is found as:…”], the first port being at a first voltage [e.g., voltage level V2DC] and; and the system is capable, for a second set of control parameter values [e.g., -- refer to Fig. 5 --, control parameters corresponding to time interval T0 – T1, p. 0048 recites “FIG. 5 shows the switching state in step 56, which in the waveform diagram of FIG. 4 corresponds to a first time interval between times T0 and T1; the flow of current is shown by bold lines. During the time interval T0-T1, the secondary-side switches QS2 and QS3 are conductive, while the switches QS1 and QS4 are blocked. On the primary side, all MOSFET switches can be blocked since the current can flow via the body diodes of switches QP2 and QP3. However, it is also possible to close the switches QP2 and QP3 on the primary side in order to reduce losses.”], of transmitting power from the second port to the first port [e.g., transmitting power from port supplying V1DC to port supplying V2DC], with an efficiency of at least 90% [e.g., p. 0052 recites “For example, to charge a smoothing capacitor C1DC with a capacitance of 2 mF to an assumed voltage of the primary battery 12 of 475V, about 225 kJ of energy is required. Assuming an efficiency of 90%, the capacitance of the clamping capacitor Cclamp is found as:…”], the first port being at a first voltage [e.g., voltage level of V1DC]
Krause does not explicitly disclose the second port being at a voltage at least 50 times the first voltage; and the second port being at a voltage between 85 times the first voltage and 144 times the first voltage.
It would have been obvious to one of ordinary skill in the art before the effective filing date to modify Krause with the second port being at a voltage at least 50 times the first voltage; and the second port being at a voltage between 85 times the first voltage and 144 times the first voltage since it has been held that where the general conditions of a claim are disclosed in the prior art, discovering the optimum or workable ranges involves only routine skill in the art. In re Aller, 105 USPQ 233 (CCPA 1955).
Regarding claim 9, Krause [e.g., Figs. 1 – 8] discloses wherein a switch of the low-voltage switching circuit comprises two semiconductor switches connected in parallel [e.g., QS2 and QS4 connected in parallel].
Regarding claim 11, Krause [e.g., Figs. 1 – 8] discloses wherein the system is configured to operate over a range of switching frequencies extending from less than 350 kHz to more than 500 kHz [e.g., desired switching frequency 60kHZ (less than 30 kHZ), p. 0051 recites “The duration of the time interval T0-T1 is determined based on the resonance frequency, which in turn depends on the capacitance of the clamping capacitor Cclamp and the leakage inductance Lleak; or, conversely, the required capacitance of the clamping capacitor Cclamp is determined based on a desired switching frequency, for example 60 kHz.”]..
Claim(s) 2 and 3 are rejected under 35 U.S.C. 103 as being unpatentable over Krause et al (US Pub. No. 2021/0175793 A1) in view of Fu et al (US Patent No. 7,742,318 B1); (hereinafter Krause and Fu).
Regarding claim 2, Krause discloses the claimed invention except for wherein the low-voltage switching circuit comprises a circuit selected from the group consisting of half-bridge circuits and full-bridge circuits.
However, it would have been obvious to one of ordinary skill in the art before the effective filing date to modify Krause with wherein the low-voltage switching circuit comprises a circuit selected from the group consisting of half-bridge circuits and full-bridge circuits since similar primary side and secondary side structures such as half-bridge circuit and full-bridge circuits are commonly understood in the art and are often interchangeable. As disclosed by Fu et al [e.g., Figs. 24 and 26 - col. 9 lines 5 – 10 recites “Other implementations may extend to other types of primary and secondary side structures, such as full bridge, stacked half bridge and three-level structures and the like as will be apparent to those skilled in the art in view of the above discussion and the particular examples which will be discussed below in connection with FIGS. 24-34”.It continues on col. 9 lines 24 – 32 recites “Also, it should be appreciated that, whether or not a transformer is included in the tank circuit, the input and output circuits (e.g. the primary and secondary side structures may be freely chosen to accommodate any particular power or design requirements. For example, any of the exemplary circuits of FIGS. 24-28 can be used for the primary side input switch structure of FIG. 23 while any of the exemplary circuits of FIGS. 29-34 can be used as the secondary output or rectification side structure of FIG. 23.”].
Regarding claim 3, Krause discloses the claimed invention except for wherein the high-voltage switching circuit comprises a circuit selected from the group consisting of half-bridge circuits, center-tapped circuits, and full-bridge circuits.
However, it would have been obvious to one of ordinary skill in the art before the effective filing date to modify Krause with wherein the high-voltage switching circuit comprises a circuit selected from the group consisting of half-bridge circuits, center-tapped circuits, and full-bridge circuits since similar primary side and secondary side structures such as half-bridge circuits, center-tapped circuits, and full-bridge circuits are commonly understood in the art and are often interchangeable to accommodate for particular power or design requirements. As disclosed by Fu et al [e.g., Figs. 24 and 26 - col. 9 lines 5 – 10 recites “Other implementations may extend to other types of primary and secondary side structures, such as full bridge, stacked half bridge and three-level structures and the like as will be apparent to those skilled in the art in view of the above discussion and the particular examples which will be discussed below in connection with FIGS. 24-34”.It continues on col. 9 lines 24 – 32 recites “Also, it should be appreciated that, whether or not a transformer is included in the tank circuit, the input and output circuits (e.g. the primary and secondary side structures may be freely chosen to accommodate any particular power or design requirements. For example, any of the exemplary circuits of FIGS. 24-28 can be used for the primary side input switch structure of FIG. 23 while any of the exemplary circuits of FIGS. 29-34 can be used as the secondary output or rectification side structure of FIG. 23.”].
Claim(s) 4 and 5 are rejected under 35 U.S.C. 103 as being unpatentable over Krause et al (US Pub. No. 2021/0175793 A1) in view of Li et al (US Pub. No. 2025/0105730 A1); (hereinafter Krause and Li).
Regarding claim 4, Krause discloses the claimed invention except for an inductance-capacitance tank circuit comprising a resonant capacitor on a first side of the transformer, and a resonant inductor on a second side of the transformer, the second side being different from the first side.
Li teaches an inductance-capacitance tank circuit comprising a resonant capacitor on a first side of the transformer [e.g., Crs 265 on the right side of the transformer], and a resonant inductor on a second side of the transformer [e.g., Lrp 262 on the left side of the transformer], the second side being different from the first side [e.g., two separate sides divided by transformer T1].
It would have been obvious to one of ordinary skill in the art before the effective filing date to modify Krause with an inductance-capacitance tank circuit comprising a resonant capacitor on a first side of the transformer, and a resonant inductor on a second side of the transformer, the second side being different from the first side as suggested by Li to aid the circuit with zero voltage switching to minimize switching losses during operation.
Regarding claim 5, Krause discloses the claimed invention except for wherein the resonant capacitor is on a low-voltage side of the transformer, and the resonant inductor is on a high-voltage side of the transformer.
Li [ e.g., Fig. 2] teaches wherein the resonant capacitor is on a low-voltage side of the transformer [e.g., capacitors Crs connected to ports 291 (+135VDC), 292], and the resonant inductor is on a high-voltage side of the transformer [e.g., resonant inductor Lrp connected to ports 221 (800VDC) and 222 (800VDC)].
It would have been obvious to one of ordinary skill in the art before the effective filing date to modify Krause with wherein the resonant capacitor is on a low-voltage side of the transformer, and the resonant inductor is on a high-voltage side of the transformer as suggested by Li to aid the circuit with zero voltage switching to minimize switching losses during operation.
Claim(s) 6 is/are rejected under 35 U.S.C. 103 as being unpatentable over Krause et al (US Pub. No. 2021/0175793 A1) in view of Warren (US Pub. No. 2023/0402667 A1); (hereinafter Krause and Warren).
Regarding claim 6, Krause discloses the claimed invention except for wherein the system is capable of achieving a transmitted power density of at least 5 W per cubic inch.
Warren [e.g., Fig. 5] teaches wherein the system is capable of achieving a transmitted power density of at least 5 W per cubic inch [e.g., p. 0083 recites “The wide bandgap semiconductors may provide a high-frequency efficient power conversion system with reduced passive component footprints. In some embodiments, the DC-DC converters 520 exhibit a power density of 5 Watts per cubic inch. In some embodiments, the DC-DC converters 520 have dimensions of 2 inches by 5 inches by 2 inches. In some embodiments, the DC-DC converters 520 are up to 98% efficient at rated load and nominal state-of-charge conditions. Wide bandgap semiconductor-based power electronics in a high-gain DC-DC power converter system may result in high converter- and system-level efficiency, higher power density, improved reliability and greater margins of safety. Thus, an easily reconfigurable and scalable grid-integrated energy storage system is provided.”].
It would have been obvious to one of ordinary skill in the art before the effective filing date to modify Krause with wherein the system is capable of achieving a transmitted power density of at least 5 W per cubic inch as suggested by Warren for higher converter efficiency, higher power density, improved reliability and greater margins of safety.
Claim(s) 7 is/are rejected under 35 U.S.C. 103 as being unpatentable over Krause et al (US Pub. No. 2021/0175793 A1) in view of Phadke et al (US Pub. No. 2023/0368963 A1); (hereinafter Krause and Phadke).
Regarding claim 7, Krause discloses the claimed invention except for wherein the transformer is a high frequency planar transformer formed on a multi-layer printed circuit board, wherein: a first layer of the multi-layer printed circuit board comprises a turn of the second winding; a second layer of the multi-layer printed circuit board comprises a turn of the first winding; a third layer of the multi-layer printed circuit board comprises a turn of the second winding; and the second layer is between the first layer and the third layer.
Phadke [e.g., Figs. 2 and 6] teaches wherein the transformer is a high frequency planar transformer formed on a multi-layer printed circuit board [e.g., planar transformer], wherein: a first layer of the multi-layer printed circuit board comprises a turn of the second winding [e.g., winding layer P3, p. 0042 recites “Turning now to FIG. 6B, a cross-sectional view 600b is illustrated. Beginning from the top, layer 607a can be an additional insulation layer apart from the PCB itself, such as an insulating tape. This insulation layer can provide insulation for the winding layer P3 (the “first” layer described above) from components external to the PCB.”]; a second layer of the multi-layer printed circuit board comprises a turn of the first winding [e.g., secondary winding S1, p. 0042 recites “Below this layer is a further insulation layer 609, followed by the above-described “third” PCB layer, which includes secondary winding S2 and insulation 610.”]; a third layer of the multi-layer printed circuit board comprises a turn of the second winding [e.g., tertiary winding P4, p. 0042 recites “Further down is additional insulation layer 608, below which is the above-described “fourth” PCB layer including tertiary winding P4. As can be seen, via 606a connects the “first” and “fourth” PCB layers through all intermediate layers.”]; and the second layer is between the first layer and the third layer [e.g., layer containing winding S1 in between layer containing P3 and layer containing P4].
It would have been obvious to one of ordinary skill in the art before the effective filing date to modify Krause with wherein the transformer is a high frequency planar transformer formed on a multi-layer printed circuit board, wherein: a first layer of the multi-layer printed circuit board comprises a turn of the second winding; a second layer of the multi-layer printed circuit board comprises a turn of the first winding; a third layer of the multi-layer printed circuit board comprises a turn of the second winding; and the second layer is between the first layer and the third layer as suggested by Phadke to provide a compact and low profile transformer that is simple, and relatively inexpensive to build while minimizing the eddy current losses typically associated with the non-conducting winding during operation of the circuit.
15. Claim(s) 8 is/are rejected under 35 U.S.C. 103 as being unpatentable over Krause et al (US Pub. No. 2021/0175793 A1) in view of Gali (US Patent No. 5,084,664); (hereinafter Krause and Gali).
Regarding claim 8, Krause discloses the claimed invention except for wherein the second winding comprises at least eight times as many turns as the first winding.
However, it would have been obvious to one of ordinary skill in the art before the effective filing date to modify Krause with wherein the second winding comprises at least eight times as many turns as the first winding to arrive at a desired turn ratio between primary side and secondary side of the transformers, as commonly understood in the art. As disclosed by Gali [e.g., cols. 2 – 3 recites “The secondary coil 33 of transformer 29 has a higher turn ratio in the order of 6 (within the range of four to eight times) to 1 than the primary coil 28 such as to produce an output unloaded voltage in the range of some thirty to forty volts AC, …”]. Furthermore, since it has been held that where the general conditions of a claim are disclosed in the prior art, discovering the optimum or workable ranges involves only routine skill in the art. In re Aller, 105 USPQ 233 (CCPA 1955).
16. Claim(s) 10 is/are rejected under 35 U.S.C. 103 as being unpatentable over Krause et al (US Pub. No. 2021/0175793 A1) in view of Kucka et al (US Pub. No. 2025/0070773 A1); (hereinafter Krause and Kucka).
Regarding claim 10, Krause discloses the claimed invention except for a switching control circuit configured: to cause a first switch, of the low-voltage switching circuit, to turn on when a voltage across the first switch is less than 1% of an off state blocking voltage; and to cause a second switch, of the high-voltage switching circuit, to turn on when a voltage across the second switch is less than 1% of an off state blocking voltage.
However, it would have been obvious to one of ordinary skill in the art before the effective filing date to modify Krauser with a switching control circuit configured: to cause a first switch, of the low-voltage switching circuit, to turn on when a voltage across the first switch is less than 1% of an off state blocking voltage; and to cause a second switch, of the high-voltage switching circuit, to turn on when a voltage across the second switch is less than 1% of an off state blocking voltage to implement a zero voltage switching technique to minimize the switching the associated losses. As disclosed by Kucka, soft switching techniques such as zero current switching and zero voltage switching are understood in the art and commonly applied to similar circuits topology to minimize switching losses in the circuit during operation [e.g., p. 0005 recites “To reduce the GCT switching losses, soft-switching can be applied. Soft-switching implies additional measures and can be generally realized as zero-current switching (ZCS) or zero-voltage switching (ZVS). In the ZCS operation, the device's current (anode-cathode-current) is close to zero immediately before and after the switching instant happens. In contrast, in the ZVS operation, the device's blocking voltage (anode-cathode-voltage) is close to zero immediately before and after the switching instant happens. Since the switching loss of a device is roughly proportional to the product of the conducting current and blocking voltage, both ZVS and ZCS enable very low switching losses for the device.”].
17. Claim(s) 14 and 15 are rejected under 35 U.S.C. 103 as being unpatentable over Li et al (US Pub. No. 2025/0105730 A1) in view of Fu et al (US Patent No. 7,742,318 B1); (hereinafter Li and Fu).
Regarding claim 14, Li discloses the claimed invention except for wherein the low-voltage switching circuit comprises a circuit selected from the group consisting of half-bridge circuits and full-bridge circuits.
However, it would have been obvious to one of ordinary skill in the art before the effective filing date to modify Li with wherein the low-voltage switching circuit comprises a circuit selected from the group consisting of half-bridge circuits and full-bridge circuits since similar primary side and secondary side structures such as half-bridge circuit and full-bridge circuits are commonly understood in the art and are often interchangeable. As disclosed by Fu et al [e.g., Figs. 24 and 26 - col. 9 lines 5 – 10 recites “Other implementations may extend to other types of primary and secondary side structures, such as full bridge, stacked half bridge and three-level structures and the like as will be apparent to those skilled in the art in view of the above discussion and the particular examples which will be discussed below in connection with FIGS. 24-34”.It continues on col. 9 lines 24 – 32 recites “Also, it should be appreciated that, whether or not a transformer is included in the tank circuit, the input and output circuits (e.g. the primary and secondary side structures may be freely chosen to accommodate any particular power or design requirements. For example, any of the exemplary circuits of FIGS. 24-28 can be used for the primary side input switch structure of FIG. 23 while any of the exemplary circuits of FIGS. 29-34 can be used as the secondary output or rectification side structure of FIG. 23.”].
Regarding claim 15, Li discloses the claimed invention except for wherein the high-voltage switching circuit comprises a circuit selected from the group consisting of half-bridge circuits, center-tapped circuits, and full-bridge circuits.
However, it would have been obvious to one of ordinary skill in the art before the effective filing date to modify Li with wherein the high-voltage switching circuit comprises a circuit selected from the group consisting of half-bridge circuits, center-tapped circuits, and full-bridge circuits since similar primary side and secondary side structures such as half-bridge circuits, center-tapped circuits, and full-bridge circuits are commonly understood in the art and are often interchangeable to accommodate for particular power or design requirements. As disclosed by Fu et al [e.g., Figs. 24 and 26 - col. 9 lines 5 – 10 recites “Other implementations may extend to other types of primary and secondary side structures, such as full bridge, stacked half bridge and three-level structures and the like as will be apparent to those skilled in the art in view of the above discussion and the particular examples which will be discussed below in connection with FIGS. 24-34”. It continues on col. 9 lines 24 – 32 recites “Also, it should be appreciated that, whether or not a transformer is included in the tank circuit, the input and output circuits (e.g. the primary and secondary side structures may be freely chosen to accommodate any particular power or design requirements. For example, any of the exemplary circuits of FIGS. 24-28 can be used for the primary side input switch structure of FIG. 23 while any of the exemplary circuits of FIGS. 29-34 can be used as the secondary output or rectification side structure of FIG. 23.”].
18. Claim(s) 16 is/are rejected under 35 U.S.C. 103 as being unpatentable over Li et al (US Pub. No. 2025/0105730 A1) in view of Warren (US Pub. No. 2023/0402667 A1); (hereinafter Li and Warren).
Regarding claim 16, Li discloses the claimed invention except for wherein the system is capable of achieving a transmitted power density of at least 5 W per cubic inch.
Warren [e.g., Fig. 5] teaches wherein the system is capable of achieving a transmitted power density of at least 5 W per cubic inch [e.g., p. 0083 recites “The wide bandgap semiconductors may provide a high-frequency efficient power conversion system with reduced passive component footprints. In some embodiments, the DC-DC converters 520 exhibit a power density of 5 Watts per cubic inch. In some embodiments, the DC-DC converters 520 have dimensions of 2 inches by 5 inches by 2 inches. In some embodiments, the DC-DC converters 520 are up to 98% efficient at rated load and nominal state-of-charge conditions. Wide bandgap semiconductor-based power electronics in a high-gain DC-DC power converter system may result in high converter- and system-level efficiency, higher power density, improved reliability and greater margins of safety. Thus, an easily reconfigurable and scalable grid-integrated energy storage system is provided.”].
It would have been obvious to one of ordinary skill in the art before the effective filing date to modify Li with wherein the system is capable of achieving a transmitted power density of at least 5 W per cubic inch as suggested by Warren for higher converter efficiency, higher power density, improved reliability and greater margins of safety.
19. Claim(s) 17 is/are rejected under 35 U.S.C. 103 as being unpatentable over Li et al (US Pub. No. 2025/0105730 A1) in view of Phadke et al (US Pub. No. 2023/0368963 A1); (hereinafter Li and Phadke).
Regarding claim 17, Li discloses the claimed invention except for wherein the transformer is a high frequency planar transformer formed on a multi-layer printed circuit board, wherein: a first layer of the multi-layer printed circuit board comprises a turn of the second winding; a second layer of the multi-layer printed circuit board comprises a turn of the first winding; a third layer of the multi-layer printed circuit board comprises a turn of the second winding; and the second layer is between the first layer and the third layer.
Phadke [e.g., Figs. 2 and 6] teaches wherein the transformer is a high frequency planar transformer formed on a multi-layer printed circuit board [e.g., planar transformer], wherein: a first layer of the multi-layer printed circuit board comprises a turn of the second winding [e.g., winding layer P3, p. 0042 recites “Turning now to FIG. 6B, a cross-sectional view 600b is illustrated. Beginning from the top, layer 607a can be an additional insulation layer apart from the PCB itself, such as an insulating tape. This insulation layer can provide insulation for the winding layer P3 (the “first” layer described above) from components external to the PCB.”]; a second layer of the multi-layer printed circuit board comprises a turn of the first winding [e.g., secondary winding S1, p. 0042 recites “Below this layer is a further insulation layer 609, followed by the above-described “third” PCB layer, which includes secondary winding S2 and insulation 610.”]; a third layer of the multi-layer printed circuit board comprises a turn of the second winding [e.g., tertiary winding P4, p. 0042 recites “Further down is additional insulation layer 608, below which is the above-described “fourth” PCB layer including tertiary winding P4. As can be seen, via 606a connects the “first” and “fourth” PCB layers through all intermediate layers.”]; and the second layer is between the first layer and the third layer [e.g., layer containing winding S1 in between layer containing P3 and layer containing P4].
It would have been obvious to one of ordinary skill in the art before the effective filing date to modify Li with wherein the transformer is a high frequency planar transformer formed on a multi-layer printed circuit board, wherein: a first layer of the multi-layer printed circuit board comprises a turn of the second winding; a second layer of the multi-layer printed circuit board comprises a turn of the first winding; a third layer of the multi-layer printed circuit board comprises a turn of the second winding; and the second layer is between the first layer and the third layer as suggested by Phadke to provide a compact and low profile transformer that is simple, and relatively inexpensive to build while minimizing the eddy current losses typically associated with the non-conducting winding during operation of the circuit.
20. Claim(s) 18 is/are rejected under 35 U.S.C. 103 as being unpatentable over Li et al (US Pub. No. 2025/0105730 A1) in view of Gali (US Patent No. 5,084,664); (hereinafter Li and Gali).
Regarding claim 18, Li discloses the claimed invention except for wherein the second winding comprises at least eight times as many turns as the first winding.
However, it would have been obvious to one of ordinary skill in the art before the effective filing date to modify Li with wherein the second winding comprises at least eight times as many turns as the first winding to arrive at a desired turn ratio between primary side and secondary side of the transformers, as commonly understood in the art. As disclosed by Gali [e.g., cols. 2 – 3 recites “The secondary coil 33 of transformer 29 has a higher turn ratio in the order of 6 (within the range of four to eight times) to 1 than the primary coil 28 such as to produce an output unloaded voltage in the range of some thirty to forty volts AC, …”]. Furthermore, since it has been held that where the general conditions of a claim are disclosed in the prior art, discovering the optimum or workable ranges involves only routine skill in the art. In re Aller, 105 USPQ 233 (CCPA 1955).
Examiner’s Note
21. Examiner has cited particular columns, paragraphs and line numbers in the references applied to the claims above for the convenience of the applicant. Although the specified citations are representative of the teachings of the art and are applied to specific limitations within the individual claim, other passages and figure may apply as well. It is respectfully requested from the applicant in preparing responses, to fully consider the references in their entirety as potentially teaching all or part of the claimed invention, as well as the context of the passage as taught by the prior art disclosed by the Examiner.
22. In the case of amending the claimed invention, Applicant is respectfully requested to indicate the portion(s) of the specification which dictate(s) the structure relied on for proper interpretation and also to verify and ascertain the metes and bounds of the claimed invention.
Conclusion
23. The prior art made of record and not relied upon is considered pertinent to applicant's disclosure:
US Pub. No. 2023/0066489 A1 (Zou et al) discloses Systems and methods for controlling a dual active bridge converter or other type of DC-DC converter.
US Pub. No. 2023/0318467 A1 (Mobarrez et al) discloses the GHA method is performed concurrently while the power converter is operating.
US Pub. No. 2022/0321016 A1 (Khaligh et al) discloses the frequency domain generalized harmonic approximation (GHA) based optimal modulation strategy.
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/ULARISLAO CORDOVA/Examiner, Art Unit 2838
/FRED E FINCH III/Primary Examiner, Art Unit 2838
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