DETAILED ACTION
This action is in response to the Application filed on 04/26/2025.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Information Disclosure Statement
The information disclosure statement(s) (IDS) submitted on 04/26/2025 is/are in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement(s) is/are being considered by the examiner.
Specification
The lengthy specification has not been checked to the extent necessary to determine the presence of all possible minor errors. Applicant's cooperation is requested in correcting any errors of which applicant may become aware in the specification.
Claim Objections
Claim(s) 10 – 11 is/are objected to because of the following informalities:
Claim(s) 10 recite(s) “a plurality of control signals” in line 20. It appears that it should be “the plurality of control signals”.
Claim(s) 10 recite(s) “a first switch and a second switch” in lines 21 - 22. It appears that it should be “the first switch and the second switch”.
Claim(s) 11 recite(s) “generating a first control signal, a second control signal, a third control signal, and a fourth control signal by the signal generator”. Claim 10 recites “a signal generator configured to provide a plurality of control signals”. Therefore, claim 11 appears that should be “generating a first control signal, a second control signal, a third control signal, and a fourth control signal by the signal generator corresponding to the plurality of control signals”.
Claim 11 recite(s) “the third switch” and “the fourth switch” in lines 5 – 6. It appears that it should be “a third switch” and “a fourth switch”.
Appropriate correction is required.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries set forth in Graham v. John Deere Co., 383 U.S. 1, 148 USPQ 459 (1966), that are applied for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim(s) 1 – 4, 6, 8 and 10 – 14 is/are rejected under 35 U.S.C. 103 as being unpatentable over US Pub. No. 2021/0384836; (hereinafter Fujimoto), cited by Applicant(s) in view of US Pub. No. 2022/0255439; (hereinafter Chen).
Regarding claim 1, Fujimoto [e.g. Figs. 1 – 2] discloses a power converter, comprising: a first bridge arm comprising a first switch [e.g. 21] and a second switch [e.g. 22] connected in series at a first connection point [e.g. P1]; two transformers [e.g. 31-32], wherein two primary sides of the two transformers are connected in series and defined as a primary series winding [e.g. 311,321] coupled to the first connection point, and two secondary sides of the two transformers are connected in series and defined as a secondary series winding [e.g. 312,322]; a secondary side unit [e.g. 41,42] coupled to the secondary series winding; a signal generator [e.g. 60] configured to provide a plurality of control signals [e.g. control signals to 21 – 22] to the first switch and the second switch, respectively, so as to control at least one of a conduction state and conduction frequency of the first switch and the second switch [e.g. paragraph 065 recites “the controller 60 alternately performs on/off control with a dead-time period dt on the first switch 21 and the second switch 22”], and sets frequencies of the plurality of control signals [e.g. frequency shown in Fig. 2].
Fujimoto fails to disclose a frequency adjuster configured to provide a switching frequency correspondingly according to an input frequency and a frequency jitter value; wherein the signal generator receives the switching frequency and sets frequencies of the plurality of control signals according to the switching frequency; the frequency adjuster is configured to operate in one of a frequency increasing mode and a frequency decreasing mode; in the frequency increasing mode, the frequency jitter value is increased until the frequency jitter value reaches a predetermined maximum value, and then the frequency adjuster operates in the frequency decreasing mode; in the frequency decreasing mode, the frequency jitter value is reduced until the frequency jitter value reaches a predetermined minimum value, and then the frequency adjuster operates in the frequency increasing mode.
Chen [e.g. Fig. 4] teaches a frequency adjuster [e.g. 304] configured to provide a switching frequency [e.g. Vf1] correspondingly according to an input frequency [e.g. Vf] and a frequency jitter value [e.g. Vjitter1]; wherein the signal generator [e.g. 302] receives the switching frequency and sets frequencies [e.g. Vg] of the control signal according to the switching frequency; the frequency adjuster is configured to operate in one of a frequency increasing mode and a frequency decreasing mode [e.g. paragraph 021 recites “the jittering range of the operating frequency of power transistor S is adjusted to be increased within an upper limit of the first range by frequency jittering signal Vjitter1…the jittering range of the operating frequency of power transistor S is adjusted to be decreased within the lower limit of the first range by frequency jittering signal Vjitter1”]; in the frequency increasing mode, the frequency jitter value is increased until the frequency jitter value reaches a predetermined maximum value, and then the frequency adjuster operates in the frequency decreasing mode [e.g. paragraph 021 recites “the jittering range of the operating frequency of power transistor S is adjusted to be increased within an upper limit of the first range by frequency jittering signal Vjitter1…the jittering range of the operating frequency of power transistor S is adjusted to be decreased within the lower limit of the first range by frequency jittering signal Vjitter1”]; in the frequency decreasing mode, the frequency jitter value is reduced until the frequency jitter value reaches a predetermined minimum value, and then the frequency adjuster operates in the frequency increasing mode [e.g. paragraph 021 recites “the jittering range of the operating frequency of power transistor S is adjusted to be increased within an upper limit of the first range by frequency jittering signal Vjitter1…the jittering range of the operating frequency of power transistor S is adjusted to be decreased within the lower limit of the first range by frequency jittering signal Vjitter1”].
It would have been obvious to one having ordinary skill in the art before the effective filing date to modify Fujimoto by a frequency adjuster configured to provide a switching frequency correspondingly according to an input frequency and a frequency jitter value; wherein the signal generator receives the switching frequency and sets frequencies of the plurality of control signals according to the switching frequency; the frequency adjuster is configured to operate in one of a frequency increasing mode and a frequency decreasing mode; in the frequency increasing mode, the frequency jitter value is increased until the frequency jitter value reaches a predetermined maximum value, and then the frequency adjuster operates in the frequency decreasing mode; in the frequency decreasing mode, the frequency jitter value is reduced until the frequency jitter value reaches a predetermined minimum value, and then the frequency adjuster operates in the frequency increasing mode as taught by Chen in order of being able to reduce conduction loss and suppress electromagnetic radiation of power transistors.
Regarding claim 2, Fujimoto [e.g. Figs. 1 - 2] discloses wherein the power converter further comprises a second bridge arm [e.g. 23 - 24] connected in parallel to the first bridge arm; the second bridge arm comprises a third switch [e.g. 23] and a fourth switch [e.g. 24] ; the third switch and the fourth switch are connected in series at a second connection point [e.g. P2]; and the primary series winding is coupled between the first connection point and the second connection point [e.g. as shown].
Regarding claim 3, Fujimoto [e.g. Figs. 1 - 2] discloses wherein the signal generator generates a first control signal, a second control signal, a third control signal, and a fourth control signal to control the first switch, the second switch, the third switch, and the fourth switch, respectively [e.g. gate control signals to 21 – 24 output from GD1 – GD4]; the first control signal is complementary to the second control signal, and the third control signal is complementary to the fourth control signal [e.g. as shown in Fig. 2].
Regarding claim 4, Fujimoto [e.g. Figs. 1 - 2] discloses further comprising an input capacitor [e.g. 33] coupled to the second switch [e.g. via transistor 24], and the primary series winding is coupled between the first connection point [e.g. P1] and the input capacitor [e.g. 33, as shown].
Regarding claim 6, Fujimoto fails to disclose further comprising a voltage controller coupled to the signal generator to generate a control variable for the signal generator.
Chen [e.g. Fig. 4] teaches further comprising a voltage controller [e.g. 305, 301] coupled to the signal generator [e.g. 302] to generate a control variable [e.g. Vr] for the signal generator [e.g. to R input].
It would have been obvious to one having ordinary skill in the art before the effective filing date to modify Fujimoto by further comprising a voltage controller coupled to the signal generator to generate a control variable for the signal generator as taught by Chen in order of being able to reduce conduction loss and suppress electromagnetic radiation of power transistors.
Regarding claim 8, Fujimoto fails to disclose wherein the frequency adjuster comprises a frequency jitter controller and a comparator coupled to the frequency jitter controller; the frequency jitter controller is configured to output a frequency jitter value; and the comparator is configured to calculate a sum of the frequency jitter value and the switching frequency generated by the frequency adjuster.
Chen [e.g. Fig. 4] teaches wherein the frequency adjuster comprises a frequency jitter controller [e.g. 3031] and a comparator [e.g. 304] coupled to the frequency jitter controller; the frequency jitter controller is configured to output a frequency jitter value [e.g. Vjitter1]; and the comparator is configured to calculate a sum of the frequency jitter value and the switching frequency generated by the frequency adjuster [e.g. paragraph 025 recites “superposing circuit 304 can superimpose frequency jittering signal Vjitter1 on frequency control signal Vf to generate superposing signal Vf1”].
It would have been obvious to one having ordinary skill in the art before the effective filing date to modify Fujimoto by wherein the frequency adjuster comprises a frequency jitter controller and a comparator coupled to the frequency jitter controller; the frequency jitter controller is configured to output a frequency jitter value; and the comparator is configured to calculate a sum of the frequency jitter value and the switching frequency generated by the frequency adjuster as taught by Chen in order of being able to reduce conduction loss and suppress electromagnetic radiation of power transistors.
Regarding claim 10, Fujimoto [e.g. Figs. 1 – 2] discloses an operating method of a power converter, wherein the power converter comprises a first bridge arm comprising a first switch [e.g. 21] and a second switch [e.g. 22] connected in series at a first connection point [e.g. P1]; two transformers [e.g. 31-32], wherein two primary sides of the two transformers are connected in series and defined as a primary series winding [e.g. 311,321] coupled to the first connection point, and two secondary sides of the two transformers are connected in series and defined as a secondary series winding [e.g. 312,322]; a secondary side unit [e.g. 41,42] coupled to the secondary series winding; a signal generator [e.g. 60] configured to provide a plurality of control signals [e.g. control signals to 21 – 22] to the first switch and the second switch, respectively; setting frequencies of a plurality of control signals [e.g. frequency shown in Fig. 2]; and providing the plurality of control signals through the signal generator to the first switch and the second switch of the first bridge arm, respectively, so as to control at least one of a conduction state and conduction frequency of the first switch and the second switch [e.g. paragraph 065 recites “the controller 60 alternately performs on/off control with a dead-time period dt on the first switch 21 and the second switch 22”].
Fujimoto fails to disclose a frequency adjuster, the operating method comprising: operating the frequency adjuster in a frequency increasing mode and a frequency decreasing mode to make the frequency adjuster provide a switching frequency correspondingly according to an input frequency and a frequency jitter value; in the frequency increasing mode, the frequency jitter value is increased until the frequency jitter value reaches a predetermined maximum value, and then the frequency adjuster operates in the frequency decreasing mode; and in the frequency decreasing mode, the frequency jitter value is reduced until the frequency jitter value reaches a predetermined minimum value, and then the frequency adjuster operates in the frequency increasing mode; receiving the switching frequency through the signal generator and setting frequencies of a control signal according to the switching frequency.
Chen teaches a frequency adjuster [e.g. 304], the operating method comprising: operating the frequency adjuster in a frequency increasing mode and a frequency decreasing mode [e.g. paragraph 021 recites “the jittering range of the operating frequency of power transistor S is adjusted to be increased within an upper limit of the first range by frequency jittering signal Vjitter1…the jittering range of the operating frequency of power transistor S is adjusted to be decreased within the lower limit of the first range by frequency jittering signal Vjitter1”]to make the frequency adjuster provide a switching frequency [e.g. Vf1] correspondingly according to an input frequency [e.g. Vf] and a frequency jitter value [e.g. Vjitter1]; in the frequency increasing mode, the frequency jitter value is increased until the frequency jitter value reaches a predetermined maximum value, and then the frequency adjuster operates in the frequency decreasing mode [e.g. paragraph 021 recites “the jittering range of the operating frequency of power transistor S is adjusted to be increased within an upper limit of the first range by frequency jittering signal Vjitter1”] ; and in the frequency decreasing mode, the frequency jitter value is reduced until the frequency jitter value reaches a predetermined minimum value, and then the frequency adjuster operates in the frequency increasing mode [e.g. paragraph 021 recites “the jittering range of the operating frequency of power transistor S is adjusted to be decreased within the lower limit of the first range by frequency jittering signal Vjitter1”]; receiving the switching frequency [e.g. Vf1] through the signal generator [e.g. 302] and setting frequencies of a control signal [e.g. Vg] according to the switching frequency [e.g. through 302].
It would have been obvious to one having ordinary skill in the art before the effective filing date to modify Fujimoto by a frequency adjuster, the operating method comprising: operating the frequency adjuster in a frequency increasing mode and a frequency decreasing mode to make the frequency adjuster provide a switching frequency correspondingly according to an input frequency and a frequency jitter value; in the frequency increasing mode, the frequency jitter value is increased until the frequency jitter value reaches a predetermined maximum value, and then the frequency adjuster operates in the frequency decreasing mode; and in the frequency decreasing mode, the frequency jitter value is reduced until the frequency jitter value reaches a predetermined minimum value, and then the frequency adjuster operates in the frequency increasing mode; receiving the switching frequency through the signal generator and setting frequencies of a control signal according to the switching frequency as taught by Chen in order of being able to reduce conduction loss and suppress electromagnetic radiation of power transistors.
Regarding claim 11, Fujimoto [e.g. Figs. 1 - 2] discloses further comprising: generating a first control signal, a second control signal, a third control signal, and a fourth control signal [e.g. gate control signals to 21 – 24 output from GD1 – GD4] by the signal generator; and controlling the first switch, the second switch, the third switch, and the fourth switch, respectively by the first control signal, the second control signal, the third control signal, and the fourth control signal, wherein the first control signal is complementary to the second control signal [e.g. as shown in Fig. 2]., and the third control signal is complementary to the fourth control signal [e.g. as shown in Fig. 2].
Regarding claim 12, Fujimoto fails to disclose wherein the power converter comprises a voltage controller coupled to the signal generator, the operating method further comprising: generating a control variable for the signal generator by the voltage controller.
Chen [e.g. Fig. 4] teaches wherein the power converter comprises a voltage controller [e.g. 305, 301] coupled to the signal generator [e.g. 302], the operating method further comprising: generating a control variable [e.g. Vr] for the signal generator [e.g. to R input] by the voltage controller.
It would have been obvious to one having ordinary skill in the art before the effective filing date to modify Fujimoto by wherein the power converter comprises a voltage controller coupled to the signal generator, the operating method further comprising: generating a control variable for the signal generator by the voltage controller as taught by Chen in order of being able to reduce conduction loss and suppress electromagnetic radiation of power transistors.
Regarding claim 14, Fujimoto fails to disclose wherein the frequency adjuster comprises a frequency jitter controller and a comparator coupled to the frequency jitter controller, the operating method further comprising: outputting a frequency jitter value by the frequency jitter controller; and calculating a sum of the frequency jitter value and the switching frequency generated by the frequency adjuster through the comparator.
Chen [e.g. Fig. 4] teaches wherein the frequency adjuster comprises a frequency jitter controller [e.g. 3031] and a comparator [e.g. 304] coupled to the frequency jitter controller, the operating method further comprising: outputting a frequency jitter value [e.g. Vjitter1] by the frequency jitter controller; and calculating a sum of the frequency jitter value and the switching frequency generated by the frequency adjuster through the comparator [e.g. paragraph 025 recites “superposing circuit 304 can superimpose frequency jittering signal Vjitter1 on frequency control signal Vf to generate superposing signal Vf1”].
It would have been obvious to one having ordinary skill in the art before the effective filing date to modify Fujimoto by wherein the frequency adjuster comprises a frequency jitter controller and a comparator coupled to the frequency jitter controller, the operating method further comprising: outputting a frequency jitter value by the frequency jitter controller; and calculating a sum of the frequency jitter value and the switching frequency generated by the frequency adjuster through the comparator as taught by Chen in order of being able to reduce conduction loss and suppress electromagnetic radiation of power transistors.
Claim(s) 5 and 9 is/are rejected under 35 U.S.C. 103 as being unpatentable over Fujimoto in view of Chen and further in view of US Pub. No. 2024/0048061; (hereinafter Sasmal).
Regarding claim 5, Fujimoto [e.g. Figs. 1 - 2] discloses the primary series winding.
Fujimoto fails to disclose further comprising a first capacitor and a second capacitor connected in series at a second connection point and defined as a capacitor group connected in parallel to the first bridge arm; and the primary series winding is coupled between the first connection point and the second connection point.
Sasmal [e.g. Fig. 1] discloses further comprising a first capacitor [e.g. C1] and a second capacitor [e.g. C2] connected in series at a second connection point [e.g. B] and defined as a capacitor group connected in parallel to the first bridge arm [e.g. S1A, S1B]; and the primary winding [e.g. primary winding of transformer] is coupled between the first connection point and the second connection point [e.g. connected between nodes A and B].
It would have been obvious to one having ordinary skill in the art before the effective filing date to modify Fujimoto by further comprising a first capacitor and a second capacitor connected in series at a second connection point and defined as a capacitor group connected in parallel to the first bridge arm; and the primary series winding is coupled between the first connection point and the second connection point as taught by Sasmal in order of being able to maintain the input voltage.
Regarding claim 9, Fujimoto fails to disclose wherein the secondary side unit comprises a half-bridge rectifier circuit and an output capacitor; the output capacitor is coupled to the half-bridge rectifier circuit; and the output capacitor is configured to couple a load.
Sasmal [e.g. Fig. 1] teaches wherein the secondary side unit comprises a half-bridge rectifier circuit [e.g. S2A-S2B] and an output capacitor [e.g. Co]; the output capacitor is coupled to the half-bridge rectifier circuit [e.g. as shown]; and the output capacitor is configured to couple a load [e.g. Ro].
It would have been obvious to one having ordinary skill in the art before the effective filing date to modify Fujimoto by further comprising a first capacitor and a second capacitor connected in series at a second connection point and defined as a capacitor group connected in parallel to the first bridge arm; and the primary series winding is coupled between the first connection point and the second connection point as taught by Sasmal in order of being able to maintain the output voltage at a desired value.
Claim(s) 7 and 13 is/are rejected under 35 U.S.C. 103 as being unpatentable over Fujimoto in view of Chen and further in view of US Pub. No. 2016/0156259; (hereinafter Zhang).
Regarding claim 7, Fujimoto fails to disclose further comprising a subtractor coupled to the voltage controller; the subtractor is configured to receive a feedback voltage and a reference voltage to calculate an error value; the feedback voltage is generated according to an output voltage of the secondary side unit; and the reference voltage is corresponding to a reference voltage value of the output voltage.
Zhang [e.g. Fig. 3] teaches further comprising a subtractor [e.g. 2102] coupled to the voltage controller [e.g. 2101]; the subtractor is configured to receive a feedback voltage [e.g. VFB] and a reference voltage [e.g. VREF] to calculate an error value [e.g. output of 2101]; the feedback voltage is generated according to an output voltage of the secondary side unit [e.g. paragraph 053 recites “a voltage feedback signal VFB representing an output voltage of the secondary side”]; and the reference voltage is corresponding to a reference voltage value of the output voltage [e.g. it is well known in the art that the reference is used to be a reference of the comparing signal, in this case the output voltage].
It would have been obvious to one having ordinary skill in the art before the effective filing date to modify Fujimoto by further comprising a subtractor coupled to the voltage controller; the subtractor is configured to receive a feedback voltage and a reference voltage to calculate an error value; the feedback voltage is generated according to an output voltage of the secondary side unit; and the reference voltage is corresponding to a reference voltage value of the output voltage as taught by Zhang in order of being able to reduce electromagnetic interference (EMI).
Regarding claim 13, Fujimoto fails to disclose wherein the power converter comprises a subtractor coupled to the voltage controller, the operating method further comprising: receiving a feedback voltage and a reference voltage to calculate an error value by the subtractor, wherein the feedback voltage is generated according to an output voltage of the secondary side unit and the reference voltage is corresponding to a reference voltage value of the output voltage.
Zhang [e.g. Fig. 3] teaches wherein the power converter comprises a subtractor [e.g. 2102] coupled to the voltage controller [e.g. 2101], the operating method further comprising: receiving a feedback voltage [e.g. VFB] and a reference voltage[e.g. VREF] to calculate an error value [e.g. output of 2101] by the subtractor, wherein the feedback voltage is generated according to an output voltage of the secondary side unit [e.g. paragraph 053 recites “a voltage feedback signal VFB representing an output voltage of the secondary side”] and the reference voltage is corresponding to a reference voltage value of the output voltage [e.g. it is well known in the art that the reference is used to be a reference of the comparing signal, in this case the output voltage].
It would have been obvious to one having ordinary skill in the art before the effective filing date to modify Fujimoto by wherein the power converter comprises a subtractor coupled to the voltage controller, the operating method further comprising: receiving a feedback voltage and a reference voltage to calculate an error value by the subtractor, wherein the feedback voltage is generated according to an output voltage of the secondary side unit and the reference voltage is corresponding to a reference voltage value of the output voltage as taught by Zhang in order of being able to reduce electromagnetic interference (EMI).
Examiner's Note
Examiner has cited particular columns and line numbers in the references applied to the claims above for the convenience of the applicant. Although the specified citations are representative of the teachings of the art and are applied to specific limitations within the individual claim, other passages and figures may apply as well. It is respectfully requested from the applicant in preparing responses, to fully consider the references in their entirety as potentially teaching all or part of the claimed invention, as well as the context of the passage as taught by the prior art or disclosed by the Examiner.
In the case of amending the claimed invention, Applicant is respectfully requested to indicate the portion(s) of the specification which dictate(s) the structure relied on for proper interpretation and also to verify and ascertain the metes and bounds of the claimed invention.
Conclusion
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/ALEX TORRES-RIVERA/Primary Examiner, Art Unit 2838
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