/27/25DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Herein after “it would have been obvious” should be read as “it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention”.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1, 2, 12, 14-18 is/are rejected under 35 U.S.C. 103 as being unpatentable over Dubeyko et al PN 2019/0163493 in view of Diez et al PN 5,951,699 and Ahuja et al PN 2014/0173739.
In regards to claim 1: Dubeyko et al teaches a method for fault tolerant implementation (moving a failure is fault tolerance Abstract: “The first data processing unit may further be configured to determine occurrence of a process failure at the third data processing unit and re-assign the child process for execution”) of a mapping (routing [0106] “In some embodiments, DPUs 38 may be directly interconnected via wires, traces, or any other conductive means. These conductive means may allow routing of data and/or instructions from one DPU 38 to another”) of at least one input value to at least one output value ([0078] “As shown in FIG. 1, computing system 5 may include one or more data processing units (DPUs) 38A-38D (collectively, “DPUs 38”), one or more routers 40A-40J (collectively, “routers 40”), input interface 42, and output interface 44”) by a processing assembly having a plurality of processing units (DPUs 38), wherein the mapping (routing) having computational operations that can be evaluated by one or more of the processing units ([0077] “Processing units in some embodiments may be pre-fabricated in hardware to perform specific computations or data manipulations. For example, the processing units may be pre-fabricated with only specific circuit logic (such as ASICs) to perform a specific calculation. Alternatively, processing units may be programmable processing units that can be programmed dynamically to perform computations or data manipulations based on execution codes”) using a criteria to determine the error-free evaluation of the computations ([0006] The first data processing unit may be further configured to transmit a process termination message to the third data processing unit comprising instructions to terminate any further processing of the child process. In some embodiments, the first data processing unit is further configured to re-assign the child process to the fourth data processing unit on the basis of one or more re-assignment criteria. In some embodiments, one re-assignment criterion is the relative load of a respective data processing unit of the plurality of data processing units”) for error-free evaluation of the mapping (routing); wherein, when at least one processing unit has a malfunction (failure), at least,; and wherein the mapping (routing) is applied to input values (inputs), and wherein the selected at least one routing is evaluated in a modified manner or is not evaluated. Dubeyko et al does not teach critical structures or evaluating criticality. Diez et al teaches critical structures (Column 2 “Within the central software failure map 110, multiple critical structures 116 including system structures and optionally user structures are assigned a location. The critical structures 116 contain pointers 120 to the central software failure map 110, while the pointers 114 within the central software failure map 110 point to the multiple critical structures 116. The central software failure map 110 implemented in high-speed storage 106 typically is persistent from time of a system failure through the time that the system 100 is operational again”). It would have been obvious to include critical structures in the remapping because this would have included the structure as the criteria of Dubeyko et al. Diez et al includes critical structures in failure mapping but does not discuss calculating a degree of criticality. Ahuja et al teaches (Abstract “A criticality rating is automatically determined for the particular asset based at least in part on the set of attributes. A security activity is caused to be performed relating to the particular asset based on the automatically determined criticality rating of the particular asset” [0019] “Quantitative risk assessment, in some instances, can include the evaluation of both the magnitude of the potential impact (e.g., loss or harm) to an asset (e.g., as expressed through a criticality score or severity score for a threat, etc.), and the probability that an event will cause the impact”). It would have been score/measure/compute the criticality because this would have allowed for a degree of criticality to determine the most critical structure.
In regards to claim 2: Ahuja et al teaches a criticality score and criticality level ([0021] “ For instance, users can specify the criticality of individual assets, or groups of assets, for example, through a user interface. For example, a set of one or more assets can be selected and defined by the user as having a particular level of criticality based on the asset's position within a hierarchy, IP address, type of asset, etc. A criticality score mapped to the specified criticality level can then be defined for the asset(s).”). Ahuja et al also teaches selecting based upon higher or lower criticality ([0024] “Further, in some implementations, an assessment engine 244 can make use of a library of criticality assessment checks, each check adapted to check whether an asset possesses a respective characteristic evidencing higher (or lower) criticality, as defined, for instance, by a corresponding rule” [0040] “through the user-definition of rule thresholds, weights to be assigned to certain rules and attribute values triggering a higher or lower criticality assessment relative to other rules, how satisfaction (or violation) of a rule by asset attributes affects the asset's criticality rating, and so on”).
In regards to claim 12: Ahuja et al teaches criticality is computer taking into account components/resources. ([0011] “For instance, data collected describing attributes of the assets can be accessed and compared against criticality criteria, conditions, and rules (sometimes referred to herein collectively as "rules") to determine criticality ratings, scores, and scores of the assets. In some instances, criticality assessments can process asset data collected at the criticality assessment server 105 and/or included in other data stores of the environment.” … “For instance, an example security management server 115 can manage and control the scanning and analysis of devices, applications, network elements, storage elements, other components and resources, and users (collectively "assets") in the environment 100 to assess computing risk associated with individual assets, as well as the composite or aggregate risk in subsystems including two or more of the computing environment's assets, as well as the risk in the computing environment 100 as a whole.”).
In regards to claim 14: Dubeyko et al teaches determining the malfunction/failure of processing units.
In regards to claims 15-18: Dubeyko et al teaches hardware/software performing the functions of claim 1.
Claim(s) 3-5 is/are rejected under 35 U.S.C. 103 as being unpatentable over Dubeyko et al PN 2019/0163493 in view of Diez et al PN 5,951,699 and Ahuja et al PN 2014/0173739 as applied to claim 1 above, and further in view of Kim et al PN 2024/0338289.
In regards to claim 3: Dubeyko et al does not teach measuring the errors and determining if the measure of indicates an expected or maximum error. Kim et al teaches a measured error/error rate and determining if the error/fault rate exceeds a maximum/threshold ([0058] “Furthermore, the term of bad core means a faulty core, and wherein the faulty core includes the cases that the core is completely non-operational, and the error rate exceeds a certain threshold so that the care cannot be functioned”). It would have been obvious to determine if a measured an error rate is above a maximum/threshold because this would have allowed determine a core that is still functional is a faulty core.
In regards to claim 4: Kim et al teaches bypassing cores that have an error/fault rate above an error/fault rate threshold. ([0058] “Furthermore, the term of bad core means a faulty core, and wherein the faulty core includes the cases that the core is completely non-operational, and the error rate exceeds a certain threshold so that the care cannot be functioned”). ([0026] “It is characterized in that a method of performance harvesting in accordance with one embodiment of the present invention, comprises detecting bad core configured to detect fault in at least one or more of multiple cores in the device comprising at least one core group where the multiple cores are arranged in a matrix structure, and harvesting performance configured to bypass operations of at least one or more of the fault detected cores among the multiple cores and demonstrate the performance of the device with remaining normally operated cores without fault among the multiple cores”).
In regards to claim 5: Kim et al teaches fault information that includes error/fault rate ([0058] “For example, if a core exhibits a certain error rate in Built-In Self-Test (BIST) but passes specific functional tests, it may have a fault but might not be registered as a bad core and could still be used normally“) that is provided to function module (bad core manager) ([0073] “When operating the device, the MCU 200 reads fault information from the OTP (One-Time Programmable) part in the Bad Core Manager 125. The OTP part contains fault information discovered through BIST during chip manufacturing process”) that controls the routing/ bypassing ([0026] “It is characterized in that a method of performance harvesting in accordance with one embodiment of the present invention, comprises detecting bad core configured to detect fault in at least one or more of multiple cores in the device comprising at least one core group where the multiple cores are arranged in a matrix structure, and harvesting performance configured to bypass operations of at least one or more of the fault detected cores among the multiple cores and demonstrate the performance of the device with remaining normally operated cores without fault among the multiple cores”).
Claim(s) 6 is/are rejected under 35 U.S.C. 103 as being unpatentable over Dubeyko et al PN 2019/0163493 in view of Diez et al PN 5,951,699, Ahuja et al PN 2014/0173739 and Kim et al PN 2024/0338289 as applied to claim 3 above, and further in view of Masuda et al PN 5,165010.
In regards to claim 6: Kim et al teaches the system being AI ([0100]) but does not give any of the standard features of AI. Masuda et al teaches a neural network with failed neurons that ate zeroed out (Column 18 et. seq. “For the failure which exerts influence to only a small number of the neurons (functional blocks), it is possible to exclude the neurons susceptible to the influenced of failure by setting the weight values thereof to zero on the side of the normal neurons (functional blocks)”). Where the neural network has all the standard features including weights and multiplying by the weight. (Column 11 line 39 et. seq. “a multiplier 102 for multiplying an input signal thereto with the weight value”) and multiply-add operations (column 4 line 17 et. seq. “In another preferred embodiment of the invention, the inter-neuron data transmission is performed by using analogue signal, wherein determination of products and a sum thereof (multiplication and addition operation) is carried out through analogue calculation or alternatively the multiplication is carried out by an analogue calculation with the addition being performed by digital calculation”). It would have been obvious to bypass/zero out failed neurons in a standard neural network because this would have allowed for fault tolerance in a standard neural network.
Claim(s) 13 is/are rejected under 35 U.S.C. 103 as being unpatentable over Dubeyko et al PN 2019/0163493 in view of Diez et al PN 5,951,699 and Ahuja et al PN 2014/0173739 as applied to claim 1 above, and further in view of Brown et al PN 2013/0159799.
In regards to claim 13: Dubeyko et al teaches redirecting/remapping the processing units but does not teach a distribution mapping table Brown et al teaches ([0084] “Programming the chip may include, for example, accessing a mapping table and automatically disabling any faulty functional unit in a processing core identified as faulty. Programming may also include disabling a processing core entirely and/or remapping another processing core (e.g. a spare or redundant core) to handle the functions originally assigned to the faulty processing core”). It would have been obvious to store the faulty processor information ion a mapping table because this is a simple means of maintaining the faulty processor information.
Allowable Subject Matter
Claims 7-11, 19-20 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
In regards to claims 7 and 11: The examiner was unable to find a remapping of processors with reduced accuracy in each case and the correlation information related to the structure.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to PAUL R MYERS whose telephone number is (571)272-3639. The examiner can normally be reached telework M-F start 7-8 leave 4-5.
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/Paul R. MYERS/Primary Examiner, Art Unit 2176
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