DETAILED ACTION
Claims 1-16 are currently pending in the application and have been examined.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13.
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Claims 1-16 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1-18 of U.S. Patent No. 11,609,270, hereinafter ‘270. Although the claims at issue are not identical, they are not patentably distinct from each other because the claims of the current application have the same limitations as the claims of ‘270 with slightly rewording. For instance, claims 1 of ‘270 limitation “responsively to a clock-enable control, selectively disable toggling of an output of the storage element by gating a clock signal provided to the storage element” is implied by the present application’s claim 1. The following table shows an example of the mapping of the claims.
19/190,826
US-11609270
1. An Integrated Circuit (IC), comprising:
a storage element having an input and an output; and
control circuitry, configured to:
receive a clock-enable control; and
while the clock-enable control indicates that the output of the storage element is to be disabled from toggling, prevent an input of the storage element from toggling, by setting the input to a constant logic state.
1. An Integrated Circuit (IC), comprising:
a storage element; and
control circuitry, configured to:
responsively to a clock-enable control, selectively disable toggling of an output of the storage element by gating a clock signal provided to the storage element; and
while the clock-enable control indicates that the output of the storage element is to be disabled from toggling, prevent an input of the storage element from toggling, by setting the input to a constant logic state.
2. The IC according to claim 1, wherein: the storage element is a dual-latch Flip-Flop (FF) comprising a primary latch and a secondary latch, in gating a clock signal provided to the storage element, the control circuit is configured to set the primary latch to a transparent mode, and to prevent the input of the storage element from toggling, the control circuit is configured to set the input of the primary latch to the constant logic state.
2. The IC according to claim 1, wherein: the storage element is a dual-latch Flip-Flop (FF) comprising a primary latch and a secondary latch, in gating the clock signal, the control circuit is configured to set the primary latch to a transparent mode, and to prevent the input of the storage element from toggling, the control circuit is configured to set the input of the primary latch to the constant logic state.
3. The IC according to claim 1, wherein the storage element comprises one or more latches, and wherein, in setting the input to the constant logic state, the control circuitry is configured to prevent any of the latches from toggling while the output is disabled from toggling, regardless of whether or not the input of the storage element is toggling.
3. The IC according to claim 1, wherein the storage element comprises one or more latches, and wherein, in setting the input to the constant logic state, the control circuitry is configured to prevent any of the latches from toggling while the output is disabled from toggling, regardless of whether or not a functional-data input of the storage element is toggling.
4. The IC according to claim 1, wherein, to set the input to the constant logic state, the control circuitry comprises a logic gate configured to set the storage element to a scan mode in response to the clock-enable control disabling a clock signal provided to the storage element.
5. The IC according to claim 1, wherein, to set the input to the constant logic state, the control circuitry comprises a logic gate configured to set the storage element to a scan mode in response to the clock-enable control disabling the clock signal.
5. The IC according to claim 1, wherein the control circuitry comprises a logic gate, which is configured to set the input of the storage element to the constant logic state in response to the clock-enable control disabling a clock signal provided to the storage element.
6. The IC according to claim 1, wherein the control circuitry comprises a logic gate, which is configured to set the input of the storage element to the constant logic state in response to the clock-enable control disabling the clock signal.
Claims 1-10 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1-10 of U.S. Patent No. 12,287,370, hereinafter ‘370. Although the claims at issue are not identical, they are not patentably distinct from each other because the only limitation from ’370’s claims 1 and 6 that is missing from the current applications claims 1 and 6 are the limitation “without adding latency to a functional-data input”. An example of the claim mapping is shown in the following table.
19/190,826
US-12287370
1. An Integrated Circuit (IC), comprising:
a storage element having an input and an output; and
control circuitry, configured to:
receive a clock-enable control; and
while the clock-enable control indicates that the output of the storage element is to be disabled from toggling, prevent an input of the storage element from toggling, by setting the input to a constant logic state.
1. An Integrated Circuit (IC), comprising:
a storage element having an input and an output; and
control circuitry, configured to:
receive a clock-enable control; and
while the clock-enable control indicates that the output of the storage element is to be disabled from toggling, prevent an input of the storage element from toggling, without adding latency to a functional-data input of the storage element, by setting the input to a constant logic state.
2. The IC according to claim 1, wherein:
the storage element is a dual-latch Flip-Flop (FF) comprising a primary latch and a secondary latch, in gating a clock signal provided to the storage element, the control circuit is configured to set the primary latch to a transparent mode, and to prevent the input of the storage element from toggling, the control circuit is configured to set the input of the primary latch to the constant logic state.
2. The IC according to claim 1, wherein:
the storage element is a dual-latch Flip-Flop (FF) comprising a primary latch and a secondary latch, in gating a clock signal provided to the storage element, the control circuit is configured to set the primary latch to a transparent mode, and to prevent the input of the storage element from toggling, the control circuit is configured to set the input of the primary latch to the constant logic state.
3. The IC according to claim 1, wherein the storage element comprises one or more latches, and wherein, in setting the input to the constant logic state, the control circuitry is configured to prevent any of the latches from toggling while the output is disabled from toggling, regardless of whether or not the input of the storage element is toggling.
3. The IC according to claim 1, wherein the storage element comprises one or more latches, and wherein, in setting the input to the constant logic state, the control circuitry is configured to prevent any of the latches from toggling while the output is disabled from toggling, regardless of whether or not the functional-data input of the storage element is toggling.
4. The IC according to claim 1, wherein, to set the input to the constant logic state, the control circuitry comprises a logic gate configured to set the storage element to a scan mode in response to the clock-enable control disabling a clock signal provided to the storage element.
4. The IC according to claim 1, wherein, to set the input to the constant logic state, the control circuitry comprises a logic gate configured to set the storage element to a scan mode in response to the clock-enable control disabling a clock signal provided to the storage element.
5. The IC according to claim 1, wherein the control circuitry comprises a logic gate, which is configured to set the input of the storage element to the constant logic state in response to the clock-enable control disabling a clock signal provided to the storage element.
5. The IC according to claim 1, wherein the control circuitry comprises a logic gate, which is configured to set the input of the storage element to the constant logic state in response to the clock-enable control disabling a clock signal provided to the storage element.
A rejection based on double patenting of the “same invention” type finds its support in the language of 35 U.S.C. 101 which states that “whoever invents or discovers any new and useful process... may obtain a patent therefor...” (Emphasis added). Thus, the term “same invention,” in this context, means an invention drawn to identical subject matter. See Miller v. Eagle Mfg. Co., 151 U.S. 186 (1894); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Ockert, 245 F.2d 467, 114 USPQ 330 (CCPA 1957).
A statutory type (35 U.S.C. 101) double patenting rejection can be overcome by canceling or amending the claims that are directed to the same invention so they are no longer coextensive in scope. The filing of a terminal disclaimer cannot overcome a double patenting rejection based upon 35 U.S.C. 101.
Claims 11-16 are rejected under 35 U.S.C. 101 as claiming the same invention as that of claims 11-16 of prior U.S. Patent No. 12,287,370, hereinafter ‘370. This is a statutory double patenting rejection. A mapping of the claims are shown below.
19/190,826
US-12287370
11. An apparatus comprising a processor that comprises (i) fetch circuitry configured to fetch instructions and (ii) execute circuitry configured to execute instructions, wherein one or both of the fetch circuitry and the execute circuitry comprise:
a storage element having an input and an output; and
control circuitry, configured to:
receive a clock-enable control; and
while the clock-enable control indicates that the output of the storage element is to be disabled from toggling, prevent an input of the storage element from toggling, without adding latency to a functional-data input of the storage element, by setting the input to a constant logic state.
11. An apparatus comprising a processor that comprises (i) fetch circuitry configured to fetch instructions and (ii) execute circuitry configured to execute instructions, wherein one or both of the fetch circuitry and the execute circuitry comprise:
a storage element having an input and an output; and
control circuitry, configured to:
receive a clock-enable control; and
while the clock-enable control indicates that the output of the storage element is to be disabled from toggling, prevent an input of the storage element from toggling, without adding latency to a functional-data input of the storage element, by setting the input to a constant logic state.
12. The apparatus according to claim 11, further comprising a display device and one or more input devices.
12. The apparatus according to claim 11, further comprising a display device and one or more input devices.
13. The apparatus according to claim 11, wherein: the storage element is a dual-latch Flip-Flop (FF) comprising a primary latch and a secondary latch, in gating a clock signal provided to the storage element, the control circuit is configured to set the primary latch to a transparent mode, and to prevent the input of the storage element from toggling, the control circuit is configured to set the input of the primary latch to the constant logic state.
13. The apparatus according to claim 11, wherein: the storage element is a dual-latch Flip-Flop (FF) comprising a primary latch and a secondary latch, in gating a clock signal provided to the storage element, the control circuit is configured to set the primary latch to a transparent mode, and to prevent the input of the storage element from toggling, the control circuit is configured to set the input of the primary latch to the constant logic state.
14. The apparatus according to claim 11, wherein the storage element comprises one or more latches, and wherein, in setting the input to the constant logic state, the control circuitry is configured to prevent any of the latches from toggling while the output is disabled from toggling, regardless of whether or not the functional-data input is toggling.
14. The apparatus according to claim 11, wherein the storage element comprises one or more latches, and wherein, in setting the input to the constant logic state, the control circuitry is configured to prevent any of the latches from toggling while the output is disabled from toggling, regardless of whether or not the functional-data input is toggling.
15. The apparatus according to claim 11, wherein, to set the input to the constant logic state, the control circuitry comprises a logic gate configured to set the storage element to a scan mode in response to the clock-enable control disabling a clock signal provided to the storage element.
15. The apparatus according to claim 11, wherein, to set the input to the constant logic state, the control circuitry comprises a logic gate configured to set the storage element to a scan mode in response to the clock-enable control disabling a clock signal provided to the storage element.
16. The apparatus according to claim 11, wherein the control circuitry comprises a logic gate, which is configured to set the input of the storage element to the constant logic state in response to the clock-enable control disabling a clock signal provided to the storage element.
16. The apparatus according to claim 11, wherein the control circuitry comprises a logic gate, which is configured to set the input of the storage element to the constant logic state in response to the clock-enable control disabling a clock signal provided to the storage element.
Allowable Subject Matter
Claims 1-16 would be allowable if rewritten or amended to overcome the nonstatutory double patenting rejection and the statutory type (35 U.S.C. 101) double patenting rejection, set forth in this Office action. None of the prior art teaches nor makes obvious the limitation “while the clock-enable control indicates that the output of the storage element is to be disabled from toggling, prevent an input of the storage element from toggling, by setting the input to a constant logic state”.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. Ramaraju et al. (US-7843218) teaches turning now to FIG. 3, there is depicted a multiplexed flip-flop 300 in which a storage cell 340 is separately clocked with a master clock MCLOCK and a slave clock SCLOCK that are applied to the L1 master latch 320 and L2 slave latch 330, respectively. In the depicted flip-flop 300, the slave latch 330 is transparent when the clock signal 351 is low (and inverted by inverter 356), and the master latch 320 is transparent when the clock signal 351 is high, resulting in a negative edge triggered flip-flop implementation whereby the flip-flop output Q 332 changes when the clock signal 351 falls. However, and as described herein, selected embodiments of the present invention may also be implemented as positive edge flip-flops by adjusting the clock generation circuitry. The multiplexed flip-flop 300 includes an input multiplexer 310 for choosing between functional data input D and scan data input I based on a control input scan enable SE 311. The multiplexer 310 conveys the chosen input to the multiplexer output 321 which is connected to the L1 master latch 320 which is clocked by the input master CLOCK signal (or MCLOCK) on line 311. In turn, the output 331 of the L1 master latch 320 is connected to the data input of the L2 slave latch 330 which is clocked with the output 333 of the slave clock multiplexer 358 to launch output data Q on the output 332. As shown in FIG. 3, the input clock signal CLOCK 351 is applied directly as the master clock MCLOCK to the L1 master latch 320 for both functional and scan modes. However, the slave clock SCLOCK for the L2 slave latch 330 is generated by the slave clock multiplexer 358 which, based on a control input scan enable SE 311, chooses between the multiplexer inputs 357, 359. The first multiplexer input 357 is an inverted master clock MCLOCK (MCLOCKB) that is generated by the inverter 356. The other multiplexer input 359 is a second clock signal BCLOCK that is generated by a clock or pulse generator circuit 350. The clock/pulse generator circuit 350 includes logic gate and inverter circuits for generating the second clock signal BCLOCK that has a DC state during the functional mode, and that switches during the scan mode to have rising edges that are delayed with respect to the falling edges of the input clock signal CLOCK. In an example implementation, the clock/pulse generator circuit 350 includes an NOR gate 353 which receives the input clock signal CLOCK and the delayed version of the input clock signal CLOCK generated by the delay element 352, and generates therefrom a pulse signal which is applied as an input 354 to the OR gate 355 which also receives an inverted version of the scan enable SE 311. Based on these inputs, the OR gate 355 generates the second clock signal BCLOCK 359. (Col. 4, ll. 4-52, Fig. 3).
Any inquiry concerning this communication or earlier communications from the examiner should be directed to JOHN J TABONE JR whose telephone number is (571)272-3827. The examiner can normally be reached M-F 9 AM to 7 PM EST.
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/JOHN J TABONE JR/Primary Examiner, Art Unit 2111 07/24/2026
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