Prosecution Insights
Last updated: October 02, 2026
Application No. 19/190,895

TEMPERATURE COMPENSATION CIRCUIT, SEMICONDUCTOR INTEGRATED CIRCUIT, SEMICONDUCTOR DEVICE, AND TEMPERATURE COMPENSATION METHOD

Non-Final OA §102§103§112
Filed
Apr 28, 2025
Priority
Jul 13, 2023 — JP 2023-115515 +1 more
Examiner
CLARK, CHRISTOPHER JAY
Art Unit
Tech Center
Assignee
Kabushiki Kaisha Toshiba
OA Round
1 (Non-Final)
76%
Grant Probability
Favorable
1-2
OA Rounds
1y 4m
Est. Remaining
99%
With Interview

Examiner Intelligence

Grants 76% — above average
76%
Career Allowance Rate
574 granted / 757 resolved
+15.8% vs TC avg
Strong +23% interview lift
Without
With
+22.8%
Interview Lift
resolved cases with interview
Typical timeline
2y 9m
Avg Prosecution
21 currently pending
Career history
770
Total Applications
across all art units

Statute-Specific Performance

§101
0.5%
-39.5% vs TC avg
§103
50.9%
+10.9% vs TC avg
§102
27.9%
-12.1% vs TC avg
§112
17.7%
-22.3% vs TC avg
Black line = Tech Center average estimate • Based on career data from 757 resolved cases

Office Action

§102 §103 §112
DETAILED ACTION Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Claim Objections Claim 10 is objected to because of the following informalities: CLAIM 10: In line 10, replace “a” with --the--. In line 11, replace “a” before “second” with --the--. In line 11, replace “an” before “output” with --the--. In line 11, replace “node,” with --node of the voltage supply circuit,”. In line 12, replace “a” with --the--. In line 14, replace “a” with --the--. In line 15, after “output node” insert --of the voltage supply circuit--. Appropriate correction is required. Claim Rejections - 35 USC § 112 Claims 1-11 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention. In re Claim 1, lines 10-12 describe a comparator circuit including the first input node and the second input node of the correction circuit, presumably. However, as seen in Figure 1 of the instant application, the first and second input (41a and 41b) of the correction circuit 41 are not included in the comparator 31. This inconsistency between the claims and the specification raises an issue of indefiniteness. Claims 2-11 are rejected due to their dependence on claim 1. For the purpose of examination claim 1 will be interpreted as follows: CLAIM 1: In line 11, replace “the” before “first” with --a--. In line 12, after “node” insert --of the comparator--. Claim Rejections - 35 USC § 102 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention. Claim(s) 1-3, 6, 7, and 12-14 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Oishi (JP 2019192950A with reference made to included translation). In re Claim 1, Oishi teaches a temperature compensation circuit as seen in Figure 1, comprising: a correction circuit (32) that includes a first input node (inputting T), a second input node (inputting Vgs), and an output node (outputting Vth), the first input node being connected to a temperature sensor (31, page 3 paragraph 1) near a power device (10, page 3 paragraph 1), the second input node being connected to a control terminal of the power device (via 20, page 3 paragraph 2); and a voltage supply circuit (33c) that includes an input node and an output node, the input node being connected to the output node of the correction circuit, the output node being connected to a second input node (Vinn) of a comparator circuit (33d) that includes a first input node (Vinp) and the second input node, the first input node being connected to one end of the power device (via 33b). In re Claim 2, Oishi teaches the correction circuit generates a correction signal that corresponds to a temperature of the power device, and a voltage of the control terminal (Pages 3-5), and the voltage supply circuit corrects a threshold voltage in response to the correction signal, and supplies the threshold voltage that has been corrected to the second input node of the comparator circuit (page 5 paragraph 2). In re Claim 3, the voltage supply circuit does not correct a threshold voltage during a first period when the comparator circuit outputs a first comparison result (such as when the compensation circuit is in an OFF state), and corrects the threshold voltage during a second period when the comparator circuit outputs a second comparison result (such as when the compensation circuit is in an ON state (Page 5). In re Claim 6, Oishi teaches the correction circuit generates a first correction signal in a case where a temperature of the power device is a first temperature (T1), and a voltage of the control terminal is a first voltage (Vgs1), and generates a second correction signal in a case where the temperature of the power device is a second temperature (T2) that is higher than the first temperature, and the voltage of the control terminal is the first voltage (Vgs1), and the voltage supply circuit corrects a level of a threshold voltage (corresponding to Ith1) to a first level in response to the first correction signal, and corrects the level of the threshold voltage to a second level (corresponding to Ith2) in response to the second correction signal, the second level being lower than the first level (Figures 3 and 4, page 4). In re Claim 7, Oishi teaches the first level corresponds to a rated current of the power device at the first temperature, and the second level corresponds to the rated current of the power device at the second temperature (page 4 paragraph 1). In re Claim 12, see discussion of claims 1 and 2. In re Claim 13, see discussion of claim 6. In re Claim 14, see discussion of claim 7. Claim Rejections - 35 USC § 103 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. Claim(s) 5 is/are rejected under 35 U.S.C. 103 as being unpatentable over Oishi (JP 2019192950A with reference made to included translation) in view of Huber (2018/0183228). In re Claim 5, Oishi teaches that the correction circuit 32 receives an input voltage from the temperature detector 31 and the gate voltage as an input voltage and includes an information conversion circuit holding correction information in which temperature, a voltage of the control terminal, and a threshold voltage have been associated with each other for a plurality of combinations of the temperature and the voltage of the control terminal to output threshold signal Vth (page 5 paragraphs 5 and 6). Oishi does not specifically teach the AD conversions circuits and DA conversion circuit. Huber teaches as seen in Figure 4A utilizing an AD converter 222 to providing a digital representation of an input voltage to a logic circuit 220 utilized to determine a threshold voltage THdes based on said input voltage (paragraphs 41-42). Huber also teach utilizing a DA converter 224 to output the determined threshold voltage signal (paragraph 43). It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to utilize an AD converter as taught by Huber for each input voltage (temperature and gate voltage) of the correction circuit of Oishi since Huber teaches that doing so would allow the correction circuit to obtain a digital representation of said input voltages to determine the threshold voltage. It also would have been obvious to utilize a DA converter as taught by Huber to output the threshold signal Vth from the correction circuit of Oishi. Claim(s) 10 and 11 is/are rejected under 35 U.S.C. 103 as being unpatentable over Oishi (JP 2019192950A with reference made to included translation) in view of Bachhuber (2020/0228109). In re Claim 10, Oishi teaches the comparator 33d outputs a signal S2 to a driver 20 to turn off switch 10 and the controller 32 outputs an input signal S1 to the driver 20 to drive switch 10 on and off (page 2 paragraph 4). Oishi does not specifically teach a signal generation circuit and driving circuit as claimed. Bachhuber teaches as seen in Figure 4 how to control a switch 201 based on the output of a comparator 195 detecting a fault condition and an input signal PWM_IN in a driver 180. Bachhuber teaches utilizing a signal generation circuit 199 and a driving circuit 181 in the driver to provide said control of switch 201 (paragraph 42). It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to include the signal generation circuit 199 and driving circuit 181 as taught by Bachhuber in the driver 20 of Oishi since Bachhuber teaches that by doing so the control of switch 10 based on inputs S1 and S2 can be facilitated. In re Claim 11, Oishi teaches a rectifying element 33b. Allowable Subject Matter Claims 4, 8, and 9 would be allowable if rewritten to overcome the rejection(s) under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), 2nd paragraph, set forth in this Office action and to include all of the limitations of the base claim and any intervening claims. Claims 15 and 16 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. In re Claim 4, Oishi fails to teach the correction circuit includes: a first amplifier that has a variable gain, and includes an input node that is connected to the temperature sensor near the power device, and an output node; a second amplifier that has the variable gain, and includes an input node that is connected to the control terminal of the power device, and an output node; and a signal generation circuit that includes a first input node that is connected to the output node of the first amplifier, a second input node that is connected to the output node of the second amplifier, and an output node. In re Claims 8, 9, 15, and 16, Oishi teaches the correction circuit generates a first correction signal in a case where a temperature of the power device is a first temperature (T1), and a voltage of the control terminal is a first voltage (Vgs1), and generates a third correction signal in a case where the temperature of the power device is a second temperature (T2) that is higher than the first temperature, and the voltage of the control terminal is the first voltage (Vgs1), and the voltage supply circuit corrects a level of a threshold voltage to a first level (corresponding to Ith1) in response to the first correction signal, and corrects the level of the threshold voltage to a third level (corresponding to Ith2) in response to the third correction signal, the third level being lower than the first level (Figures 3 and 4, page 4). Oishi fails to teach that the third level is higher than the first level. Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to CHRISTOPHER JAY CLARK whose telephone number is (571)270-1427. The examiner can normally be reached Monday - Friday, 10:00am - 6:00pm EST. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Thienvu Tran can be reached at 571-270-1276. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /CHRISTOPHER J CLARK/Examiner, Art Unit 2838 /THIENVU V TRAN/Supervisory Patent Examiner, Art Unit 2838
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Prosecution Timeline

Apr 28, 2025
Application Filed
Sep 22, 2026
Non-Final Rejection mailed — §102, §103, §112 (current)

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Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

1-2
Expected OA Rounds
76%
Grant Probability
99%
With Interview (+22.8%)
2y 9m (~1y 4m remaining)
Median Time to Grant
Low
PTA Risk
Based on 757 resolved cases by this examiner. Grant probability derived from career allowance rate.

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