Prosecution Insights
Last updated: August 17, 2026
Application No. 19/190,957

EQUALIZATION SIGNAL PROCESSING CIRCUIT, RECEIVER, AND EQUALIZATION SIGNAL PROCESSING METHOD

Non-Final OA §101
Filed
Apr 28, 2025
Priority
May 17, 2024 — JP 2024-080858
Examiner
MALEK, LEILA
Art Unit
Tech Center
Assignee
NEC Corporation
OA Round
1 (Non-Final)
80%
Grant Probability
Favorable
1-2
OA Rounds
1y 6m
Est. Remaining
87%
With Interview

Examiner Intelligence

Grants 80% — above average
80%
Career Allowance Rate
558 granted / 700 resolved
+19.7% vs TC avg
Moderate +8% lift
Without
With
+7.6%
Interview Lift
resolved cases with interview
Typical timeline
2y 10m
Avg Prosecution
13 currently pending
Career history
721
Total Applications
across all art units

Statute-Specific Performance

§101
9.2%
-30.8% vs TC avg
§103
48.0%
+8.0% vs TC avg
§102
14.9%
-25.1% vs TC avg
§112
19.5%
-20.5% vs TC avg
Black line = Tech Center average estimate • Based on career data from 700 resolved cases

Office Action

§101
DETAILED ACTION Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Priority Acknowledgment is made of applicant’s claim for foreign priority under 35 U.S.C. 119 (a)-(d). Information Disclosure Statement The information disclosure statement submitted on 04/28/2025 has been considered and made of record by the examiner. Specification The lengthy specification has not been checked to the extent necessary to determine the presence of all possible minor errors. Applicant’s cooperation is requested in correcting any errors of which applicant may become aware in the specification. Claim Rejections - 35 USC § 101 35 U.S.C. 101 reads as follows: Whoever invents or discovers any new and useful process, machine, manufacture, or composition of matter, or any new and useful improvement thereof, may obtain a patent therefor, subject to the conditions and requirements of this title. Claims 1-14 are rejected under 35 U.S.C. 101 because the claimed invention is directed to an abstract idea (mathematical concepts) without significantly more. Claims 1, 8, and 14 recite an equalization signal processing circuit/method for dividing, into M signals, an input signal of oversampling of a rational number M/L multiple in which M and L are natural numbers satisfying 1<M/L<2, converting each of the divided M signals into a signal in a frequency domain, in a first frequency domain filter, performing an arithmetic operation of a first filter coefficient on M signals converted into a signal in the frequency domain, in a second frequency domain filter, performing an arithmetic operation of a second filter coefficient on, for each L group, M signals on which the arithmetic operation of the first filter coefficient is performed, adding, for each group, M signals on which the arithmetic operation of the second filter coefficient is performed, converting, for each group, the added output signal into a signal in a time domain, sequentially selecting, for each group, a signal converted into a signal in the time domain, and calculating a gradient of a loss function for the first filter coefficient and a gradient of the loss function for the second filter coefficient by using an error back propagation method, by using, as the loss function, a magnitude of a difference between the sequentially selected signal and a predetermined value, and updating the first filter coefficient and the second filter coefficient. The steps of dividing an input signal, converting each of the divided signals into a signal in a frequency domain, performing arithmetic operations, adding M signals, sequentially selecting a signal into a signal in the time domain, and calculating a gradient of a loss function for the first filter coefficients and second filter coefficients by using an error back propagation method, and updating the first filter coefficient and the second filter coefficient, are all mathematical concepts that can be executed using mathematical formulas. According to the Court, concepts determined to be abstract ideas and, thus, patent ineligible, include certain methods of organizing human activity, such as fundamental economic practices (Alice, 573 U.S. at 219-20; Bilski, 561 U.S. at 611); mathematical formulas (Parker V. Flook, 437 U.S. 584, 594-95 (1978)), and mental processes (Gottschalk V. Benson, 409 U.S. 63,67 (1972)). The equalization signal processing circuit cited in the preamble of claim 1, the memory, and the processor cited in the body of claim 1 are general purpose computer components. The memory and the processor cited in the body of claim 8 are general purpose computer components. The detector, cited in claim 8, is a general- purpose computer component used for data gathering. The equalization signal processing circuit cited in claim 8 can also be a component in a general-purpose computer that executes a set of mathematical steps. The cited claim limitations do not improve the functionality of the general-purpose computer system. Therefore, the claims as a whole are directed to an abstract idea. This judicial exception is not integrated into practical application, because the claims recite only a generic well- known computer component as additional elements (e.g., a memory and a processor). As explained above, the claims do not include additional elements that are sufficient to amount to significantly more than the judicial exception because the additional components, as cited in claims 1 and 8, are recited at a high-level of generality such that it amounts no more than mere instructions to apply the exception using a generic computer component. Accordingly, these additional elements do not integrate the abstract idea into a practical application because they do not impose any meaningful limits on practicing the abstract idea. Claims 1, 8, and 14 are directed to an abstract idea, because the claim limitations cited in these claims only generally link the use of the judicial exception to a particular technological environment or field of use and do not meaningfully limit these claims, thus do not transform the claims into patent-eligible subject matter. Claims 2-7 and 9-13 are also directed to an abstract idea, similar to claims 1 and 8 as explained above. The limitations cited in claims 2-7 and 9-13 only generally link the use pf the judicial exception to a particular technological environment or field of use and do not meaningfully limit these claims thus do not transform these claims into patent-eligible subject matter. Conclusion The prior art made of record and not relied upon is considered pertinent to applicant's disclosure (US 2023/0130197) and (US 2022/0385374). Any inquiry concerning this communication or earlier communications from the examiner should be directed to LEILA MALEK whose telephone number is (571)272-8731. The examiner can normally be reached Monday-Friday 8:30am-4:30pm. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Chieh Fan can be reached at 571-272-3042. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. LEILA . MALEK Examiner Art Unit 2632 /LEILA MALEK/Primary Examiner, Art Unit 2632
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Prosecution Timeline

Apr 28, 2025
Application Filed
Aug 06, 2026
Non-Final Rejection mailed — §101 (current)

Precedent Cases

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Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

1-2
Expected OA Rounds
80%
Grant Probability
87%
With Interview (+7.6%)
2y 10m (~1y 6m remaining)
Median Time to Grant
Low
PTA Risk
Based on 700 resolved cases by this examiner. Grant probability derived from career allowance rate.

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