DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Double Patenting
A rejection based on double patenting of the “same invention” type finds its support in the language of 35 U.S.C. 101 which states that “whoever invents or discovers any new and useful process... may obtain a patent therefor...” (Emphasis added). Thus, the term “same invention,” in this context, means an invention drawn to identical subject matter. See Miller v. Eagle Mfg. Co., 151 U.S. 186 (1894); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Ockert, 245 F.2d 467, 114 USPQ 330 (CCPA 1957).
A statutory type (35 U.S.C. 101) double patenting rejection can be overcome by canceling or amending the claims that are directed to the same invention so they are no longer coextensive in scope. The filing of a terminal disclaimer cannot overcome a double patenting rejection based upon 35 U.S.C. 101.
Claim comparison table
Claims of Application# 19/191,177
Claims of U.S. Patent# 12,288,520
1. A CMOS-like logic gate comprising: a set of thin-film-transistors (TFTs), the set of TFTs including a subset of pull down TFTs, a subset of diode-connected TFTs and an output pull-up transistor; and a capacitor; wherein the subset of diode-connected TFTs, the output pull-up transistor and the capacitor are positioned to provide a bootstrapped feedback network to provide full-output swing; and wherein the subset of diode-connected TFTs and one of the subset of pull-down TFTs form a leakage current path; and wherein at least one of the subset of pull-down TFTs is connected to a first input.
1. A CMOS-like logic gate comprising: a set of thin-film-transistors (TFTs), the set of TFTs including a subset of pull down TFTs, a subset of diode-connected TFTs and an output pull-up transistor; and a capacitor; wherein the subset of diode-connected TFTs, the output pull-up transistor and the capacitor are positioned to provide a bootstrapped feedback network to provide full-output swing; and wherein the subset of diode-connected TFTs and one of the subset of pull-down TFTs form a leakage current path; and wherein at least one of the subset of pull-down TFTs is connected to a first input.
2. The CMOS-like logic gate of claim 1 wherein a width of the pull-down TFT in the leakage current path is less than a width of the other TFTs in the set of TFTs to reduce static leakage current.
2. The CMOS-like logic gate of claim 1 wherein a width of the pull-down TFT in the leakage current path is less than a width of the other TFTs in the set of TFTs to reduce static leakage current.
3. The CMOS-like logic gate of claim 1 wherein the capacitor is positioned between the set of diode-connected TFTs and a signal output.
3. The CMOS-like logic gate of claim 1 wherein the capacitor is positioned between the set of diode-connected TFTs and a signal output.
4. The CMOS-like logic gate of claim 1 wherein the subset of pull-down TFTs are connected to a signal input.
4. The CMOS-like logic gate of claim 1 wherein the subset of pull-down TFTs are connected to a signal input.
5. The CMOS-like logic gate of claim 1 wherein the subset of diode-connected TFTs is connected to a voltage input.
5. The CMOS-like logic gate of claim 1 wherein the subset of diode-connected TFTs is connected to a voltage input.
6. The CMOS-like logic gate of claim 1 further comprising: a NAND gate set of TFTs connected to a second input.
6. The CMOS-like logic gate of claim 1 further comprising: a NAND gate set of TFTs connected to a second input.
7. The CMOS-like logic gate of claim 6 wherein the NAND gate set of TFTs are located in series between the subset of diode-connected TFTs and the subset of pull-down TFTs.
7. The CMOS-like logic gate of claim 6 wherein the NAND gate set of TFTs are located in series between the subset of diode-connected TFTs and the subset of pull-down TFTs.
8. The CMOS-like logic gate of claim 1 further comprising: a NOR gate set of TFTs connected to a second input.
8. The CMOS-like logic gate of claim 1 further comprising: a NOR gate set of TFTs connected to a second input.
9. The CMOS-like logic gate of claim 8 wherein the NOR gate set of TFTs are located in parallel with the subset of pull-down TFTs.
9. The CMOS-like logic gate of claim 8 wherein the NOR gate set of TFTs are located in parallel with the subset of pull-down TFTs
10. The CMOS-like logic gate of claim 1 wherein the other of the pull-down TFTs is connected to an output.
10. The CMOS-like logic gate of claim 1 wherein the other of the pull-down TFTs is connected to an output.
11. The CMOS-like logic gate of claim 10 wherein the output pull-up TFT is connected to the output.
11. The CMOS-like logic gate of claim 10 wherein the output pull-up TFT is connected to the output.
12. A flexible substrate for use in displays comprising: a set of logic gates, each logic gate comprising: a set of thin-film-transistors (TFTs), the set of TFTs including a subset of pull-down TFTs, a subset of diode-connected TFTs and an output pull-up transistor; and a capacitor; wherein the subset of diode-connected TFTs, the output pull-up transistor and the capacitor are positioned to provide a bootstrapped feedback network to provide full-output swing; and wherein the subset of diode-connected TFTs and one of the subset of pull-down TFTs form a leakage current path; wherein at least one of the subset of pull-down TFTs is connected to a first input; and wherein the subset of pull-down transistors are positioned to be parallel or perpendicular to a bending direction of the flexible substrate.
12. A flexible substrate for use in displays comprising: a set of logic gates, each logic gate comprising: a set of thin-film-transistors (TFTs), the set of TFTs including a subset of pull-down TFTs, a subset of diode-connected TFTs and an output pull-up transistor; and a capacitor; wherein the subset of diode-connected TFTs, the output pull-up transistor and the capacitor are positioned to provide a bootstrapped feedback network to provide full-output swing; and wherein the subset of diode-connected TFTs and one of the subset of pull-down TFTs form a leakage current path; wherein at least one of the subset of pull-down TFTs is connected to a first input; and wherein the subset of pull-down transistors are positioned to be parallel or perpendicular to a bending direction of the flexible substrate.
13. The flexible substrate of claim 12 further comprising: a set of metal layers, the set of metal layers including an via layer for internal routing within the set of logic gates, a horizontal interconnects layer and a vertical interconnects layer.
13. The flexible substrate of claim 12 further comprising: a set of metal layers, the set of metal layers including an via layer for internal routing within the set of logic gates, a horizontal interconnects layer and a vertical interconnects layer
Claims 1-13 is/are rejected under 35 U.S.C. 101 as claiming the same invention as that of claims 1-13 of prior U.S. Patent No. 12,288,520. This is a statutory double patenting rejection.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 14, 15 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Kim et al. (2019/0156764).
Regarding claim 14, Kim teaches a display comprising: an array of pixels positioned in a grid-like manner having a set of pixel rows and a set of pixel columns (para [0057] The display panel 110 includes a plurality of gate lines GL1-GLm extending in a row direction DR1, a plurality of data lines (not shown) and a plurality of pixels PX coupled to the gate lines GL1-GLM and the data lines. For example, the pixels PX may be arranged in a matrix form of m rows and n columns.; Fig 4; Fig 7); a set of row drivers (GDRV; Fig 4), each of the set of row drivers connected to one of the set of pixel rows (para [0066] The gate driving circuit 140 provides gate driving signals through the gate lines GL1-GLm for controlling rows of pixels);a set of shift registers and hold registers (131+132; Fig 6), each of the set of shift registers and each of the set of hold registers connected to one of the set of pixel columns (para [0066] The source driving circuit 130 provides data signals to the display panel 110 by providing data signals or data voltages through the data lines connected to the connection nodes NC1-NCL.); wherein a connection between each of the set of pixel columns and its associated hold register is via a pair of data lines (Fig 7 shows pixels in first column which has R pixels are connected to data lines DL1 and DL2; Fig 8 further shows first and second latch groups. para [0071] The latch circuit 132 may store pixel data in response to the latch clock signals LCLK provided by the shift register 131. The latch circuit 132 may output the stored pixel data as a plurality of digital data signals DS to the decoder circuit 133 in response to a control signal from the timing controller 120 in FIG. 4. Para [0085] Each of the first driver circuit 310 and the second driver circuit 320 includes a decoder DEC and a source amplifier AMP. The decoder DEC may receive the gamma voltages VGREF from the gamma voltage generation circuit 150 in FIG. 4 and the digital data signals DS1 and DS2 through the first input switch group 330 and the second input switch group 340. Each of the digital data signals DS1 and DS2 may include pixel data corresponding to pixels in the display panel DPN).
Regarding claim 15, Kim teaches the display of Claim 14 further comprising: a set of pixel column electrical components located between each hold register and its associated pixel column (Fig 8 shows plurality of electrical components located between pixels and latch groups 350 and 360) (Note: specification of instant application in para [0064] describes “Examples of electrical components that may form part of the first or second set of pixel row or pixel column electrical components include, but are not limited to, transistors, switches, demultiplexers, buffers, DAC, capacitors and the like.”. Claim is interpreted in light of this and any of the components between pixel and elements 350 and 360 will read on the claim.).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 16 is/are rejected under 35 U.S.C. 103 as being unpatentable over Kim et al. (2019/0156764) in view of Lee et al. (2020/0143728).
Regarding claim 16, Kim teaches the display as explained for claim 14 above.
Kim fails to teach further comprising: a set of pixel row electrical components located between each row driver and its associated pixel row; as claimed.
Lee teaches a display comprising: a set of row drivers (220; Fig 4); a set of pixel rows (Fig 1; para [0038] The display panel 110 may include a plurality of gate lines GL, a plurality of data lines DL, and a plurality of pixels PX each electrically coupled to corresponding ones of the gate lines GL and the data lines DL.); and further comprising: a set of pixel row electrical components (242, 244, 246; Fig 2) located between each row driver and its associated pixel row (para [0054] Each of the output buffers 242, 244, 246 may correspond to each of the stages of the shift register 220 and each of the gate lines GL1 through GLN. Each of the output buffers 242, 244, 246 may include an amplifier AMP, a first switch SW1, and a second switch SW2.) (Note: specification of instant application in para [0064] describes “Examples of electrical components that may form part of the first or second set of pixel row or pixel column electrical components include, but are not limited to, transistors, switches, demultiplexers, buffers, DAC, capacitors and the like.”. Claim is interpreted in light of this and thus elements 242, 244, 246… will read on the claim).
It would have been obvious to one of ordinary skill in the art before the filing date of present application to have modified the display of Kim with providing output buffer as taught by Lee, because this will provide amplified gate signal and prevent display abnormality.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Papadopoulos et al. (2018/0152189) teaches a CMOS-like logic gate comprising: a set of thin-film-transistors (TFTs) (Fig 2), the set of TFTs including a subset of pull down TFTs (To, T2; Fig 2), a subset of diode-connected TFTs (T1, T3; Fig 2) and an output pull-up transistor (T4; Fig 2); and a capacitor (Co; Fig 2).
Pyon et al. (2012/0313903) teaches an organic light emitting display is disclosed. In one embodiment, the display includes pixels formed in every horizontal line, scan lines coupled to the pixels positioned in two horizontal lines, i data lines coupled to pixels positioned in odd horizontal lines, (i+1) data lines coupled to pixels positioned in even horizontal lines, and first and second emission control lines coupled to the pixels positioned in the two horizontal lines to supply first and second emission control signals, respectively. Each of the pixels includes a pixel circuit coupled to one of the data lines and one of the scan lines, a first organic light emitting diode (OLED) and a second OLED coupled to the pixel circuit to emit light to correspond to current supplied from the pixel circuit, and a selection unit for supplying current from the pixel circuit to the first or second OLED.
Lee et al. (2011/0242140) teaches a method of driving a display panel, a gate signal is outputted to the display panel based on a first control signal.
Shin et al. (2020/0184900) teaches a display device, which may include a display panel including a pixel column having a first pixel and a second pixel, a first data line coupled to the first pixel, and a second data line coupled to the second pixel, a data driver configured to output a data signal for the pixel column to an output line, a signal distribution circuit configured to receive the data signal through the output line, and to alternately transmit the data signal to the first data line and to the second data line, and a signal transmission circuit coupled between the data driver and the output line, and configured to transmit the data signal to the output line during a first period and a second period, and to block transmission of the data signal during a third period that is between the first period and the second period.
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/PREMAL R PATEL/Primary Examiner, Art Unit 2624