CTNF 19/191,962 CTNF 79263 DETAILED ACTION Notice of Pre-AIA or AIA Status 07-03-aia AIA 15-10-aia The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA. Claim Rejections - 35 USC § 102 07-06 AIA 15-10-15 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. 07-07-aia AIA 07-07 The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – 07-08-aia AIA (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention. 07-15 AIA Claim s 1-4, 6-10, and 12-20 are rejected under 35 U.S.C. 102( a)(1 ) as being anticipated by Pang et al. (2017/0301403) . Regarding claim 1: Pang teaches: A system comprising: a set of memory components of a memory sub-system [par 45, 57 – NAND memory comprised of cells in blocks or sub-blocks] ; and at least one processing device operatively coupled to the set of memory components [par 57 – controller with processor and control circuitry] , the at least one processing device being configured to perform operations comprising: determining that a condition to prevent first page read errors has been met [par 54, 59, 161 – timer to measure time since a last sensing operation, a first read situation occurs after a specified amount of time has elapsed, timer is a trigger for detecting the condition] ; in response to determining that the condition to prevent the first page read errors has been met, selecting a first portion of the set of memory components [par 170 – performed on a block basis and done sequentially, a first block is a first portion] ; determining whether the first portion corresponds to single level cell (SLC) usage [par 167 – different operations for different voltage levels are selectively performed based on mode of operation, one of those modes being SLC mode] ; and selectively performing one or more memory operations to prevent first page read errors associated with the first portion based on whether the first portion corresponds to the SLC usage [par 55, 147, 167 – the dummy voltage level increase is performed selectively in order to increase the voltage to a level selected among multiple possible levels. This selective increase is performed based on a mode of operation. If the mode is SLC the voltage is selectively increased to a dummy voltage level corresponding to the SLC mode. The claim recitation requires that one or more operations are performed and wherein the performance is selective in nature. The disclose in Pang of selectively increasing the voltage to one of a plurality of levels meets the broadest reasonable interpretation of the claim language] . Regarding claim 2: Pang teaches: The system of claim 1, wherein the memory sub-system comprises a three- dimensional (3D) NAND memory [par 77] . Regarding claim 3: Pang teaches: The system of claim 1, the operations comprising: accessing a timer associated with performing the one or more memory operations to prevent first page read errors [par 55, 59, 147, 161 – uses a timer to measure an elapsed time and once that elapsed time passes a specified period the operation to avoid read errors due to a first read situation is triggered] ; determining that the timer transgresses a threshold value [par 55, 59, 147, 161] ; and determining that the condition has been met in response to determining that the timer transgresses the threshold value [par 55, 59, 147, 161] . Regarding claim 4: Pang teaches: The system of claim 3, wherein the threshold value comprises a period of one or more minutes [par 147 – the example of 1-2 hours is inclusive of one or more minutes] . Regarding claim 6: Pang teaches: The system of claim 1, the operations comprising: determining that the first portion fails to correspond to SLC usage [par 167 – more than two states means it fails to correspond to SLC usage] ; and performing the one or more memory operations on the first portion in response to determining that the first portion fails to correspond to SLC usage [par 167 – the operations are performed when it fails to correspond to SLC usage] . Regarding claim 7: Pang teaches: The system of claim 6, the operations comprising: performing a ganged reset read operation on the first portion as the one or more memory operations [par 55, 147, 167 – par 0016 of the instant specification describes a ganged reset as moving the state of charges from a stable state to a transient state to enable read operations to be executed properly. The disclosures of Pang for applying a dummy voltage to couple up the word line voltage so that a voltage is moved from an initial 0V state to an elevated dummy voltage state in order to avoid read errors in the first read situation meets this definition of ganged reset] . Regarding claim 8: Pang teaches: The system of claim 7, wherein performing the ganged reset read operation comprises: ramping up one or more word lines (WLs) without sensing a voltage associated with the one or more WLs in the first portion [par 55, 147, 167] . Regarding claim 9: Pang teaches: The system of claim 6, the operations comprising: performing a dummy read operation on the first portion as the one or more memory operations [par 145 – dummy read] . Regarding claim 10: Pang teaches: The system of claim 1, the operations comprising: selecting a second portion of the set of memory component [par 170 – done sequentially by block] ; determining whether the second portion corresponds to the SLC usage [par 170] ; and selectively performing the one or more memory operations to prevent first page read errors associated with the second portion based on whether the second portion corresponds to SLC usage [par 170] . Regarding claim 12: Pang teaches: The system of claim 10, wherein the second portion corresponds to tri-level cell (TLC) or quad level cell (QLC) usage [par 167] . Regarding claim 13: Pang teaches: The system of claim 1, the operations comprising: initiating performing a first page read errors scan operation in response to determining that the condition has been met [par 55, 59, 161] . Regarding claim 14: Pang teaches: The system of claim 1, the operations comprising: transitioning a voltage threshold of the first portion from a stable state to a transient state in response to selectively performing the one or more memory operations [55, 147, 167] . Regarding claim 15: Pang teaches: The system of claim 14, wherein the voltage threshold of the first portion returns to the stable state after a period of time elapses [55, 147, 167] . Regarding claims 16-20: See the teachings above with respect to claims 1-4. Pang further teaches a non-transitory computer readable medium comprising instructions that, when executed by at least one processing device, cause operations to be performed [par 63-65] . Allowable Subject Matter 12-151-08 AIA 07-43 12-51-08 Claim s 5 and 11 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. Conclusion 07-96 AIA The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. ‘558 to Prakash et al. discloses first read situations in 3D NAND and addressing post-read disturbs in first read situations based on whether a memory portion is SLC or not. ‘902 to Yanes et al. discloses 3D NAND pages that haven’t been read for a long time having high BER and performing mitigation reads based on a time interval between reads. Xia et al. (NPL) discloses means and methods for handling temporary read errors due to 3D NAND remaining in an idle state for too long. Zhou et al. (NPL) discloses means and methods for handling temporary read errors due to 3D NAND remaining in an idle state for too long. Any inquiry concerning this communication or earlier communications from the examiner should be directed to MARC M DUNCAN whose telephone number is (571)272-3646. The examiner can normally be reached M-F: 730am-9am, 10am-4:30pm. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Bryce Bonzo can be reached at 571-272-3655. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /MARC DUNCAN/Primary Examiner, Art Unit 2113 Application/Control Number: 19/191,962 Page 2 Art Unit: 2113 Application/Control Number: 19/191,962 Page 3 Art Unit: 2113 Application/Control Number: 19/191,962 Page 4 Art Unit: 2113 Application/Control Number: 19/191,962 Page 5 Art Unit: 2113 Application/Control Number: 19/191,962 Page 6 Art Unit: 2113 Application/Control Number: 19/191,962 Page 7 Art Unit: 2113 Application/Control Number: 19/191,962 Page 8 Art Unit: 2113 Application/Control Number: 19/191,962 Page 9 Art Unit: 2113
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