Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claims 1-6, 8-14, 16, 31-34, and 42-43 are now pending in the application under prosecution and have been examined. Claims 17-30 and 35-41 have been canceled by applicant’s preliminary amendment; and claims 42-43 have been newly added.
In the response to this Office action, the Examiner respectfully requests that support be shown for language added to any original claims on amendment and any new claims. That is, indicate support for newly added claim language by specifically pointing to page(s) and line numbers in the specification and/or drawing figure(s). This will assist the Examiner in prosecuting this application.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claims 1-6, 8-14, 15-16, 30-34, and 42 are rejected under 35 U.S.C. 103 as being unpatentable over US 20140032854 (LIH et al in view of US 20210209026 (BACHAND et al).
With respect to claims 1 and 31, LIH teaches apparatus comprising: interface circuitry; instructions; and at least one programmable circuit to be programmed by the instructions (coherence management using a coherence domain table, the coherent domains may be used to ensure cache coherence between multiple processors and/or to sequence processes, tasks) [Par. 0006-0007; Par. 0015-0016] to: access a request identifying a memory range and a coherency model [monitor address lines for accesses to cached memory locations when an operation is observed (Par. 0018) where a coherence management using a coherence domain table referencing coherence domain comprising at least one address range (Table 200; Par. 0024-0025; Par. 0018)]; and apply the coherency model to a memory address in the memory range based on a coherency model setting (the coherence domain(s) being configurable, i.e., dynamically altered based on the needs and/or resources of the implementing system, e.g., by modifying the address ranges, by changing the number of address ranges in a coherence domain] [Par. 0023-0024]. LIH teaches creation and assignment of domains (corresponding to recited model), the assignment of coherence domains may be logged in a directory, where the coherence domain be modified or reconfigured, e.g., substituting alternate address ranges and/or assigning new values in the relevant entries [Par. 0026].
LIH teaches interface circuitry to receive the request from a compute element, the request generated based on a coherency instruction executed by the compute element (coherence management to monitor, using a coherence domain table when an observed operation is applied to a coherence domain, after creation of the coherency domain, falling into addressing range) (Table 200; Par. 0024-0025; Par. 0018), but fails to specifically teach process the request to determine the memory range and a coherency protocol type identified by the request for implementing the coherency model and apply the coherency model to a memory address in the memory range based on a coherency setting corresponding to the coherency protocol type. However, BACHAND teaches processor-based devices comprising multiple processing elements (PE) having a master PE, the master PE used to send a cache coherence bus command to a central ordering point COP (interface) as unit of a memory store operation for maintaining cache coherency for a memory store operation by the master PE, the processor-based devices used to dynamic selection of cache coherence protocols, wherein the selection is made by the COP based on one or more protocol preference indicators that may be generated and the indicator indicating the selected cache coherence protocol and addressing range associated with the protocol [Abstract; Par. 0006-0008; Par. 0026-0031; Par. 0041-0042]. Therefore, it would have been obvious to one having at least ordinary skill in the art before the effective filing data of the instant application to combine the system of coherence management using a coherence domain table, the coherent domains used to ensure cache coherence between multiple processors, as taught by LIH, with the cache coherency protocol system implementing dynamic selection of cache coherence protocols in processor-based devices, taught by BACHAND, in order to indicate a preference for the update protocol based on knowledge available to each processing element of the number of PEs holding a local cached copy of the coherence granule, as taught by BACHAND [Par. 0007; Par. 0020]. BACHAM teaches, based on the one or more protocol preference indicators received by the central ordering point, the COP dynamically selects the cache coherence protocol, and then communicates the selected cache coherence protocol to the PEs [Par. 0026-0027].
With respect to claim 9, LIH teaches non-transitory computer readable medium comprising instructions which cause at least one programmable circuit (apparatus for management of coherent domains, comprising: a memory; a processor coupled to the memory, wherein the memory contains instructions that when executed by the processor cause the apparatus to perform) [Fig. 1; Par. 0016] to at least: access a request identifying a memory range and a coherency model [monitor address lines for accesses to cached memory locations when an operation is observed (Par. 0018) where a coherence management using a coherence domain table referencing coherence domain comprising at least one address range (Table 200; Par. 0024-0025; Par. 0018)] and apply the coherency model to a memory address in the memory range based on a coherency model setting (the coherence domain(s) being configurable, i.e., dynamically altered based on the needs and/or resources of the implementing system, e.g., by modifying the address ranges, by changing the number of address ranges in a coherence domain] [Par. 0023-0024]. LIH teaches interface circuitry to receive the request from a compute element, the request generated based on a coherency instruction executed by the compute element (coherence management to monitor, using a coherence domain table when an observed operation is applied to a coherence domain, after creation of the coherency domain, falling into addressing range) (Table 200; Par. 0024-0025; Par. 0018), but fails to specifically teach process the request to determine the memory range and a coherency protocol type identified by the request for implementing the coherency model and apply the coherency model to a memory address in the memory range based on a coherency setting corresponding to the coherency protocol type. However, BACHAND teaches processor-based devices comprising multiple processing elements (PE) having a master PE, the master PE used to send a cache coherence bus command to a central ordering point COP (interface) as unit of a memory store operation for maintaining cache coherency for a memory store operation by the master PE, the processor-based devices used to dynamic selection of cache coherence protocols, wherein the selection is made by the COP based on one or more protocol preference indicators that may be generated and the indicator indicating the selected cache coherence protocol and addressing range associated with the protocol [Abstract; Par. 0006-0008; Par. 0026-0031; Par. 0041-0042]. Therefore, it would have been obvious to one having at least ordinary skill in the art before the effective filing data of the instant application to combine the system of coherence management using a coherence domain table, the coherent domains used to ensure cache coherence between multiple processors, as taught by LIH, with the cache coherency protocol system implementing dynamic selection of cache coherence protocols in processor-based devices, taught by BACHAND, in order to indicate a preference for the update protocol based on knowledge available to each processing element of the number of PEs holding a local cached copy of the coherence granule, as taught by [Par. 0007]. BACHAM teaches, based on the one or more protocol preference indicators received by the central ordering point, the COP dynamically selects the cache coherence protocol, and then communicates the selected cache coherence protocol to the PEs [Par. 0026-0027].
With respect to claims 2, 10, and 32, LIH and BACHAND, combined teach the apparatus and non-transitory computer readable medium, wherein the instructions cause one or more of the at least one programmable circuit to configure the coherency setting for the memory range based on the request (application executing on processors to perform traffic monitoring and dynamic control of coherency traffic, using table 200 populated with coherence domain model information) [LIH’s Par. 0023-0024].
With respect to claims 3, 11, and 33, LIH and BACHAND, combined teach the non-transitory computer readable medium, wherein the request includes a bitmask that identifies processor elements that are to implement the coherency model for the memory range (multicore processor chip utilizing a cache coherence domain model for cache coherence management using table entries identifying coherency model and pointer to point to addressing range assigned to the coherency domain resource) [LIH’s Fig. 3-4; Par. 0007; Par. 0025-0026].
With respect to claims 4, 12, and 34, LIH and BACHAND, combined, teach the non-transitory computer readable medium, wherein the instructions cause one or more of the at least one programmable circuit to configure the coherency setting by storing an entry including the memory range and an identifier of the coherency model (multicore processor chip utilizing a cache coherence domain model for cache coherence management using table entries identifying coherency model and using pointer to point to addressing range assigned to coherency domain resources) [LIH’s Fig. 3-4; Par. 0007; Par. 0024-0026].
With respect to claims 5 and 13, LIH and BACHAND, combined teach the non-transitory computer readable medium, wherein the instructions cause one or more of the at least one programmable circuit to configure the coherency setting by tagging the memory range as coherent [coherence management using coherence domain table populated with identified information, mapping addressing ranges to different coherency domains or resources (LIH’s Par. 0024-0026)].
With respect to claims 6 and 14, LIH and BACHAND, combined teach the non-transitory computer readable medium, wherein the instructions cause one or more of the at least one programmable circuit to reset the coherency setting to a default coherency protocol based on a revert coherency request (coherence domain management process to create and assign coherence domains for a plurality of tasks and/or a plurality of resources, as needed, e.g., to ensure appropriate synchronizing or ordering of tasks (LIH’s Par. 0026); … indication that the coherence domain, or a sub-portion thereof, is no longer required. This indication may permit the cache controller to release the coherence domain in its directory, e.g., by deleting the entry associated with the coherence domain. In some embodiments, the coherence domain entry may be modified or reconfigured, e.g., substituting alternate address ranges and/or assigning new values in the relevant entries,… deleting the entry) [LIH’s Par. 0026.
With respect to claims 8 and 16, LIH and BACHAND, combined teach the non-transitory computer readable medium, wherein the instructions cause one or more of the at least one programmable circuit to determine that an access request identifying the memory address corresponds to the coherency setting based on the memory address being within the memory range [coherence management to monitor, using a coherence domain table when an observed operation is applied to a coherence domain, i.e., fall into addressing range, e.g., identified memory locations to order or sequence processes (LIH’s Table 200; Par. 0024-0025; Par. 0018).
With respect to claim 42, LIH and BACHAND, combined teach apparatus wherein one or more of the at least one programmable circuit is to configure the coherency setting by storing an entry including the memory range and an identifier of the coherency protocol type, and to remove the entry based on a reset coherency request identifying the memory range (the master PE to determine that the memory store operation will be one of a plurality of memory store operations to a same coherence granule, the central ordering point COP indicating preferred cache coherence protocol preference indicators that may be generated updating coherency model [BACHAND’s Par. 0020-0021; Par. 0027-0031; Par. 0041-0042].
Claims 1-2, 9-10, 31-32, and 42 are rejected under 35 U.S.C. 103 as being unpatentable over US 20210011864 (GUIM BERNAT et al) in view of US 20210209026 (BACHAND et al).
With respect to claims 1 and 31, GUIM BERNAT teaches apparatus comprising: interface circuitry; instructions; and at least one programmable circuit to be programmed by the instructions (coherency circuitry within a switch to implement coherency domains, the circuitry being configured to intercept snoops switch includes a configuration interface, including the ability to dynamically instantiate and update coherent memory domains) [Par. 0027-0029] to: access a request identifying a memory range and a coherency model (in response to memory allocation requests issued by processes, the coherency circuit to leverage information in system address decoder, which may decode incoming system addresses in requests to determine whether an incoming request is for a coherent domain, memory domain is composed by a set of memory regions with address ranges) [Par. 0026-0029]; and apply the coherency model to a memory address in the memory range based on a coherency model setting (request including an address at which requested data is located, featuring accessing a memory domain table based on an address of the memory request to identify an entry in the table associated with a memory domain including the address, each entry of the memory domain table to identify a memory domain of the system and a coherency status of the memory domain) [Par. 000026-0029; Par. 0048-0049]. GUIM BERNAT fails to specifically teach access, via the interface circuitry, the request from a compute element and generated based on a coherency instruction executed by the compute element; process the request to determine the memory range and a coherency protocol type identified by the request for implementing the coherency model and apply the coherency model to a memory address in the memory range based on a coherency setting corresponding to the coherency protocol type. However, BACHAND teaches processor-based devices comprising multiple processing elements (PE) having a master PE, the master PE used to send a cache coherence bus command to a central ordering point COP (interface) as unit of a memory store operation for maintaining cache coherency for a memory store operation by the master PE, the processor-based devices used to dynamic selection of cache coherence protocols, wherein the selection is made by the COP based on one or more protocol preference indicators that may be generated and the indicator indicating the selected cache coherence protocol and addressing range associated with the protocol [Abstract; Par. 0006-0008; Par. 0026-0031; Par. 0041-0042]. Therefore, it would have been obvious to one having at least ordinary skill in the art before the effective filing data of the instant application to combine the coherency circuitry within a switch to implement coherency domains, as taught by GUIM BERNAT, with the cache coherency protocol system implementing dynamic selection of cache coherence protocols in processor-based devices, taught by BACHAND, in order to indicate a preference for the update protocol based on knowledge available to each processing element of the number of PEs holding a local cached copy of the coherence granule, as taught by [Par. 0007]. BACHAM teaches, based on the one or more protocol preference indicators received by the central ordering point, the COP dynamically selects the cache coherence protocol, and then communicates the selected cache coherence protocol to the PEs [Par. 0026-0027].
With respect to claim 9, GUIM BERNAT teaches non-transitory computer readable medium comprising instructions which cause at least one programmable circuit (at least one computer readable storage medium having stored thereon instructions, which if performed by a machine cause the machine to perform a method for handling an incoming memory request in a switch) [Fig. 4; Par. 0054-0055; Par. 0047-0048; Par. 0091] to at least: access a request identifying a memory range and a coherency model (in response to memory allocation requests issued by processes, the coherency circuit to leverage information in system address decoder, which may decode incoming system addresses in requests to determine whether an incoming request is for a coherent domain, memory domain is composed by a set of memory regions with address ranges) [Par. 0026-0029]; and apply the coherency model to a memory address in the memory range based on a coherency model setting (request including an address at which requested data is located, featuring accessing a memory domain table based on an address of the memory request to identify an entry in the table associated with a memory domain including the address, each entry of the memory domain table to identify a memory domain of the system and a coherency status of the memory domain) [Par. 000026-0031; Par. 0048-0049].
GUIM BERNAT fails to specifically teach access, via the interface circuitry, the request from a compute element and generated based on a coherency instruction executed by the compute element; process the request to determine the memory range and a coherency protocol type identified by the request for implementing the coherency model and apply the coherency model to a memory address in the memory range based on a coherency setting corresponding to the coherency protocol type. However, BACHAND teaches processor-based devices comprising multiple processing elements (PE) having a master PE, the master PE used to send a cache coherence bus command to a central ordering point COP (interface) as unit of a memory store operation for maintaining cache coherency for a memory store operation by the master PE, the processor-based devices used to dynamic selection of cache coherence protocols, wherein the selection is made by the COP based on one or more protocol preference indicators that may be generated and the indicator indicating the selected cache coherence protocol and addressing range associated with the protocol [Abstract; Par. 0006-0008; Par. 0026-0031; Par. 0041-0042]. Therefore, it would have been obvious to one having at least ordinary skill in the art before the effective filing data of the instant application to combine the coherency circuitry within a switch to implement coherency domains, as taught by GUIM BERNAT, with the cache coherency protocol system implementing dynamic selection of cache coherence protocols in processor-based devices, taught by BACHAND, in order to indicate a preference for the update protocol based on knowledge available to each processing element of the number of PEs holding a local cached copy of the coherence granule, as taught by [Par. 0007]. BACHAM teaches, based on the one or more protocol preference indicators received by the central ordering point, the COP dynamically selects the cache coherence protocol, and then communicates the selected cache coherence protocol to the PEs [Par. 0026-0027].
With respect to claims 2, 10, and 32, GUIM BERNAT and BACHAND, combined teach the apparatus and non-transitory computer readable medium, wherein the instructions cause one or more of the at least one programmable circuit to configure the coherency setting for the memory range based on the request (application executing on processors to perform traffic monitoring and dynamic control of coherency traffic, storing entries the coherent memory domain in a memory domain table, each entry including memory region information, one or more process address identifiers that belong to the first coherent memory domain) [Par. 0077-0078; Par. 0059].
With respect to claim 42, GUIM BERNAT and BACHAND, combined teach the apparatus wherein one or more of the at least one programmable circuit is to configure the coherency setting by storing an entry including the memory range and an identifier of the coherency protocol type, and to remove the entry based on a reset coherency request identifying the memory range (the master PE to determine that the memory store operation will be one of a plurality of memory store operations to a same coherence granule, the central ordering point COP indicating preferred cache coherence protocol preference indicators that may be generated updating coherency model [BACHAND’s Par. 0020-0021; Par. 0027-0031; Par. 0041-0042].
Allowable Subject Matter
Claim 43 is objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
US 10176100 B1 (SAUER et al) teaching system: providing a mixed abstraction simulation model including an abstract portion and a detailed portion, wherein the detailed portion includes a cache coherent interconnect and a coherency proxy; establishing, within the detailed portion, communication between an extended smart memory function and at least one of the cache coherent interconnect and the coherency proxy.
US 20240338315 A1 (CHOI et al) teaching coherent interface scheme using a cache protocol enabling a device to access host memory in a cache coherent manner, the coherent cache interface scheme features device logic including a cache and/or cache agent used to implement one or more coherency models, i.e., memory access protocol implementing one or more coherence models such as a host coherent model, a device coherent model, a device coherent model using back-invalidation.
US 10970213 B2 (McGEE et al) teaching apparatus, system, and method of enforcing cache coherency in a multiprocessor shared memory system wherein a request is received from a node controller, to process a cache coherent operation on a memory block in a shared memory, and based on the information included in the request, a determination of coherency model is made relative to the memory that includes the memory block referenced in the request.
N. Eisley, L. -s. Peh and L. Shang, "In-Network Cache Coherence," 2006 39th Annual IEEE/ACM International Symposium on Microarchitecture (MICRO'06), Orlando, FL, USA, 2006, pp. 321-332.
L. Alvarez et al., "Coherence protocol for transparent management of scratchpad memories in shared memory manycore architectures," 2015 ACM/IEEE 42nd Annual International Symposium on Computer Architecture (ISCA), Portland, OR, USA, 2015, pp. 720-732.
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/PIERRE MICHEL BATAILLE/ Primary Examiner, Art Unit 2138
