Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claims 1-20 are now pending in the application under prosecution and have been examined.
The specification has not been checked to the extent necessary to determine the presence of all possible minor errors.
The specification should be amended to reflect the status of all related application, whether patented or abandoned. Therefore, applications noted by their serial number and/or attorney docket number should be updated with correct serial number and patent number if patented.
The first instance of all acronyms or abbreviation should be spelled out for clarity, whether or not considered well known in the art.
In the response to this Office action, the Examiner respectfully requests that support be shown for language added to any original claims on amendment and any new claims. That is, indicate support for newly added claim language by specifically pointing to page(s) and line numbers in the specification and/or drawing figure(s). This will assist the Examiner in prosecuting this application.
37 C.F.R. § 1.83(a) requires the Drawings to illustrate or show all claimed features.
Applicant must clearly point out the patentable novelty that they think the claims present, in view of the state of the art disclosed by the references cited or the objections made, and must also explain how the amendments avoid the references or objections. See 37 C.F.R. § 1.111(c).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claims 1-20 are rejected under 35 U.S.C. 103 as being unpatentable over CN 118764548 A (LI et al) In view of US 20220114128 A1 (JEN et al).
With respect to claim 1, LI (CN 118764548 A) teaches an interface device for interfacing a communication between a first device and a second device (data transmitting and receiving device through the use of a network device interfacing a main device and a storage module) [See abstract; Content of the invention Par. 2 and Par. 3, the interface device comprising: a first element configured to receive a first packet from the first device based on a first protocol and transmit the first packet to the second device, wherein the first packet includes a command (first protocol processing module connected with the main device for data access address corresponding to data transmitting/receiving instruction in the storage module; through the first protocol processing module, based on the first protocol format and the data access address, the transmission data of the data transceiver instruction is transmitted between the main device and the storage module) [See abstract; Content of the invention Par. 2 and Par. 3], and a second element configured to receive a packet from the first device based on a second protocol different from the first protocol and transmit the packet to the second device, wherein the second packet includes a command address representing a storage position of the command (second protocol processing module connected with the network device based on a second protocol format different from the first protocol format and the data access address, transmitting the transmission data of the data transmitting/receiving instruction between the network device and the storage module to cooperatively execute the data transmitting/receiving operation of the data transmitting/receiving instruction through second protocol processing module) [See abstract; Content of the invention Par. 2 and Par. 3].
LI teaches transmission of data from first to second storage, but fails to explicitly differentiate first and second packets representing the data type, a first data being different to a second data. However, JEN teaches transmitter and receiver configured to transmit and receive transaction layer data packets through an interconnect link featuring interconnect protocol for various functions, such as the interconnect link may process requests and memory flows that support various interconnect protocols between host processor (first device) and circuitry (second device) [Abstract; Fig. 4; Par. 0044-0045]; the requests and data flows featuring one or more protocol queues with the interface link to determine an interconnect protocol based on the messages and data for communication [Par. 0045]; configured to receive a first packet where an incoming packet data stream received from the first device based on a first protocol (physical logic to interface logic) in multi-protocol multiplexer 450" and transmit the first packet to the second device wherein the first packet includes a command and a command address link layer processing for these protocols" commands for addressing memory/cache [Fig. 3; Par. 0037-0038]; a second element configured to receive a second packet {"CXL interface circuit 300 including a transaction layer 310, a link layer 320, and a physical layer 340" from the first device based on a second protocol. different from the first protocol [Fig. 3a, Par. 0037-0038].
Therefore, it would have been obvious to one of ordinary skill in the art, having the teachings of LI and JEN before the effective filing date of the claimed invention, to modify LI's transmission and receiving method and incorporate the multiple packets interfacing multiple protocol layers, as taught by JEN. The motivation for the combination would have been to implement multiprotocol system enabling efficient use of all available resources.
With respect to claim 2, LI and JEN, combined, teach the interface device, wherein the first protocol and the second protocol are a low-ranked protocol of a compute express link (CXL) protocol (interface circuit being a CXL interface circuit, where: the CXL interface circuit includes CXL transaction layer protocols) [JEN’s Par. 0037-0038].
With respect to claim 3, LI and JEN, combined, teach the interface device, wherein the first protocol is a CXL.mem protocol supported by a compute express link (CXL) protocol (interface circuit being a CXL interface circuit, where: the CXL interface circuit includes CXL transaction layer to include components to enable transaction layer processing for PCIe/CXL.io communications and CXL.cache and CXL.memory transactions; a PCIe/CXL.io transaction layer for handling enhancements to PCIe transaction layer 316 for handling CXL.io transactions, CXL.cache and CXL.memory transaction layer protocols) [JEN’s Par. 0037-0038].
With respect to claim 4, LI and JEN, combined, teach the interface device, wherein the second protocol is a CXL.io protocol supported by a compute express link (CXL) protocol (interface circuit being a CXL interface circuit, where: the CXL interface circuit includes CXL transaction layer to include components to enable transaction layer processing for PCIe/CXL.io communications and CXL.cache and CXL.memory transactions; a PCIe/CXL.io transaction layer for handling enhancements to PCIe transaction layer 316 for handling CXL.io transactions, CXL.cache and CXL.memory transaction layer protocols) [JEN’s Par. 0037-0038].
With respect to claim 5, LI and JEN, combined, teach the interface device, wherein the first packet further comprises data (the packet being data stream of transaction layer packets sent via a multi-lane link) [Par. 0030-0031].
With respect to claim 6, LI data computing device comprising: an interface device configured to receive a first packet from a first device based on a first protocol and to receive a second packet to from the first device based on a second protocol different from the first protocol, wherein the first packet includes a command (method transmitting and receiving data through the use of a network device interfacing a main device and a storage module; data transmitting/receiving through a first protocol processing module, based on the first protocol format and the data access address and transmitting transmission data of the data through transmitting/receiving instruction between the network device and the storage module through second protocol processing module [See abstract; Content of the invention Par. 2 and Par. 3]; and, receiving a packet from the first device based on a second protocol different from the first protocol by the second device, wherein the second packet includes a command address representing a storage position of the command and based on the address, first protocol processing module is triggered, and based on the determining address the protocol processing module is triggered establishing a link, based on the first or second protocol format and the data access address, the transmission data of the data transmission instruction is read from the master device, and the transmission data is written into the storage module [See abstract; Content of the invention Par. 2 and Par. 3] [See abstract; Content of the invention Par. 2 and Par. 3; Specific Implementation Examples 16th Par.].
LI teaches determining the data access address corresponding to the data transmitting/receiving instruction in the storage module by the communication cooperation between the first protocol processing module and the second protocol processing module in response to the data transmitting/receiving instruction of the main device and based on the determining address the protocol processing module is triggered establishing a link, based on the first or second protocol format and the data access address, the transmission data of the data transmission instruction is read from the master device, and the transmission data is written into the storage module [See abstract; Content of the invention Par. 2 and Par. 3; Specific Implementation Examples 16th Par] (corresponding to processor configured to parse the first packet to extract the command and the command address and to store the command in the storage position of the device memory and parse the second packet to extract the command address); but fails to explicitly differentiate first and second packets representing the data type, a first data being different to a second data.
However, JEN teaches transmitter and receiver configured to transmit and receive transaction layer data packets through an interconnect link featuring interconnect protocol for various functions, such as the interconnect link may process requests and memory flows that support various interconnect protocols between host processor (first device) and circuitry (second device) [Abstract; Fig. 4; Par. 0044-0045]; the interface link to determine an interconnect protocol based on the messages and data for communication including sync headers decoded to determine determining which blocks to decode the packet or block set (corresponding to parsing the packet to extract the command) [Par. 0045]; the requests and data flows featuring one or more protocol queues with the interface link to determine an interconnect protocol based on the messages and data for communication with the interface logic coupled to a multi-protocol multiplexer having one or more protocol queues to send and receive messages and data with host processor wherein each protocol queue may be protocol specific such that each interconnect protocol may be associated with a particular protocol queue [Par. 0045]; configured to receive a first packet where an incoming packet data stream received from the first device based on a first protocol (physical logic to interface logic) in multi-protocol multiplexer 450" and transmit the first packet to the second device wherein the first packet includes a command and a command address link layer processing for these protocols" commands for addressing memory/cache [Fig. 3; Par. 0037-0038]; a second element configured to receive a second packet {"CXL interface circuit 300 including a transaction layer 310, a link layer 320, and a physical layer 340" from the first device based on a second protocol. different from the first protocol [Fig. 3a, Par. 0037-0038].
Therefore, it would have been obvious to one of ordinary skill in the art, having the teachings of LI and JEN before the effective filing date of the claimed invention, to modify LI's transmission and receiving method and incorporate the multiple packets interfacing multiple protocol layers, as taught by JEN. The motivation for the combination would have been to implement multiprotocol system enabling efficient use of all available resources.
With respect to claim 7, the rejection of claim 2, addressed above is applicable to claim 7, as claim 7 recites data processing system reciting the same functional limitation as the features of the interface device of claim 2, addressed and rejected above.
With respect to claim 8, the rejection of claim 3, addressed above is applicable to claim 8, as claim 8 recites data processing system reciting the same functional limitation as the features of the interface device of claim 3, addressed and rejected above.
With respect to claim 9, the rejection of claim 4, addressed above is applicable to claim 9, as claim 9 recites data processing system reciting the same functional limitation as the features of the interface device of claim 4, addressed and rejected above.
With respect to claim 10, the rejection of claim 5, addressed above is applicable to claim 10, as claim 10 recites data processing system reciting the same functional limitation as the features of the interface device of claim 5, addressed and rejected above.
With respect to claim 11, LI (CN 118764548 A) teaches data processing system comprising: a first device; and a second device, wherein the second device comprises an interface device and a processor (data transmitting and receiving device through the use of a network device interfacing a main device and a storage module, first protocol processing module connected with the main device for data access address corresponding to data transmitting/receiving instruction in the storage module) [See abstract; Content of the invention Par. 2 and Par. 3] wherein the interface device is configured to: receive a request from the first device, receive a packet based on a first protocol, and receive a packet from the first device based on a second protocol different from the first protocol, the first packet including a command, the second packet including a command address representing a storage position of the command (first protocol processing module connected with the main device for data access address corresponding to data transmitting/receiving instruction in the storage module; through the first protocol processing module, based on the first protocol format and the data access address, the transmission data of the data transceiver instruction is transmitted between the main device and the storage module) [See abstract; Content of the invention Par. 2 and Par. 3]; second protocol processing module connected with the network device based on a second protocol format different from the first protocol format and the data access address, transmitting the transmission data of the data transmitting/receiving instruction between the network device and the storage module to cooperatively execute the data transmitting/receiving operation of the data transmitting/receiving instruction through second protocol processing module) [See abstract; Content of the invention Par. 2 and Par. 3].
LI fails to specifically teach the interface device is configured to: receive an off- road calculation request and explicitly differentiate first and second packets representing the data type, a first data being different to a second data, wherein the processor is configured to: parse the first packet and the second packet to process the off-road calculation request.
However, Off-load calculation is being interpreted as the determining process where the processing module to determine the data access address corresponding to the data transmission instruction in the storage module, in more detailed, determining the data access address corresponding to the data transmitting/receiving instruction in the storage module by the communication cooperation between the first protocol processing module and the second protocol processing module in response to the data transmitting/receiving instruction of the main device and based on the determining address the protocol processing module is triggered establishing a link, based on the first or second protocol format and the data access address, the transmission data of the data transmission instruction is read from the master device, and the transmission data is written into the storage module [See abstract; Content of the invention Par. 2 and Par. 3; Specific Implementation Examples 16th Par].
JEN,, in the same field of endeavor, teaches transmitter and receiver configured to transmit and receive transaction layer data packets through an interconnect link featuring interconnect protocol for various functions, such as the interconnect link may process requests and memory flows that support various interconnect protocols between host processor (first device) and circuitry (second device) [Abstract; Fig. 4; Par. 0044-0045]; the interface link to determine an interconnect protocol based on the messages and data for communication including sync headers decoded to determine determining which blocks to decode the packet or block set (corresponding to parsing the packet to extract the command) [Par. 0045]; a first packet where an incoming packet data stream received from the first device based on a first protocol (physical logic to interface logic) in multi-protocol multiplexer 450" and transmit the first packet to the second device wherein the first packet includes a command and a command address link layer processing for these protocols" commands for addressing memory/cache [Fig. 3; Par. 0037-0038]; a second element configured to receive a second packet {"CXL interface circuit 300 including a transaction layer 310, a link layer 320, and a physical layer 340" from the first device based on a second protocol. different from the first protocol [Fig. 3a, Par. 0037-0038].
Therefore, it would have been obvious to one of ordinary skill in the art, having the teachings of LI and JEN before the effective filing date of the claimed invention, to modify LI's transmission and receiving method and incorporate the multiple packets interfacing multiple protocol layers, as taught by JEN. The motivation for the combination would have been to implement multiprotocol system enabling efficient use of all available resources.
With respect to claim 12, LI and JEN, combined, teach the data processing system, further comprising a device memory configured to store the command (JEN’s memory resource configured to share computing and/or networking resources) [Par. 0024-0025]; ( JI’s processing module to include coprocessor, an embedded soft core (e.g., microblaze soft core 228) configured to convert the NVMe format command, establish a link, and implement data sharing by access) [See abstract; Content of the invention Par. 2 and Par. 3; Specific Implementation Examples 15th Par].
With respect to claim 13, LI and JEN, combined, teach the data processing system, wherein the first to device comprises a plurality of devices and the device memory is shared with at least part of the plurality of devices (processor circuitry, and memory circuitry includes hardware accelerators (e.g., FPGA cells, the hardware accelerator 1003) data storage circuitry, memory (shared, dedicated, or group), storage circuitry with shared or respective controllers with sharing features) [Jen’s Fig. 7-8; Par. 0023-0024; 000070-0072]; ( JI’s first and second processing modules implement data sharing by access) [See abstract; Content of the invention Par. 2 and Par. 3; Specific Implementation Examples 15th Par].
With respect to claim 14, LI and JEN, combined, teach the data processing system, wherein the first device comprises a plurality of devices and the second device is shared with at least part of the plurality of devices (processor circuitry, and memory circuitry includes hardware accelerators (e.g., FPGA cells, the hardware accelerator 1003) data storage circuitry, memory (shared, dedicated, or group), storage circuitry with shared or respective controllers with sharing features) [Jen’s Fig. 7-8; Par. 0023-0024; 000070-0072]; ( JI’s first and second processing modules implement data sharing by access) [See abstract; Content of the invention Par. 2 and Par. 3; Specific Implementation Examples 15th Par.
With respect to claim 15, LI and JEN, combined, teach the data processing system, wherein the first protocol and the second protocol are a low-ranked protocol of a compute express link (CXL) protocol (interface circuit being a CXL interface circuit, where: the CXL interface circuit includes CXL transaction layer protocols) [JEN’s Par. 0037-0038].
With respect to claim 16, LI and JEN, combined, teach data processing system, wherein the first protocol is a CXL.mem protocol supported by a compute express link (CXL) protocol (interface circuit being a CXL interface circuit, where: the CXL interface circuit includes CXL transaction layer to include components to enable transaction layer processing for PCIe/CXL.io communications and CXL.cache and CXL.memory transactions; a PCIe/CXL.io transaction layer for handling enhancements to PCIe transaction layer 316 for handling CXL.io transactions, CXL.cache and CXL.memory transaction layer protocols) [JEN’s Par. 0037-0038].
With respect to claim 17, LI and JEN, combined, teach the data processing system, wherein the second protocol is a CXL.io protocol supported by a compute express link (CXL) protocol (interface circuit being a CXL interface circuit, where: the CXL interface circuit includes CXL transaction layer to include components to enable transaction layer processing for PCIe/CXL.io communications and CXL.cache and CXL.memory transactions; a PCIe/CXL.io transaction layer for handling enhancements to PCIe transaction layer 316 for handling CXL.io transactions, CXL.cache and CXL.memory transaction layer protocols) [JEN’s Par. 0037-0038].
With respect to claim 18, LI teaches an interface method for interfacing between a first device and a second device (method transmitting and receiving data through the use of a network device interfacing a main device and a storage module) [See abstract; Content of the invention Par. 2 and Par. 3, the interface method comprising: receiving a first packet from the first device based on a first protocol by the second device, wherein the first packet includes a command (data transmitting/receiving instruction in the storage module; through a first protocol processing module, based on the first protocol format and the data access address, the transmission data of the data transceiver instruction is transmitted between the main device and the storage module) [See abstract; Content of the invention Par. 2 and Par. 3]; and receiving a packet from the first device based on a second protocol different from the first protocol by the second device, wherein the second packet includes a command address representing a storage position of the command (transmitting transmission data of the data through transmitting/receiving instruction between the network device and the storage module to cooperatively execute the data transmitting/receiving operation of the data transmitting/receiving instruction through second protocol processing module) [See abstract; Content of the invention Par. 2 and Par. 3].
LI teaches transmission of data from first to second storage, but fails to explicitly differentiate first and second packets representing the data type, a first data being different to a second data. However, JEN teaches transmitter and receiver configured to transmit and receive transaction layer data packets through an interconnect link featuring interconnect protocol for various functions, such as the interconnect link may process requests and memory flows that support various interconnect protocols between host processor (first device) and circuitry (second device) [Abstract; Fig. 4; Par. 0044-0045]; the requests and data flows featuring one or more protocol queues with the interface link to determine an interconnect protocol based on the messages and data for communication [Par. 0045]; configured to receive a first packet where an incoming packet data stream received from the first device based on a first protocol (physical logic to interface logic) in multi-protocol multiplexer 450" and transmit the first packet to the second device wherein the first packet includes a command and a command address link layer processing for these protocols" commands for addressing memory/cache [Fig. 3; Par. 0037-0038]; a second element configured to receive a second packet {"CXL interface circuit 300 including a transaction layer 310, a link layer 320, and a physical layer 340" from the first device based on a second protocol. different from the first protocol [Fig. 3a, Par. 0037-0038]. Therefore, it would have been obvious to one of ordinary skill in the art, having the teachings of LI and JEN before the effective filing date of the claimed invention, to modify LI's transmission and receiving method and incorporate the multiple packets interfacing multiple protocol layers, as taught by JEN. The motivation for the combination would have been to implement multiprotocol system enabling efficient use of all available resources.
With respect to claim 19, the rejection of claim 2, addressed above is applicable to claim 19, as claim 19 repeat the features of the method of the interface device of claim 2.
With respect to claim 20, the rejection of claim 5, addressed above is applicable to claim 20, as claim 20 features the method of the interface device of claim 5.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
US 20220263913 A1 (ZHANG et al) teaching data center cluster includes a plurality of host systems coupled to a network processing device by a Compute Express Link (CXL) switch, where the network processing device includes memory to implement a memory pool for the data center cluster. Request and responses are communicated within the data center cluster using the memory pool and the network processing device manages communication within the data center cluster.
US 20220147470 A1 (LEE et al) teaching device configured to communicate through a bus, the device comprising: a first interface circuit configured to, based on a first protocol, provide a first access to a first memory through the bus; and a second interface circuit configured to, based on a second protocol, provide a non-coherent input/output (I/O) interface through the bus, wherein the second interface circuit is further configured to provide a second access to the first memory through the bus by accessing the first memory in response to a first message received through the bus based on the second protocol.
US 20240241847 A1 (ZHANG et al) teaching apparatus comprising: a network interface device comprising: an interface comprising protocol circuitry to couple to a host device by a link, wherein the link is compliant with a Compute Express Link (CXL) protocol; a memory; and logic to support emulation of a file system by the host device of at least a portion of the memory, wherein the link is used for memory accesses for requests or responses associated with the emulation of the file system.
CN 116486868 A (SEHGAL et al) teaching computing High Speed Non-volatile Memory (NVMe) On High Speed Link (CXL), CXL memory request from the host system is processed according to the CXL.io protocol; the NVMe data request encapsulated into a CXL request packet; common front end identifying the NVMe data request within the CXL packet, parsing the NVMe data request, and routes the request to the NVMe memory; a hhe host operating system software driver intercepting the NVMe memory request and encapsulates it into the CXL request packet.
R. R. S, R. R, M. Moharir and S. G, "SCAPY- A powerful interactive packet manipulation program," 2018 International Conference on Networking, Embedded and Wireless Systems (ICNEWS), Bangalore, India, 2018, pp. 1-5.
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/PIERRE MICHEL BATAILLE/Primary Examiner, Art Unit 2138
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