DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1-7, 16, 17, 19 and 20 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Xiang et al. (US 2017/0221419).
In regard to claim 1, Xiang et al. teach an electronic device, comprising: a data line (fig. 5 Vdata); a first scan line (Scan 1); a second scan line (Scan 2); a first electronic unit (D1); a second electronic unit (D2); a first circuit unit configured to drive the first electronic unit and comprising a first time-interleaved circuit (fig. 1 element 11 and element 501); and a second circuit unit adjacent to the first circuit unit, configured to drive the second electronic unit and comprising a second time-interleaved circuit (fig. 1 element 11 and element 502); wherein the data line is coupled to the first circuit unit and the second circuit unit (fig. 5, Vdata is connected to both 501 and 502), the first scan line is coupled to the first time-interleaved circuit (Scan1 connected to 501), and the second scan line is coupled to the second time-interleaved circuit (Scan2 connected to 502).
In regard to claim 2, Xiang et al. teach wherein at least one of the first time-interleaved circuit and the second time-interleaved circuit comprises a capacitor (elements C1 and C2), a first end of the capacitor is coupled to at least two transistors (C1 is connected to DT1 and M2), and a second end of the capacitor is coupled to a system voltage end (PVEE through D1).
In regard to claim 3, Xiang et al. teach a third circuit unit and a fourth circuit unit, wherein the first circuit unit, the second circuit unit, the third circuit unit, and the fourth circuit unit are arranged in proximity, the third circuit unit comprises a third time-interleaved circuit, and the fourth circuit unit comprises a fourth time-interleaved circuit (see fig. 1, Xiang et al. teach an array of paired circuits 101 and 102).
In regard to claim 4, Xiang et al. teach wherein the first scan line is coupled to the first time-interleaved circuit and the third time-interleaved circuit, and the second scan line is coupled to the second time-interleaved circuit and the fourth time-interleaved circuit (see the second column of fig. 1. S12 and S22 are connected to every other pixel).
In regard to claim 5, Xiang et al. teach wherein at least one of the first time-interleaved circuit, the second time-interleaved circuit, the third time-interleaved circuit, and the fourth time-interleaved circuit comprises a capacitor (elements C1 and C2), a first end of the capacitor is coupled to at least two transistors (C1 is connected to DT1 and M2), and a second end of the capacitor is coupled to a system voltage end (PVEE through D1).
In regard to claim 6, Xiang et al. teach wherein the first circuit unit and the second circuit unit are pixel circuit units, and the first electronic unit and the second electronic unit are light-emitting units (fig. 5 and paragraph 62, D1 is a light emitting unit).
In regard to claim 7, Xiang et al. teach wherein each of the first electronic unit and the second electronic unit comprises a light-emitting diode (LED) (paragraph 62).
In regard to claim 16, Xiang et al. teach wherein the first circuit unit and the second circuit unit respectively sample a voltage level of the data line at different times through the first time-interleaved circuit and the second time-interleaved circuit (figs. 5 and 6. M3 and M5 are connected to the first and second scan lines which are active at different times. When these are active the data line is sampled).
In regard to claim 17, Xiang et al. teach wherein each of the first time-interleaved circuit and the second time-interleaved circuit comprises a capacitor, a first end of the capacitor is coupled to at least two transistors, and a second end of the capacitor is coupled to a system voltage end (fig. 5 elements C1 and C2).
In regard to claim 19, Xiang et al. teach wherein a control end of a second switch of the first time-interleaved circuit and a control end of a fourth switch of the second time-interleaved circuit receive a signal, the first time-interleaved circuit outputs a first switch signal, the second time-interleaved circuit outputs a second switch signal (see M2 and M4 in fig. 5. When they receive the signal Scan 1 or Scan2 they output the switch signal Vref1 or 2), and the first switch signal and the second switch signal are at a low voltage level only when the signal is at a high voltage level (see paragraph 72, the drawings of Xiang et al. show N-type transistors which are active when the signal is high. Paragraph 72 of Xiang et al. shows a P-type can be used which is active when the signal is low and inactive when the signal is high).
In regard to claim 20, Xiang et al. teach wherein the electronic device is a display device (fig. 1 and paragraph 25).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 14 and 15 is/are rejected under 35 U.S.C. 103 as being unpatentable over Xiang et al. in view of Fan et al. (US 2022/0328460).
In regard to claims 14 and 15, Xiang et al. teach all the elements of these claims except antennas or a sensing device.
Fan et al. teaches antennas or a sensing device (paragraph 18. Fan et al. teach a circuit that could be used to drive a display, antenna or sensing device).
The two are analogous art because they both deal with the same field of invention of driving circuits in an array.
Before the effective filing date it would have been obvious to one of ordinary skill in the art to provide the apparatus of Xiang et al. with the antenna or sensing device of Fan et al. The rationale is as follows: Before the effective filing date it would have been obvious to provide the apparatus of Xiang et al. with the antenna or sensing device of Fan et al. because the circuit of Xiang et al. could be used to drive any electronic circuit in an array. One or ordinary skill in the art would recognize the use of antennas or sensing devices in the driving circuit of Xiang et al. would provide predictable results and would allow for a greater range of uses.
Claim(s) 18 is/are rejected under 35 U.S.C. 103 as being unpatentable over Xiang et al.
In regard to claim 18, Xiang et al. teach all the elements of claim 18 except a ground voltage (paragraphs 65 and 71, Xiang et al. shows PVEE being a low voltage but not specifically a ground voltage).
Before the effective filing date it would have been obvious to one of ordinary skill in the art to provide the apparatus of Xiang et al. with a ground voltage. The rationale is as follows: Before the effective filing date it would have been obvious to provide the apparatus of Xiang et al. with a ground voltage because a ground voltage would provide protection to the circuit.
Allowable Subject Matter
Claims 8-13 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is an examiner’s statement of reasons for allowance: In regard to claims 8-11, the prior art fails to teach or make obvious “a control end of the first switch and a control end of the third switch receive a same signal, a first end of the first switch is coupled to the first scan line to receive a first clock signal, and a first end of the third switch is coupled to the second scan line to receive a second clock signal.”
In regard to claims 12 and 13, the prior art fails to teach or make obvious “a control end of the first switch and a control end of the fourth switch receive a same signal, a first end of the first switch is coupled to the first scan line to receive a first clock signal, and a first end of the fourth switch is coupled to the second scan line to receive a second clock signal”.
Any comments considered necessary by applicant must be submitted no later than the payment of the issue fee and, to avoid processing delays, should preferably accompany the issue fee. Such submissions should be clearly labeled “Comments on Statement of Reasons for Allowance.”
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to JOSEPH R HALEY whose telephone number is (571)272-0574. The examiner can normally be reached 7:30am-5pm.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Amr Awad can be reached at 571-272-7764. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/JOSEPH R HALEY/ Primary Examiner, Art Unit 2621