DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Specification
The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed.
The following title is suggested: IMPROVED LAYOUT DESIGN OF A DISPLAY SUBSTRATE
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-18 are rejected under 35 U.S.C. 103 as being unpatentable over Zhu et al. (US PGPub 2018/0261164) in view of Koo (US PGPub 2012/0032937).
Regarding claim 1, Zhu discloses a display substrate ([0023], “organic light-emitting display panel”), comprising:
a base substrate ([0041], “the organic light-emitting display panel includes a substrate”), comprising a pixel array region and a peripheral region ([0026], “the organic light-emitting display panel includes a display region AA and a peripheral circuit region NAA outside the display region AA”),
a scan circuit ([0023], “gate driving circuit”), a plurality of power lines (fig. 2, first power signal terminal VGH and second power signal terminal VGL), a first signal line group and a second signal line group in the peripheral region ([0028] and fig. 1, first clock signal terminal A1, second clock signal terminal A2 and trigger signal input terminal B) and on at least one side of the base substrate (fig. 1, NAA outside of AA),
wherein the scan circuit comprises a plurality of cascaded shift register units ([0023], “The gate driving circuit is commonly formed by a plurality of cascaded shift registers”),
the plurality of power lines are configured to provide a plurality of power signals to the
plurality of cascaded shift register units comprised in the scan circuit (fig. 2, first power signal terminal VGH and second power signal terminal VGL);
the first signal line group comprises at least one clock signal line ([0028] and fig. 1, first clock signal terminal A1), and the at least one clock signal line is configured to provide at least one clock signal to the plurality of cascaded shift register units comprised in the scan circuit ([0028], “the shift register 1 is configured to output the gate driving signal via the driving signal output terminal C according the first clock signal inputted from the first clock signal terminal A1”);
the second signal line group comprises a trigger signal line ([0028] and fig. 1, trigger signal input terminal B), and the trigger signal line is configured to be connected to a first-stage shift register unit in the plurality of cascaded shift register units comprised in the scan circuit to provide a trigger signal to the first-stage shift register unit ([0028], “the shift register 1 is configured to output the gate driving signal via the driving signal output terminal C according the first clock signal inputted from the first clock signal terminal A1, the second clock signal inputted from the second clock signal terminal A2 and the trigger signal inputted from the trigger signal input terminal B”);
the at least one clock signal line comprises a first clock signal line for providing a first
clock signal and a second clock signal line for providing a second clock signal ([0028], “the first clock signal inputted from the first clock signal terminal A1, the second clock signal inputted from the second clock signal terminal A2”), and the plurality of power lines comprise a first power line for providing a first power signal and a second power line for providing a second power signal (fig. 2, first power signal terminal VGH and second power signal terminal VGL),
the scan circuit comprises at least one transistor (fig. 2, transistor T3), an extending direction of a channel of the at least one transistor is parallel to an extending direction of the at least one clock signal line (fig. 2, channel of transistor T3 and first clock signal A1 extend in the vertical direction), and the extending direction of the at least one clock signal line is a second direction (fig. 2, the vertical direction);
each of the plurality of cascaded shift register units comprises an input control circuit (fig. 2, transistor T3), an output circuit (fig. 2, transistors T4-T9), and an input circuit (fig. 2, transistor T1);
the input control circuit is configured to input the first power signal to the output circuit
in response to the first clock signal ([0031], “A gate electrode b1 of the third transistor T3 is electrically connected to the gate electrode b1 of the second transistor T2, and a first electrode b2 of the third transistor T3 is electrically connected to a second power signal terminal VGL, a second electrode b3 of the third transistor T3 is electrically connected to a first node N1”), and the input circuit is configured to input an input signal
to the output circuit in response to the first clock signal ([0031], “A gate electrode b1 of the first transistor T1 is configured as a first clock signal terminal A1 of the shift register 1, a first electrode b2 of the first transistor T1 is configured as a trigger signal inputting terminal B of the shift register 1, and a second electrode b3 of the first transistor T1 is electrically connected to a first electrode b2 of the second transistor T2”);
a control terminal of the input control circuit is configured to receive the first clock signal (fig. 2, gate electrode b1 of transistor T3 receives clock signal A1),
the control terminal of the input control circuit comprises a main body portion, and an
extending direction of the main body portion is in a straight line (fig. 2 and [0031], “A gate electrode b1 of the third transistor T3”).
While Zhu discloses signals including first power signal terminal VGH, second power signal terminal VGL, first clock signal terminal A1, second clock signal terminal A2 and trigger signal input terminal B as shown in figs. 1 and 2 and Zhu is silent regarding the specific placement ordering of all the signal lines, it would have been known in the art to have signal lines disposed sequentially as a physical layout choice. In a similar field of endeavor of display devices, Koo discloses the trigger signal line, the first clock signal line, the second clock signal line, the first power line and the second power line are disposed sequentially in a first direction ([0048] and fig. 2A which shows the first peripheral area PA1 as shown in fig. 1, “The line part 135 includes a first voltage line VSL1, a first clock line CKL1, a second clock line CKL2 and a vertical start line STL delivering a plurality of driving signals to the circuit part 137” and fig. 2B shows a second voltage line VSL2 which is formed in the second peripheral area PA2 as shown in fig. 1).
In view of the teachings of Zhu and Koo, it would have been obvious to one of ordinary skill in the art to dispose signal lines sequentially, as taught by Koo, within the system of Zhu, as a known physical arrangement choice of the lines which may help to improve the size/width of a bezel area of a display (Koo: [0007]-[0008]).
Regarding claim 2, the combination of Zhu and Koo further discloses wherein each of the plurality of cascaded shift register units further comprises an output terminal (Zhu: [0034], “driving signal output terminal C”), the output terminal is electrically connected to the output circuit, and the output circuit is configured to output a second clock signal or a second power signal to the output terminal under control of the input signal and the first power signal (Zhu: fig. 2, transistor circuitry).
Regarding claim 3, the combination of Zhu and Koo further discloses wherein the output circuit comprises an output sub-circuit, a first output control sub-circuit, and a second output control sub-circuit (Zhu: fig. 2, transistor circuitry);
the output sub-circuit is electrically connected to a second clock signal line (Zhu: fig. 2, second clock signal terminal A2), the output terminal (Zhu: fig. 2, output terminal C), and a first node (Zhu: fig. 2, node N2), and is configured to output the second clock signal on the second
clock signal line to the output terminal under control of a level of the first node (Zhu: fig. 2, function of transistor T9),
the first output control sub-circuit is electrically connected to the second power line (Zhu: fig. 2, VGH), the output terminal (Zhu: fig. 2, output terminal C), and a second node (Zhu: fig. 2, node N1), and is configured to output the second power signal on the second power line to the output terminal under control of a level of the second node (Zhu: fig. 2, function of transistor T8), and
the second output control sub-circuit is electrically connected to the first node (Zhu: fig. 2, node N2), the second node (Zhu: fig. 2, node N1), a third node (Zhu: fig. 2, node between transistor T4 and T7), the first clock signal line (Zhu: fig. 2, A1), the second clock signal line (Zhu: fig. 2, A2), the first power line (Zhu: fig. 2, VGL) and the second power line (Zhu: fig. 2, VGH), and is configured to control the level of the first node and the level of the second node (Zhu: fig. 2, function of transistors in fig);
the input control circuit is electrically connected to the second node and is configured to
write the first power signal to the second node under control of the first clock signal on the first
power line (Zhu: fig. 2, function of transistor T3), and
the input circuit is electrically connected to the third node and is configured to write the input signal to the third node under control of the first clock signal (Zhu: fig. 2, function of transistor T2).
Regarding claim 4, the combination of Zhu and Koo further discloses wherein the first output control sub-circuit comprises a third transistor (Zhu: fig. 2, transistor T8), a gate electrode of the third transistor is electrically connected to the second node (Zhu: fig. 2, node N1), a first electrode of the third transistor is electrically connected to the second power line (Zhu: fig. 2, VGH), and a second electrode of the third transistor is electrically connected to the output terminal (Zhu: fig. 2, output terminal C);
the second output control sub-circuit comprises a fourth transistor (Zhu: fig. 2, transistor T5), a fifth transistor (Zhu: fig. 2, transistor T4), a sixth transistor (Zhu: fig. 2, transistor T7), and a seventh transistor (Zhu: fig. 2, transistor T6);
a gate electrode of the fourth transistor is electrically connected to the second node (Zhu: fig. 2, node N1), a first electrode of the fourth transistor is electrically connected to the second power line (Zhu: fig. 2, VGH), and a second electrode of the fourth transistor is electrically connected to a first electrode of the fifth transistor (Zhu: fig. 2, transistor T5 connected to transistor T4);
a gate electrode of the fifth transistor is electrically connected to the second clock signal
line (Zhu: fig. 2, A2 signal), and a second electrode of the fifth transistor is electrically connected to the third node (Zhu: fig. 2, node between T4 and T7);
a gate electrode of the sixth transistor is electrically connected to the first power line (Zhu: fig. 2, VGL), a first electrode of the sixth transistor is electrically connected to the third node (Zhu: fig. 2, node between T4 and T7), and a second electrode of the sixth transistor is electrically connected to the first node (Zhu: fig. 2, node N2);
a gate electrode of the seventh transistor is electrically connected to the third node (Zhu: fig. 2, node between T4 and T7), a first electrode of the seventh transistor is electrically connected to the first clock signal line (Zhu: fig. 2, A1), and a second electrode of the seventh transistor is electrically connected to the second node (Zhu: fig. 2, node N1); and
the output sub-circuit comprises an eighth transistor (Zhu: fig. 2, transistor T9), a gate electrode of the eighth transistor is electrically connected to the first node (Zhu: fig. 2, node N2), a first electrode of the eighth transistor is electrically connected to the second clock signal line (Zhu: fig. 2, A2), and a second electrode of the eighth transistor is electrically connected to the output terminal (Zhu: fig. 2, output terminal C).
Regarding claim 5, the combination of Zhu and Koo further discloses wherein the input control circuit comprises a first transistor (Zhu: fig. 2, transistor T3), and a gate electrode of the first transistor is the control terminal of the input control circuit (Zhu: [0031], “A gate electrode b1 of the third transistor T3 is electrically connected to the gate electrode b1 of the second transistor T2, and a first electrode b2 of the third transistor T3 is electrically connected to a second power signal terminal VGL, a second electrode b3 of the third transistor T3 is electrically connected to a first node N1”);
the gate electrode of the first transistor comprises a first gate portion, and the first gate portion is the main body portion (Zhu: [0031], “A gate electrode b1 of the third transistor T3”);
the extending direction of the main body portion is the first direction (Zhu: fig. 2, where the gate of T3 extends in the horizontal direction), and the first direction is perpendicular to the second direction (Zhu: fig. 2, where the second direction is vertical);
the first transistor is configured as the at least one transistor (Zhu: fig. 2, transistor T3), and an extending direction of a channel of the first transistor is a direction from a first electrode of the first transistor to a second electrode of the first transistor (Zhu: fig. 2, where the channel of T3 is between b2 and b3); and
a distance between an orthographic projection of the first gate portion on the base substrate and an orthographic projection of the first electrode of the first transistor on the base substrate in the second direction is a certain value, and a distance between the orthographic projection of the first gate portion on the base substrate and an orthographic projection of the second electrode of the first transistor on the base substrate in the second direction is a certain value (Zhu: [0041], “an active layer structure 3, a gate electrode layer 4 and a source-drain electrode layer (not shown in FIG. 5) along a direction away from the substrate 2. The active layer structure 3 includes an region K1 and an region K2, which are overlapped with the gate electrode layer 4”, where a distance inherently has a value).
Regarding claim 6, the combination of Zhu and Koo further discloses wherein the control terminal of the input control circuit further comprises a protruding portion (Zhu: fig. 2, gate of transistor T1), and the protruding portion is electrically connected to the main body portion (Zhu: fig. 2, gate of transistor T2);
the gate electrode of the first transistor further comprises a second gate portion, and the second gate portion is the protruding portion (Zhu: fig. 2, gate of transistor T1 where two transistors could be a dual gate transistor); and
in the second direction, at least a portion of an orthographic projection of the second gate
portion on the base substrate is between the orthographic projection of the first electrode of the
first transistor on the base substrate and the orthographic projection of the second electrode of
the first transistor on the base substrate (Zhu: fig. 2, transistors T1 and T2 where two transistors could be a dual gate transistor).
Regarding claim 7, the combination of Zhu and Koo further discloses wherein a control terminal of the input circuit is configured to receive the first clock signal, and an extending direction of the control terminal of the input circuit is in a straight line (Zhu: [0031], “a first clock signal terminal A1 of the shift register 1” and where a direction would be in a line).
Regarding claim 8, the combination of Zhu and Koo further discloses wherein the extending direction of the control terminal of the input control circuit is the first direction (Zhu: fig. 2, gates of T2 and T3 are connected in a horizontal direction).
Regarding claim 9, the combination of Zhu and Koo further discloses wherein the input circuit comprises a second transistor (Zhu: fig. 2, transistor T2), the control terminal of the input circuit comprises a gate electrode of the second transistor (Zhu: fig. 2, b1 is a gate electrode of the transistors), and
the gate electrode of the first transistor and the gate electrode of the second transistor are arranged in the first direction (Zhu: fig. 2, gates of T2 and T3 are connected in a horizontal direction).
Regarding claim 10, the combination of Zhu and Koo further discloses wherein each of the plurality of cascaded shift register units further comprises a first wiring portion (Zhu: figs 1 and 2, horizontal direction of line A1),
the first gate portion of the gate electrode of the first transistor is directly connected to a first end of the first wiring portion (Zhu: fig. 2, line A1 connected to gate of T3 in the horizontal direction),
the gate electrode of the second transistor is directly connected to a second end of the first wiring portion (Zhu: fig. 2, line A1 connected to gate of T2 in the horizontal direction), and
the first wiring portion extends in a straight line along the first direction (Zhu: fig. 2, gates of T1 and T3 are connected in a horizontal direction).
Regarding claim 11, the combination of Zhu and Koo further discloses wherein each of the plurality of cascaded shift register units further comprises a second wiring portion (Zhu: fig. 1, lines A1 in vertical direction),
the second wiring portion is electrically connected to the first wiring portion (Zhu: fig. 1, lines A1 connected in vertical and horizontal directions), and
the second wiring portion extends along the second direction (Zhu: fig. 1, lines A1 in vertical directions).
Regarding claim 12, the combination of Zhu and Koo further discloses wherein each of the plurality of cascaded shift register units further comprises a third wiring portion (Zhu: fig. 2, line A1), and the third wiring portion extends along the first direction (Zhu: fig. 2, section of A1 line in the horizontal direction);
a first end of the third wiring portion is electrically connected to the first clock signal line
providing the first clock signal (Zhu: fig. 2, A1 input terminal), and a second end of the third wiring portion is electrically connected to the gate electrode of the first transistor (Zhu: fig. 2, gate of T2 transistor); and
the third wiring portion is configured to transmit the first clock signal provided by the first clock signal line to the gate electrode of the first transistor (Zhu: [0028], “a first clock signal terminal A1”).
Regarding claim 13, the combination of Zhu and Koo further discloses further comprising: a semiconductor layer, a first insulating layer, a first conductive layer, a second insulating layer, a second conductive layer, a third insulating layer, and a third conductive layer (Zhu: [0041], “an active layer structure 3, a gate electrode layer 4 and a source-drain electrode layer” where insulating layers would be between the active layers),
wherein the semiconductor layer is on the base substrate, the first insulating layer is on a side of the semiconductor layer away from the base substrate, the first conductive layer is on a side of the first insulating layer away from the semiconductor layer, the second insulating layer is on a side of the first conductive layer away from the first insulating layer, the second conductive layer is on a side of the second insulating layer away from the first conductive layer, the third insulating layer is on a side of the second conductive layer away from the second insulating layer, and the third conductive layer is on a side of the third insulating layer away from the second conductive layer (Zhu: [0041], “As shown in FIG. 5, the organic light-emitting display panel includes a substrate 2, both of the eighth transistor T8 and the ninth transistor T9 include an active layer structure 3, a gate electrode layer 4 and a source-drain electrode layer (not shown in FIG. 5) along a direction away from the substrate 2. The active layer structure 3 includes an region K1 and an region K2, which are overlapped with the gate electrode layer 4. That is, the overlapped region K1 is the channel of the eighth transistor T8, and the overlapped region K2 is the channel of the ninth transistor T9”).
Regarding claim 14, the combination of Zhu and Koo further discloses wherein the first electrode of the eighth transistor is electrically connected to the gate electrode of the fifth transistor through a first connection component (Zhu: fig. 2, node N2);
the gate electrode of the fifth transistor is in the first conductive layer, and the first connection component is in the third conductive layer (Zhu: [0041], a gate electrode layer 4);
the first connection component is electrically connected to the gate electrode of the fifth transistor through at least one first via hole, and the at least one first via hole is in the second insulating layer and the third insulating layer, and penetrates the second insulating layer and the third insulating layer (Zhu: [0041], “The active layer structure 3 includes an region K1 and an region K2, which are overlapped with the gate electrode layer 4”); and
an orthographic projection of the at least one first via hole on the base substrate is on a side of an orthographic projection of the gate electrode of the fifth transistor on the base substrate away from an orthographic projection of the gate electrode of the eighth transistor on the base substrate in a first direction perpendicular to the second direction (Zhu: fig. 5 and [0041], “As shown in FIG. 5, the organic light-emitting display panel includes a substrate 2, both of the eighth transistor T8 and the ninth transistor T9 include an active layer structure 3, a gate electrode layer 4 and a source-drain electrode layer (not shown in FIG. 5) along a direction away from the substrate 2”).
Regarding claim 15, the combination of Zhu and Koo further discloses wherein in a case where the at least one first via hole comprises a plurality of first via holes, the plurality of first via holes are arranged in the first direction (Koo: fig. 4, circuit area CA with transistors and capacitors in a horizontal direction).
Regarding claim 16, the combination of Zhu and Koo further discloses wherein in a case where the input control circuit comprises a first transistor, the gate electrode of the fourth transistor is electrically connected to a second electrode of the first transistor and the second electrode of the seventh transistor through a second connection component, a third connection component, and a fourth connection component (Zhu: fig. 2, gate of T5 connected to b3 of T6);
the second connection component and the fourth connection component are in the third conductive layer, and the third connection component is in the second conductive layer (Zhu: fig. 2, connections at node N1);
the gate electrode of the fourth transistor is in the first conductive layer, the gate electrode of the fourth transistor is electrically connected to the second connection component through a fifth via hole, and the fifth via hole is in the second insulating layer and the third insulating layer, and penetrates the second insulating layer and the third insulating layer (Koo: [0073], “the gate connection line GCL is patterned from a metal layer substantially identical to a control electrode CE1 of the first transistor T1. The gate insulation layer 102 is formed on a base substrate 101 on which the gate connection line GCL is formed. The source connection line SCL is disposed on the gate insulation layer 102, which is partially overlapped by the gate connection line GCL. In one exemplary embodiment, the source connection line SCL is patterned from a metal layer substantially identical to the input electrode IE1 and the output electrode OE1 of the first transistor T1”);
the second connection component is electrically connected to the third connection component through a sixth via hole, and the sixth via hole is in the third insulating layer and penetrates the third insulating layer (Koo: [0080], “The second capacitor Cgs2 may be formed by the gate electrode pattern GEP, the portion of the source electrode pattern SEP which partially overlaps the gate electrode pattern GEP, and the gate insulation layer 102 disposed between the gate electrode pattern GEP and the source electrode pattern SEP”);
the third connection component is electrically connected to the fourth connection component through a seventh via hole, and the seventh via hole is in the third insulating layer and penetrates the third insulating layer (Koo: [0079], “a protection insulation layer 103 is formed on the base substrate 101 on which the source electrode pattern SEP is already formed. A transparent organic insulation layer or a non-transparent organic insulation may be formed on the protection insulation layer 103”); and
the second electrode of the first transistor and the second electrode of the seventh transistor are in the semiconductor layer, the second electrode of the first transistor is electrically connected to the fourth connection component through an eighth via hole, the second electrode of the seventh transistor is electrically connected to the fourth connection component through a ninth via hole, and the eighth via hole and the ninth via hole are in the first insulating layer, the second insulating layer, and the third insulating layer, and penetrate the first insulating layer, the second insulating layer, and the third insulating layer (Koo: [0081], “the first metal connection line and the second metal connection line which connect the plurality of transistors to each other are overlapped with each other to form the first capacitor Cgs1 of the boosting capacitor Cgs, so that an area used for forming the second capacitor Cgs2 may be decreased. As a result, an area where the gate driving circuit 110 is formed may be decreased”).
Regarding claim 17, the combination of Zhu and Koo further discloses wherein the fifth via hole and the sixth via hole are arranged in the second direction (Koo: fig. 5B, input and output electrodes IE1 and OE1 arranged in a direction).
Regarding claim 18, the combination of Zhu and Koo discloses a display device (Zhu: [0010], “the present disclosure further provides an organic light-emitting display device including the organic light-emitting display panel”), comprising the display substrate according to claim 1.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Xiao (US PGPub 2016/0189648) discloses a circuit schematic diagram of a GOA circuit (fig. 1).
Qian (US PGPub 2015/0340102) discloses “Specifically, referring to FIG. 2, an embodiment provides a TFT array substrate 1, including: a plurality of gate lines 2, which are generally disposed within a display area AA; and a gate driving circuit 3 connected to the gate lines 2, with the gate driving circuit 3 including multiple stages of shift registers SRs, where, odd-numbered stages of shift registers from the multiple stages of shift registers (odd SRs) are cascaded-connected to each other, even-numbered stages of shift registers from the multiple stages of shift registers (even SRs) are cascaded-connected to each other, and the odd-numbered stages of shift registers (odd SRs) and the even-numbered stages of shift registers (even SRs) are respectively disposed at both ends of the gate lines 2” ([0018]).
Any inquiry concerning this communication or earlier communications from the examiner should be directed to EMILY J FRANK whose telephone number is (571)270-7255. The examiner can normally be reached Monday-Thursday 8AM-6PM.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Benjamin C Lee can be reached at (571)272-2963. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/EJF/
/BENJAMIN C LEE/Supervisory Patent Examiner, Art Unit 2629