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The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
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Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
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Claim 1 is rejected on the ground of nonstatutory double patenting as being unpatentable over claim 1 of U.S. Patent No. 12,334,022 (resulting from App. No. 18/618,413) in view of Kim et al. (US 2019/0164478).
claim 1 of this application
claim 1 of U.S. Patent No. 12,334,022
1. A shift register unit, comprising a first sub-circuit, a leakage prevention circuit and a blanking input sub-circuit, wherein
the first sub-circuit comprises a first input circuit and a first output circuit, the first input circuit is configured to control a level of a first node in response to a first input signal, and the first output circuit is configured to output a shift signal and a first output signal under control of the level of the first node;
the blanking input sub-circuit comprises a first transmission circuit, the first transmission circuit comprises a first transmission transistor and a second transmission transistor;
the leakage prevention circuit is connected to the first node, a first voltage and a leakage prevention node;
a gate electrode of the first transmission transistor is configured to receive a first clock signal, a first electrode of the first transmission transistor is connected to a fourth node, and a second electrode of the first transmission transistor is connected to the leakage prevention node; and
a gate electrode of the second transmission transistor is configured to receive the first clock signal, a first electrode of the second transmission transistor is connected to the leakage prevention node, and a second electrode of the second transmission transistor is connected to the first node,
wherein the blanking input sub-circuit further comprises a selection control circuit, and wherein the selection control circuit comprises a fourth input transistor and a first capacitor, a gate electrode of the fourth input transistor is configured to receive a selection control signal, a first electrode of the fourth input transistor is configured to receive a second input signal, and a second electrode of the fourth input transistor is connected to a third node.
1. A shift register unit, comprising a first sub-circuit, a leakage prevention circuit and a blanking input sub-circuit, wherein
the first sub-circuit comprises a first input circuit and a first output circuit, the first input circuit is configured to control a level of a first node in response to a first input signal, and the first output circuit is configured to output a shift signal and a first output signal under control of the level of the first node;
the blanking input sub-circuit comprises a first transmission circuit, the first transmission circuit comprises a first transmission transistor and a second transmission transistor;
the leakage prevention circuit is connected to the first node, a first voltage and a leakage prevention node;
a gate electrode of the first transmission transistor is configured to receive a first clock signal, a first electrode of the first transmission transistor is connected to a fourth node, and a second electrode of the first transmission transistor is connected to the leakage prevention node; and
a gate electrode of the second transmission transistor is configured to receive the first clock signal, a first electrode of the second transmission transistor is connected to the leakage prevention node, and a second electrode of the second transmission transistor is connected to the first node.
As can be seen from the comparison above, claim 1 of this instant application is different from claim 1 of U.S. Patent No. 12,334,022 in that the former further includes the features “wherein the blanking input sub-circuit further comprises a selection control circuit, and wherein the selection control circuit comprises a fourth input transistor and a first capacitor, a gate electrode of the fourth input transistor is configured to receive a selection control signal, a first electrode of the fourth input transistor is configured to receive a second input signal, and a second electrode of the fourth input transistor is connected to a third node” (support is found in originally filed Figs. 9-13, i.e., “selection control circuit” is selection control circuit 310 of blanking input sub-circuits 300, which includes fourth input transistor B4 reading on “fourth input transistor” in the instant claim, fifth input transistor B5, and first capacitor C1 reading on “first capacitor” in the instant claim).
However, the differentiating features are not new in the related art.
Kim, for instance, teaches in Fig. 5 a blanking input sub-circuit (i.e., blank time first node controller 21) comprises a selection control circuit (i.e., transistors TA, TB and capacitor C1), and wherein the selection control circuit comprises a fourth input transistor (i.e., transistor TA) and a first capacitor (i.e., capacitor C1), a gate electrode (i.e., gate electrode of TA) of the fourth input transistor is configured to receive a selection control signal (i.e., line select pulse LSP), a first electrode (i.e., upper electrode of TA) of the fourth input transistor is configured to receive a second input signal (i.e., set signal CP(k)), and a second electrode (i.e., lower electrode of TA) of the fourth input transistor is connected to a third node (i.e., node M).
Before the effective filing date of the invention, it would have been obvious for one ordinary skill in the art to combine Kim’s technique with the invention of claim 1 of U.S. Patent No. 12,334,022 incorporating Kim’s technique in the blanking input sub-circuit of claim 1 of this instant application to achieve a necessarily required selection control functionality providing a well-controlled timing for a blank period of each gate line (Kim: [0080]).
Claim 2 is rejected on the ground of nonstatutory double patenting as being unpatentable over claim 2 of U.S. Patent No. 12,334,022 (resulting from App. No. 18/618,413) in view of Kim et al. (US 2019/0164478).
Claim 3 is rejected on the ground of nonstatutory double patenting as being unpatentable over claim 3 of U.S. Patent No. 12,334,022 (resulting from App. No. 18/618,413) in view of Kim et al. (US 2019/0164478).
Claim 4 is rejected on the ground of nonstatutory double patenting as being unpatentable over claim 4 of U.S. Patent No. 12,334,022 (resulting from App. No. 18/618,413) in view of Kim et al. (US 2019/0164478).
Claim 5 is rejected on the ground of nonstatutory double patenting as being unpatentable over claim 5 of U.S. Patent No. 12,334,022 (resulting from App. No. 18/618,413) in view of Kim et al. (US 2019/0164478).
Claim 6 is rejected on the ground of nonstatutory double patenting as being unpatentable over claim 6 of U.S. Patent No. 12,334,022 (resulting from App. No. 18/618,413) in view of Kim et al. (US 2019/0164478).
Claim 7 is rejected on the ground of nonstatutory double patenting as being unpatentable over claim 8 of U.S. Patent No. 12,334,022 (resulting from App. No. 18/618,413) in view of Kim et al. (US 2019/0164478).
Claim 8 is rejected on the ground of nonstatutory double patenting as being unpatentable over claim 9 of U.S. Patent No. 12,334,022 (resulting from App. No. 18/618,413) in view of Kim et al. (US 2019/0164478).
Claim 9 is rejected on the ground of nonstatutory double patenting as being unpatentable over claim 10 of U.S. Patent No. 12,334,022 (resulting from App. No. 18/618,413) in view of Kim et al. (US 2019/0164478).
Claim 10 is rejected on the ground of nonstatutory double patenting as being unpatentable over claim 11 of U.S. Patent No. 12,334,022 (resulting from App. No. 18/618,413) in view of Kim et al. (US 2019/0164478).
Claim 11 is rejected on the ground of nonstatutory double patenting as being unpatentable over claim 12 of U.S. Patent No. 12,334,022 (resulting from App. No. 18/618,413) in view of Kim et al. (US 2019/0164478).
Claim 12 is rejected on the ground of nonstatutory double patenting as being unpatentable over claim 13 of U.S. Patent No. 12,334,022 (resulting from App. No. 18/618,413) in view of Kim et al. (US 2019/0164478).
Claim 13 is rejected on the ground of nonstatutory double patenting as being unpatentable over claim 14 of U.S. Patent No. 12,334,022 (resulting from App. No. 18/618,413) in view of Kim et al. (US 2019/0164478).
Claim 14 is rejected on the ground of nonstatutory double patenting as being unpatentable over claim 15 of U.S. Patent No. 12,334,022 (resulting from App. No. 18/618,413) in view of Kim et al. (US 2019/0164478).
Claim 15 is rejected on the ground of nonstatutory double patenting as being unpatentable over claim 16 of U.S. Patent No. 12,334,022 (resulting from App. No. 18/618,413) in view of Kim et al. (US 2019/0164478).
Claim 16 is rejected on the ground of nonstatutory double patenting as being unpatentable over claim 17 of U.S. Patent No. 12,334,022 (resulting from App. No. 18/618,413) in view of Kim et al. (US 2019/0164478).
Claim 17 is rejected on the ground of nonstatutory double patenting as being unpatentable over claim 18 of U.S. Patent No. 12,334,022 (resulting from App. No. 18/618,413) in view of Kim et al. (US 2019/0164478).
Claim 18 is rejected on the ground of nonstatutory double patenting as being unpatentable over claim 19 of U.S. Patent No. 12,334,022 (resulting from App. No. 18/618,413) in view of Kim et al. (US 2019/0164478) for substantially the same rationale as applied to claim 1 (Note: same differentiating features identified in claim 18 as in claim 1).
Claim 19 is rejected on the ground of nonstatutory double patenting as being unpatentable over claim 20 of U.S. Patent No. 12,334,022 (resulting from App. No. 18/618,413) in view of Kim et al. (US 2019/0164478).
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure:
US 2018/0337682 by Takasugi et al. teaches in Fig. 5 sensing control block BK1a that reads on the selection control circuit in claim 1 and claim 18 of this instant application.
US 2020/0074937 by Choi teaches in Fig. 10 sensing line selector BLK5 that reads on the selection control circuit in claim 1 and claim 18 of this instant application.
KR 20150188925 teaches in Figs. 7-8 sampling unit (BK1) that reads on the selection control circuit in claim 1 and claim 18 of this instant application, the sampling unit (BK1) activating the node Q in the vertical blank period (BP) according to the activation potential of the node M.
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/XUEMEI ZHENG/Primary Examiner, Art Unit 2629