NON-FINAL OFFICE ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 24-29 and 32-40 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by U.S. Patent Pub. No. 2014/0218316 to Chen et al. (hereinafter Chen).
Chen discloses:
24. A device comprising:
a digital comparator to receive a digital input value (paras. [0024], [0034], and Fig. 2, processing module 210), wherein the digital comparator generates a plurality of outputs comprising at least a first output based on a first programmable threshold value and a second output based on a second programmable threshold value, the first programmable threshold value different from the second programmable threshold value (paras. [0036], [0037] and Fig. 3, steps 111-1 and 111-2, and T0 and T1);
a first counter coupled to the first output of the plurality of outputs of the digital comparator (paras. [0036], [0037] and Fig. 3, first counting value C1);
a second counter coupled to the second output of the plurality of outputs of the digital comparator (paras. [0036], [0038] and Fig. 3, first counting value C2), and
an output controller with a first input coupled to an output of the first counter and a second input coupled to an output of the second counter, the output controller to generate a filtered fault event signal based at least partially on the output of the first counter and the output of the second counter (paras. [0024], [0037], [0038] – protection mechanism initiated depending on output of Fig. 3, step 317).
25. The device as claimed in claim 24, wherein the first programmable threshold value comprises at least one of an upper limit applied to the digital input value and a lower limit applied to the digital input value (paras. [0020]-[0023]).
26. The device as claimed in claim 24, wherein the second programmable threshold value comprises at least one of a range of allowed digital input values and a range of restricted digital input values (paras. [0020]-[0023]).
27. The device as claimed in claim 24, wherein the first and second counter respectively to count samples of a respective one of the plurality of outputs of the digital comparator (paras. [0037], [0038] and Fig. 3, steps 311, 313).
28. The device as claimed in claim 24, wherein the second counter comprises a decoder to reset the first counter based on the value of the second counter and a programmable condition (para. [0036] and Fig. 3, steps 315, 311, 312).
29. The device as claimed in claim 24, wherein the output controller asserts a fault event output based at least on a value of the first counter, a first programmable counter limit, a value of the second counter, and a second programmable counter limit (paras. [0036]-[0038] and Fig. 3).
32. The device as claimed in claim 29, wherein the device is a programmable peripheral device in a microcontroller (paras. [0011], [0033]).
33. A microcontroller comprising a programmable threshold violation filter, wherein the programmable threshold violation filter comprises:
a digital comparator to receive a digital input value (paras. [0024], [0034], and Fig. 2, processing module 210), wherein the digital comparator generates a plurality of outputs based on a first programmable threshold value and a second programmable threshold value, the first programmable threshold value different from the second programmable threshold value (paras. [0036], [0037] and Fig. 3, steps 111-1 and 111-2, and T0 and T1);
a first counter coupled to at least one of the plurality of outputs of the digital comparator (paras. [0036], [0037] and Fig. 3, first counting value C1); and
an output controller with a first input coupled to an output of the first counter, the output controller to assert a fault event output when the first counter exceeds a first programmable counter limit and to reset the fault event signal when the first counter exceeds a second programmable counter limit (paras. [0024], [0037] – protection mechanism initiated depending on output of Fig. 3, step 317).
34. The microcontroller as claimed in claim 33, comprising a second counter coupled to at least one of the plurality of outputs of the digital comparator and an output controller with a second input coupled to an output of the second counter (paras. [0036], [0038] and Fig. 3, second counting value C2), the output controller to assert a fault event output when the first counter exceeds the first programmable counter limit and to reset the fault event signal when the second counter exceeds the second programmable counter limit (paras. [0024], [0037], [0038] – initiation of protection mechanism or reset counters according to outputs of counters).
35. A method comprising:
providing a digital comparator to generate a plurality of outputs based upon an input value (paras. [0024], [0034], and Fig. 2, processing module 210);
incrementing a first counter based on a first output of the digital comparator, the first output of the digital comparator based on a first programmable threshold (paras. [0036], [0037] and Fig. 3, first counting value C1);
incrementing a second counter based on a second output of the digital comparator and an output of the first counter, resetting the second counter based on a programmable condition; and, asserting an output based on the first counter value and the second counter value and a programmable condition (paras. [0036], [0038] and Fig. 3, second counting value C2);
resetting the first counter and the second counter based on a programmable condition (para. [0036] and Fig. 3, steps 315, 311, 312), and
asserting an output based on the value of the first counter, a value of the second counter, and the programmable condition (paras. [0024], [0037], [0038] – initiation of protection mechanism or reset counters according to outputs of counters).
36. A method as claimed in claim 35, comprising setting the digital comparator with at least one of an upper limit on the input value and a lower limit on the input value (paras. [0020]-[0023]).
37. A method as claimed in claim 35, comprising setting the digital comparator with at least one of a range of allowed input values and a range of restricted input values (paras. [0020]-[0023]).
38. The method as claimed in claim 35, wherein resetting the first counter based on the programmable condition comprises resetting the first counter based on the value of the second output of the digital comparator, and wherein resetting the second counter based on the programmable condition comprises resetting the second counter based on the value of the second counter exceeding a programmable second counter limit (paras. [0036], [0038] and Fig. 3, steps 315, 311, 312).
39. The method as claimed in claim 35, wherein resetting the first counter based on the programmable condition comprises resetting the first counter based on the value of the second counter exceeding a programmable second counter limit and wherein resetting the second counter based on the programmable condition comprises resetting the second counter based on the value of the second counter exceeding a programmable second counter limit (paras. [0036], [0038] and Fig. 3, steps 315, 311, 312).
40. The method as claimed in claim 35, wherein generating the output comprises setting a first output value based on the value of the first counter exceeding a programmable first counter limit and generating a second output value based on the value of the second counter exceeding a programmable second counter limit (paras. [0024], [0037], [0038]).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claims 30-31 are rejected under 35 U.S.C. 103 as being unpatentable over Chen in view of U.S. Patent Pub. No. 2016/0266605 to Hegde.
Chen discloses:
30. The device as claimed in claim 29, wherein the first and second counters respectively comprise a reset input (para. [0036] and Fig. 3, step 312).
Chen does not disclose expressly wherein the first and second counters respectively comprise a clock input.
Hegde teaches a counter comprising a clock input (paras. [0020],[0021] and Fig. 1, PCOUNTER 104, SCOUNTER 105).
Before the effective filing date of the invention, it would have been obvious to a person of ordinary skill in the art to modify Chen by having counters with a clock input, as taught by Hegde. A person of ordinary skill in the art would have been motivated to do so in order to implement a watchdog timer which is capable of detecting errors before the restart of a loop, which may be caused by clock failures, as discussed by Hegde (paras. [0004], [0005], [0030]).
Modified Chen discloses:
31. The device as claimed in claim 30, wherein the clock inputs of the first and second counter are to receive a clock signal having a programmable frequency (Hegde – para. [0036]).
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13.
The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/patent/patents-forms. The actual filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIA /25, or PTO/AIA /26) should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to www.uspto.gov/patents/apply/applying-online/eterminal-disclaimer.
Claims 24-30 and 32-40 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1-8 of U.S. Patent No. 12,314,123 (hereinafter ‘123). Although the claims at issue are not identical, they are not patentably distinct from each other because claims 1-8 of ‘123 contain every element of claims 24-30 and 32-40 of the instant application and thus anticipate the claims of the instant application. Claims of the instant application therefore are not patently distinct from the earlier patent claims and as such are unpatentable over obvious-type double patenting. A later application claim is not patentably distinct from an earlier claim if the later claim is anticipated by the earlier claim.
Conclusion
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/PHILIP GUYTON/Primary Examiner, Art Unit 2113
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