Detailed Action
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
The information disclosure statement (IDS) submitted in on 04/30/2025 and
06/24/2025 are being considered by the examiner.
Priority
This application is claiming priority of a Provisional of 63/644145 filed on
May 8, 2024 is acknowledged. Acknowledge is made of the domestic priority data as claimed by applicant application.
Specification
The lengthy specification has not been checked to the extent necessary to determine the presence of all possible minor errors. Applicant’s cooperation is requested in correcting any errors of which applicant may become aware in the specification.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claims 1-3, and 14-15 are rejected under 35 U.S.C. 103 as being unpatentable over Roberts et al. (US-20230058668-A1 hereafter Roberts) in further view of Drehmel et al. (US-20060015753-A1 hereafter Drehmel).
Regarding claim 1 Roberts discloses a memory encryption circuit comprising:
a first cache comprising a first plurality of cache entries, wherein each cache entry of the first plurality of cache entries has a first persistent valid flag and a first data field for plaintext data (see Roberts par.0060: “The cache line structure 300 further includes a validity field 306 (V) and a modify field 308 (D). The validity field 306 can include a bit that indicates whether the cache line is used (e.g., whether the cache line includes valid data) or is unused. The modify field 308 can include a bit that indicates whether the cache line includes the same data as in main memory or is modified (sometimes referred to as dirty). Par.0059: “the data field 304 comprises encrypted data and in other examples the data field 304 comprises unencrypted data.”);
cryptographic circuitry (see Roberts par.0053: “cryptographic processing circuitry”);
control circuitry (see Roberts par.0050: “The controller 202 can include or use the programmable atomic unit 208 to carry out operations using information in a memory device 204.”), wherein the control circuitry is to:
in a power-off process (see Roberts par.0086: “monitoring the cache security timer for an expiration condition (power-off process). Upon expiration of the cache security timer, the cryptographic controller 404 can scan all or a designated portion of the cache memory and identify any cache lines that are unencrypted.”),
cause the cryptographic circuitry to encrypt the plaintext data of one or more cache entries of the first plurality of cache entries having the first persistent valid flag set to obtain ciphertext data for the one or more cache entries (see Roberts par.0071: “the cryptographic memory system 400 can include the second cryptographic engine 416 to help facilitate or optimize some transactions between the cache memory 410 and main memory, such as via the memory controller 414. For example, the second cryptographic engine 416 can include an encryption circuit configured to encrypt any unencrypted data that is evicted from the cache memory 410.”); and
store the ciphertext data in a memory system coupled to the memory encryption
circuit (see Roberts par.0084: “the cache data write example 600 can include, at block 610, writing the encrypted data to main memory using the memory controller 414. The encrypted data can be written to main memory together with its corresponding key identifier for later user.”); and
Roberts does not explicitly teach in a power-on process, load the ciphertext data from the memory system for the one or more cache entries having the first persistent valid flag set; cause the cryptographic circuitry to decrypt the ciphertext data to obtain the plaintext data for the one or more cache entries; and store the plaintext data in the one or more cache entries of the first cache.
In this instance examiner notes the teaching of prior art reference Drehmel.
With regards to applicant’s claim limitation element of, in a power-on process (see Drehmel par.0041: “the system may not allow further data to be read from external memory until a reset event, such as a power-on-reset, occurs” Examiner interpret that that the retrieval of the secure data happens during power-on process. ),
load the ciphertext data from the memory system for the one or more cache entries having the first persistent valid flag set (see Drehmel par.0038-0039: “FIG. 4 is a flow diagram of exemplary operations 400, that illustrate how the ICVs stored in secure RAM 160 may be utilized during retrieval of secure data. The operations begin, at step 402, by fetching a block of data from external memory…the secure ciphertext data may be routed to a decryption engine 154 of the security component 150 for decryption. The decryption engine 154 decrypts the secure data”);
cause the cryptographic circuitry to decrypt the ciphertext data to obtain the plaintext data for the one or more cache entries(see Drehmel par.0039: “the data is ciphertext and, therefore, is decrypted, at step 406. For example, referring back to FIG. 2, the secure ciphertext data may be routed to a decryption engine 154 of the security component 150 for decryption.”); and
store the plaintext data in the one or more cache entries of the first cache (see Drehmel par.0039: “The decryption engine 154 decrypts the secure data and returns the secure data decrypted (as plaintext). If integrity is not enabled, as determined at step 407, the (plaintext) secure data is forwarded to cache, as no validation is required.”).
Therefore It would have been obvious to someone of ordinary skill in the art
before the effective filing date of the claimed invention to have combined Roberts teaching “compute-near-memory systems, can use data or memory encryption to help protect information from unwanted use or observation. Encryption can help avoid data observation by other systems or actors who impermissibly gain access to a physical (e.g., non-volatile) memory device”, (see Roberts par.002) with Drehmel teaching because Drehmel teaching of, “the CPU 110 may include a security component 150 used to encrypt secure data prior to transmission over the FSB 128 by the FSB interface 120. Upon later retrieval of the encrypted data, the security component 150 may also be used to decrypt the encrypted secure data prior to passing it into the L2 cache 116 for use by one or more of the processor cores 112.”, (see Drehmel par.0029). The reason to combined would have been to protect data received from external main memory which is less secure and prone to tampering.
Regarding claim 14 is method claim that recites similar limitations as the
method claim 1 and is rejected based on the same rational as claim 1.
Regarding claim 2 Roberts in view of Drehmel disclose the memory encryption circuit of claim 1, Roberts further teaches wherein each cache entry of the first plurality of cache entries further comprises a first modified flag (see Roberts par.0060: “The cache line structure 300 further includes a validity field 306 (V) and a modify field 308 (D). The validity field 306 can include a bit that indicates whether the cache line is used (e.g., whether the cache line includes valid data) or is unused. The modify field 308 can include a bit that indicates whether the cache line includes the same data as in main memory or is modified (sometimes referred to as dirty)., wherein, in the power-off process, the control circuitry is to cause the cryptographic circuitry to encrypt the plaintext data of the one or more cache entries having the first persistent valid flag and the first modified flag set to obtain the ciphertext data for the one or more cache entries (see Roberts par.0086: “security timer for an expiration condition. Upon expiration of the cache security timer, the cryptographic controller 404 can scan all or a designated portion of the cache memory and identify any cache lines that are unencrypted. For example, the cryptographic controller 404 can search the cache memory for any lines with an encryption status field 310 that indicates information in the data field 304 is unencrypted. The cryptographic controller 404 can command the first cryptographic engine 412 to encrypt any lines that were identified as including unencrypted data.”).
Regarding claim 15 is method claim that recites similar limitations as the
method claim 2 and is rejected based on the same rational as claim 2.
Regarding claim 3 Roberts in view of Drehmel disclose the memory encryption circuit of claim 1, Roberts further teaches wherein each cache entry of the first plurality of cache entries further comprises a tag field for tag data associated with the plaintext data (see Roberts Fig. 3 and par.0058: “cache line structure 300 includes a tag field 302 (TAG) that facilitates translation from a cache address to a particular CPU address. When a CPU or host attempts to access a particular address and a matching cache line is available, then the access is successful and is considered a cache hit.”).
Claims 4 and 6 are rejected under 35 U.S.C. 103 as being unpatentable over Roberts in view of Drehmel as applied to claim 1, in further view of MEDWED et al. (US 20200380140 A1 hereafter MEDWED).
Regarding claim 4 Roberts in view of Drehmel disclose the memory encryption circuit of claim 1, Roberts in view of Drehmel do not explicitly teach however examiner notes the teaching of prior art reference MEDWED.
With regards to applicant’s claim limitation of, further comprising:
a second cache comprising a second plurality of cache entries, wherein each cache entry of the second plurality of cache entries has a second persistent valid flag and a second data field for metadata associated with the respective plaintext data of the corresponding cache entry of the first plurality of cache entries (see MEDWED par.0057-0060: “a second cache (L2) 520… cache L2 stores the data in encrypted form and cache L1 stores the data both in encrypted and decrypted form. Cache L1 (or a different storage area) may also store memory safety tags for the data stored in the L2 cache and metadata… each pointer may include an address and a memory safety tag. The address may correspond to a cache line in L2, which stores data which is encrypted using the key and a unique memory safety tag. …The metadata may include a first control bit T and a second control bit A. The first control bit T may keep track of the tag that was used to decrypt the data stored in the L1 cache. The second control bit A may provide an indication of whether the data has been accessed by the first processor (e.g., CPU) 10… the L1 cache to have two slots for each cache line 610 in the second cache L2. The first slot 620 stores a copy of the encrypted data stored in a corresponding cache line in L2. The second slot 630 stores the decrypted version of the cache line data, e.g., the cache line data from L2 that has been decrypted by the cipher engine 30. The first cache L1 also stores the metadata T and A for each cache line.”).
Therefore It would have been obvious to someone of ordinary skill in the art
before the effective filing date of the claimed invention to have combined Roberts in view Drehmel teaching of claim 1 with MEDWED teaching because of MEDWED teaching of, “The metadata T and A may be used to resolve problems which arise, for example, when an attempt is made to access and decrypt data from the L2 cache using an incorrect or unintended memory safety tag, e.g., prefetching could request a cache line which does not belong to the pointer that was used to encrypt the data at that cache line.”, (see MEDWED par.0059).
Regarding claim 6 Roberts in view of Drehmel, and MEDWED the memory encryption circuit of claim 4, Roberts further teaches wherein:
each cache entry of the first plurality of cache entries further comprises a first tag field for first tag data associated with the plaintext data (see Roberts par.0058-0061: “cache line structure 300 includes a tag field 302 (TAG) that facilitates translation from a cache address to a particular CPU address… The cache line structure 300 further includes a data field 304 (DATA). The size of the data field 304 can be fixed or variable and can be configured to hold data of various types. In some examples, the data field 304 comprises encrypted data and in other examples the data field 304 comprises unencrypted data… further includes a validity field 306 (V) and a modify field 308 (D)… further includes an encryption status field 310 (E), an access counter 312 (F), and a key field 314 (KEY ID). In an example, the encryption status field 310 can include one or more bits set to indicate whether information elsewhere in the same cache line (e.g., in the data field 304) is encrypted or unencrypted.”); and
Roberts in view of Drehmel do not explicitly teach however examiner notes the teaching of prior art reference MEDWED.
With regards to applicant’s claim limitation of, each cache entry of the second plurality of cache entries further comprises a second tag field for second tag data associated with the metadata (see MEDWED par.0058-0059: “each pointer may include an address and a memory safety tag. The address may correspond to a cache line in L2, which stores data which is encrypted using the key and a unique memory safety tag. …The metadata may include a first control bit T and a second control bit A. The first control bit T may keep track of the tag that was used to decrypt the data stored in the L1 cache.”).
Therefore It would have been obvious to someone of ordinary skill in the art
before the effective filing date of the claimed invention to have combined Roberts in view of Drehmel, and MEDWED teaching of claim 4 with MEDWED teaching because of, “The pointer includes, for example, a memory safety tag generated for the data and, for example, a logical address for storing the data in the second cache L2.”, (see MEDWED par.0069).
Claim 5 is rejected under 35 U.S.C. 103 as being unpatentable over Roberts in view of Drehmel, and MEDWED as applied to claim 4, in further view of Erickson et al. (US-20240143197-A1 hereafter Erickson).
Regarding claim 5 Roberts in view of Drehmel, and MEDWED disclose the memory encryption circuit of claim 4, Roberts in view of Drehmel, and MEDWED do not explicitly teach however examiner notes the teaching of prior art reference Erickson.
With regards to applicant’s claim limitation of, wherein the metadata comprises a message authentication code (MAC) of the respective plaintext data of the corresponding cache entry of the first plurality of cache entries (see Erickson Fig 3. And par.0037: “a cache line 202 in which a MAC 122 is stored and transferred in side-band metadata 204 associated with cache line data 206 and a cache line 208 in which a MAC 122 is stored and transferred as in-band metadata 210 associated with cache line data 212, according to various embodiments. In general, the metadata includes ECC symbols and the MAC 122. The metadata can be stored as side-band metadata 204 or in-band metadata 210.”).
Therefore It would have been obvious to someone of ordinary skill in the art
before the effective filing date of the claimed invention to have combined Roberts in view of Drehmel, and MEDWED teaching of claim 4 with Erickson teaching because of, “The IME circuit can generate a MAC as described herein that can be used to detect and track errors caused by attacks.”, (see Erickson par.0019).
Claims 7 and 20 are rejected under 35 U.S.C. 103 as being unpatentable over Roberts in view of Drehmel as applied to claim 1, in further view of Song et al. (US-20230350603-A1 hereafter Song), in further view of Kim et al. (US-20210090684-A1 hereafter Kim).
Regarding claim 7 Roberts in view of Drehmel disclose the memory encryption circuit of claim 1, Roberts in view of Drehmel do not explicitly teach wherein the control circuitry is to: in the power-off process, send a first signal to a host system coupled to the memory encryption circuit, the first signal indicating a first status of the power-off process; and in the power-on process, send a second signal to the host system, the second signal indicating a second status of the power-on process.
In this instance examiner notes the teaching of prior art reference Song.
With regards to applicant’s claim limitation of, wherein the control circuitry is to:
in the power-off process, send a first signal to a host system coupled to the memory encryption circuit, the first signal indicating a first status of the power-off process (see Song par.0015: “The notification signal 105 can be a management command, or part of a management command, such as a GPF signal or a PWRDIS global persistent flush (GPF) or power disappear (PWRDIS) signal, received through a command interface between the host 112 and the management processor 106.”); and
Therefore It would have been obvious to someone of ordinary skill in the art
before the effective filing date of the claimed invention to have combined Roberts in view Drehmel teaching of claim 1 with Song teaching because of Song teaching of, “The NVM module 102 has persistent memory backup capabilities where the management processor 106 can access the encrypted data 103 and transfer the encrypted data 103 from the DRAM 114 to persistent memory 118 in the event of a power-down event or a power-loss event… the management processor 106 transfers the encrypted data to the persistent memory 118 using an NVM controller 166 (e.g., NAND controller). Because the attacker cannot interpret encrypted data correctly, the management processor 106 can access the encrypted DRAM contents and transfer the encrypted DRAM contents to the persistent memory 118 without exposing the data to probing on the lines between the memory expansion device 108 and the persistent memory 118.”, (see Song par.0015).
Song do not explicitly teach in the power-on process, send a second signal to the host system, the second signal indicating a second status of the power-on process.
In this instance examiner notes the teaching of prior art reference Kim.
With regards to applicant’s claim limitation of, in the power-on process, send a second signal to the host system, the second signal indicating a second status of the power-on process (see KIM par.0033: “the module controller 320 may transmit the request-resume signal REQ_RESUME to the host 200. The host 200 may perform a subsequent operation of the memory system 300 in response to the request-resume signal REQ_RESUME.”).
Therefore It would have been obvious to someone of ordinary skill in the art
before the effective filing date of the claimed invention to have combined Roberts in view Drehmel, and Song teaching described above with Kim teaching because of Kim teaching of, “The host 200, receiving the request-stop signal REQ_STOP, may terminate all operations of the memory system 100 until a request-resume signal REQ_RESUME is inputted into the host 200.”, (see Kim par.0021). the reason to combine would have been to notify the host when is memory controller ready to receive request.
Regarding claim 20 is method claim that recites similar limitations as the
method claim 7 and is rejected based on the same rational as claim 7.
Claim 8 is rejected under 35 U.S.C. 103 as being unpatentable over WANG et al. (US-20200264980-A1 hereafter WANG), in view of Roberts et al. (US-20230058668-A1 hereafter Roberts).
Regarding claim 8 An in-line memory encryption (IME) circuit comprising:
a first cache (see WANG par.0019: “cache storage having a plurality of entries to cache data items associated with memory addresses”); and
control circuitry (see WANG par.0068 : “Cache control circuitry 105 is used to control access to the cache RAMs 100, and may be considered to comprise allocation circuitry 120 for allocating data received in association with a write request, so that that data is stored within one of the cache lines. For a read request, lookup circuitry (not separately shown within the cache control circuitry 105) can be used to perform a lookup operation in the cache RAMs”), wherein the control circuitry is to:
store first plaintext data in a first cache entry of the first cache (see WANG par.0019: “cache storage having a plurality of entries to cache data items associated with memory addresses in a non-volatile memory. The data items may comprise persistent data items and non-persistent data items. The entries can take a variety of forms, but in one embodiment each entry comprises a cache line of the cache storage, in which one or more data items may be stored.”);
set a first valid flag in the first cache entry, wherein the first valid flag is stored in an always-on cell of the first cache (see WANG par.0038: “each entry within the cache storage has a persistence indication (valid flag) associated therewith that is set to identify that that entry stores persistent data (always-on cell).”);
receive a first indication of a first power event (see WANG par.0027-0028: “responsive to a trigger event to perform the determination of the subset of the plurality of entries to be used to store persistent data items. The trigger event can take a variety of forms, for example it can be one or more of: a boot procedure performed on the apparatus;”); and
WANG appear to be silence, however in this instance examiner notes the teaching of prior art reference.
With regards of applicant’s claim limitation element of, cryptographic circuitry (see Roberts par.0053: “cryptographic processing circuitry”);
in response to receiving the first indication (see Roberts par.0086: “monitoring the cache security timer for an expiration condition (first indication). Upon expiration of the cache security timer, the cryptographic controller 404 can scan all or a designated portion of the cache memory and identify any cache lines that are unencrypted.”), encrypt, using the cryptographic circuitry, the first plaintext data to obtain first ciphertext data (see Roberts par.0071: “the cryptographic memory system 400 can include the second cryptographic engine 416 to help facilitate or optimize some transactions between the cache memory 410 and main memory, such as via the memory controller 414. For example, the second cryptographic engine 416 can include an encryption circuit configured to encrypt any unencrypted data that is evicted from the cache memory 410.”); and
store the first ciphertext data in a memory coupled to the IME circuit (see Roberts par.0084: “the cache data write example 600 can include, at block 610, writing the encrypted data to main memory using the memory controller 414. The encrypted data can be written to main memory together with its corresponding key identifier for later user.”).
Therefore It would have been obvious to someone of ordinary skill in the art
before the effective filing date of the claimed invention to have combined WANG teaching “ the content of each cache entry will have an associated memory address and analysis of at least a portion of that memory address can be used to determine whether that entry is considered to be within the persistent region or the non-persistent region.”, (see WANG par.0035) with Roberts teaching because of Roberts teaching of, “compute-near-memory systems, can use data or memory encryption to help protect information from unwanted use or observation. Encryption can help avoid data observation by other systems or actors who impermissibly gain access to a physical (e.g., non-volatile) memory device”, (see Roberts par.002).
Claim 9 is rejected under 35 U.S.C. 103 as being unpatentable over WANG in view of Roberts as applied to claim 8, in further view of Drehmel et al. (US-20060015753-A1 hereafter Drehmel).
Regarding claim 9 WANG in view of Roberts disclose the IME circuit of claim 8, WANG in view of Roberts do not explicitly teach however Drehmel teaches wherein the control circuitry is further to:
receive a second indication of a second power event (see Drehmel par.0041: “the system may not allow further data to be read from external memory until a reset event, such as a power-on-reset, occurs” Examiner interpret that that the retrieval of the secure data happens during power-on process.); and
in response to receiving the second indication, load the first ciphertext data from the memory (see Drehmel par.0038-0039: “FIG. 4 is a flow diagram of exemplary operations 400, that illustrate how the ICVs stored in secure RAM 160 may be utilized during retrieval of secure data. The operations begin, at step 402, by fetching a block of data from external memory");
decrypt, using the cryptographic circuitry, the first ciphertext data to obtain the first plaintext data (see Drehmel par.0039: the secure ciphertext data may be routed to a decryption engine 154 of the security component 150 for decryption. The decryption engine 154 decrypts the secure data”); and
store the first plaintext data in the first cache (see Drehmel par.0039: “The decryption engine 154 decrypts the secure data and returns the secure data decrypted (as plaintext). If integrity is not enabled, as determined at step 407, the (plaintext) secure data is forwarded to cache, as no validation is required.”).
Therefore It would have been obvious to someone of ordinary skill in the art
before the effective filing date of the claimed invention to have combined WANG in view of Roberts teaching of claim 8 with Drehmel teaching because Drehmel teaching of, “the CPU 110 may include a security component 150 used to encrypt secure data prior to transmission over the FSB 128 by the FSB interface 120. Upon later retrieval of the encrypted data, the security component 150 may also be used to decrypt the encrypted secure data prior to passing it into the L2 cache 116 for use by one or more of the processor cores 112.”, (see Drehmel par.0029).
Claim 10 is rejected under 35 U.S.C. 103 as being unpatentable over WANG in view of Roberts as applied to claim 8, in further view of Kumar et al. (US-20190042458-A1 hereafter Kumar).
Regarding claim 10 WANG in view of Roberts disclose the IME circuit of claim 8, and WANG further discloses
in response to receiving the first indication (see WANG par.0027-0028: “responsive to a trigger event to perform the determination of the subset of the plurality of entries to be used to store persistent data items. The trigger event can take a variety of forms, for example it can be one or more of: a boot procedure performed on the apparatus;”), store the first metadata in the memory (see WANG par.0019: “cache storage having a plurality of entries to cache data items associated with memory addresses in a non-volatile memory. The data items may comprise persistent data items and non-persistent data items.”, Par.0021: “in response to an event causing the backup energy source to be used, the write back control circuitry is arranged to initiate write back to the non-volatile memory of the persistent data items cached in the subset of the plurality of entries”).
WANG in view of Roberts do not explicitly discloses further comprising a second cache, wherein the control circuitry is further to: store first metadata in a first cache entry of the second cache; set a second valid flag in the first cache entry of the second cache, wherein the first metadata and the second valid flag are stored in always-on cells of the second cache.
In this instance examiner notes the teaching of prior art reference Kumar.
With regards of applicant’s claim limitation elements of, further comprising a second cache (see Kumar par.0034: “The persistent memory module 128 also includes a volatile memory 202 (second cache) which acts as a cache for the persistent memory 134 which may be referred to as cache memory. Data is transferred between persistent memory 134 and volatile memory 202 (which may be referred to as an intra-module transfer) in blocks of fixed size, called cache lines or cache blocks. Each cache line 206 in the volatile memory 202 may be dynamically assigned to be a read (prefetch) cache line or a write cache line.”), wherein the control circuitry is further to:
store first metadata in a first cache entry of the second cache (see Kumar par.0041-0042: “The requested 64-bytes of data are returned to CPU module 108 and are also stored in one of the four assigned read cache entries 300 in volatile memory 202… The read cache entry 300 also includes metadata,”);
set a second valid flag in the first cache entry of the second cache, wherein the first metadata and the second valid flag are stored in always-on cells of the second cache (see Kumar par.0042: “The read cache entry 300 also includes metadata, the metadata includes a tag field 302, and a flag field 306. A tag stored in the tag field 302 includes a portion of the persistent memory address in persistent memory 134 that is associated with the cache line in volatile memory 202. The flag field 306 includes a valid bit (‘V’) 308, a dirty bit (‘D’) 310, and a Read/Write flag 312.”).
Therefore It would have been obvious to someone of ordinary skill in the art
before the effective filing date of the claimed invention to have combined WANG in view of Roberts teaching of claim 8 with Kumar teaching because Kumar teaching of, “A tag stored in the tag field 302 includes a portion of the persistent memory address in persistent memory 134 that is associated with the cache line in volatile memory 202.”, (see Kumar par.0029). The reason to combine would have been to have persistence reference in case of a power loss.
Claim 11 is rejected under 35 U.S.C. 103 as being unpatentable over WANG in view of Roberts, and Kumar as applied to claim 10, in further view of Drehmel et al. (US-20060015753-A1 hereafter Drehmel).
Regarding claim 11 WANG in view of Roberts, and Kumar disclose the IME circuit of claim 10, Kumar further teaches and
store the first metadata in the second cache (see Kumar par.0041-0042: “The requested 64-bytes of data are returned to CPU module 108 and are also stored in one of the four assigned read cache entries 300 in volatile memory 202… The read cache entry 300 also includes metadata,”).
WANG in view of Roberts, and Kumar do not explicitly teach wherein the control circuitry is further to:
receive a second indication of a second power event; and in response to receiving the second indication, load the first ciphertext data and the first metadata from the memory; decrypt, using the cryptographic circuitry, the first ciphertext data to obtain the first plaintext data; store the first plaintext data in the first cache.
In this instance examiner notes the teaching of prior art reference Drehmel.
With regards to applicant’s claim limitation of, wherein the control circuitry is further to:
receive a second indication of a second power event (see Drehmel par.0041: “the system may not allow further data to be read from external memory until a reset event, such as a power-on-reset, occurs” Examiner interpret that that the retrieval of the secure data happens during power-on process.”); and
in response to receiving the second indication, load the first ciphertext data and the first metadata from the memory (see Drehmel par.0038-0039: “fetching a block of data from external memory… the data is ciphertext and, therefore, is decrypted, at step 406. For example, referring back to FIG. 2, the secure ciphertext data may be routed to a decryption engine 154 of the security component 150 for decryption.).”);
decrypt, using the cryptographic circuitry, the first ciphertext data to obtain the first plaintext data (see Drehmel par.0038-0039: “FIG. 4 is a flow diagram of exemplary operations 400, that illustrate how the ICVs stored in secure RAM 160 may be utilized during retrieval of secure data. The operations begin, at step 402, by fetching a block of data from external memory");
store the first plaintext data in the first cache (see Drehmel par.0038: “fetching a block of data from external memory. If the data is not secure, as determined at step 404, the data is forwarded on to the cache,”);
Therefore It would have been obvious to someone of ordinary skill in the art
before the effective filing date of the claimed invention to have combined WANG in view of Roberts, and Kumar teaching of claim 10 with Drehmel teaching because Drehmel teaching of, “the CPU 110 may include a security component 150 used to encrypt secure data prior to transmission over the FSB 128 by the FSB interface 120. Upon later retrieval of the encrypted data, the security component 150 may also be used to decrypt the encrypted secure data prior to passing it into the L2 cache 116 for use by one or more of the processor cores 112.”, (see Drehmel par.0029). The reason to combined would have been to protect data received from external main memory which is less secure and prone to tampering.
Claim 12 is rejected under 35 U.S.C. 103 as being unpatentable over WANG in view of Roberts as applied to claim 8, in further view of ZITLAW et al. (US-20240184875-A1 hereafter ZITLAW).
Regarding claim 12 WANG in view of Roberts disclose the IME circuit of claim 8, WANG further teaches wherein the control circuitry is further to
store a first tag associated with the first plaintext data in the first cache entry, wherein the first tag is stored in always-on cells of the first cache (see WANG par.0051: “the cache 20 that are allowed to be used to store persistent data. As will be discussed in more detail later, as a result of the determination performed by the cache usage determination circuitry, usage control information is provided to the cache 20 to identify the subset of entries that can be used to store persistent data items. This usage control information may in one embodiment directly identify the entries that are to be used to store such persistent data (always-on cell), or alternatively can indicate a maximum number of entries that can be used to store such persistent data, with additional information then being retained by the cache to identify the actual entries that are used to store persistent data.”, par.0057-0058: “the page tables 45 having a number of entries 50 for storing address translation information for associated pages in memory, for example to enable virtual addresses specified by the processing circuitry to be translated into physical addresses within the memory system. Such page table entries can also store associated attributes of the pages in memory, and in one embodiment each entry includes a persistence bit identifying whether the data stored within that page in memory is persistent data or non-persistent data…persistence cache 20 is managed by the operating system, the operating system would have full knowledge from the persistence bit 52 (a first tag) whether the data to be allocated is persistent data or not.”);
receive a second indication of a second power event (see WANG par.0027-0028: “responsive to a trigger event to perform the determination of the subset of the plurality of entries to be used to store persistent data items. The trigger event can take a variety of forms, for example it can be one or more of: an indication received from the backup energy source providing an updated indication of capacity.”); and
store the first plaintext data in the first cache entry with the first tag stored in the always-on cells of the first cache (see WANG par.0051: “the cache 20 that are allowed to be used to store persistent data. As will be discussed in more detail later, as a result of the determination performed by the cache usage determination circuitry, usage control information is provided to the cache 20 to identify the subset of entries that can be used to store persistent data items. This usage control information may in one embodiment directly identify the entries that are to be used to store such persistent data (always-on cell), or alternatively can indicate a maximum number of entries that can be used to store such persistent data, with additional information then being retained by the cache to identify the actual entries that are used to store persistent data.”, par.0057-0058: “the page tables 45 having a number of entries 50 for storing address translation information for associated pages in memory, for example to enable virtual addresses specified by the processing circuitry to be translated into physical addresses within the memory system. Such page table entries can also store associated attributes of the pages in memory, and in one embodiment each entry includes a persistence bit identifying whether the data stored within that page in memory is persistent data or non-persistent data…persistence cache 20 is managed by the operating system, the operating system would have full knowledge from the persistence bit 52 (a first tag) whether the data to be allocated is persistent data or not.”).
WANG in view of Roberts do not explicitly teach however ZITLAW teaches
in response to receiving the second indication, load, using the first tag, the first ciphertext data from the memory (see ZITLAW par.0071 “various tags and authentication values shown in FIGS. 2A to 2G can be per transaction values, not single-event time authentication values, such as those generated on power-on or reset.”, par.0077: “a memory device can return encrypted data with a separate tag in a transaction (e.g., read operation). FIGS. 4A to 4D are diagrams showing transaction data orders according to embodiments.”); and
decrypt, using the cryptographic circuitry, the first ciphertext data to obtain the first plaintext data (see ZITLAW par.0063:“decryption circuits 220-0 can decrypt an encrypted tag 250 in addition to decrypted data 236.”).
Therefore It would have been obvious to someone of ordinary skill in the art
before the effective filing date of the claimed invention to have combined WANG in view of Roberts teaching of claim 8 with ZITLAW teaching because ZITLAW teaching of, “a transaction can be authenticated with encrypted data and an encrypted tag, which can further authenticate the data and/or the device.”, (see ZITLAW l par.0064). The reason to combined would have been provide an authentication method using the tag.
Claim 13 is rejected under 35 U.S.C. 103 as being unpatentable over WANG in view of Roberts, and ZITLAW as applied to claim 12, in further view of Wilson et al. (US-20150046658-A1 hereafter Wilson), in further view of Dutta et al. (US-20250209001-A1 hereafter Dutta), in further view of Flynn et al. (US-20120151118-A1 hereafter Flynn).
Regarding claim 13 WANG in view of Roberts, and ZITLAW disclose the IME circuit of claim 12, WANG in view of Roberts, and ZITLAW do not explicitly teach however Wilson teaches further comprising a second cache (see Wilson par.0028: “a cache data array 202”), wherein the control circuitry is further to:
store first metadata and the first tag in a first cache entry of the second cache (see Wilson par.0028: “Each tag of cache tag array 201 is associated with a respective cache line of cache data array 202, as shown by connections 207, 210, 213, 216, 219, 222, 225, and 228… Connection 228 connects tag 227 to cache line 229. Line select lines 204 from metadata connect individually to cache lines 208, 211, 214, 217, 220, 223, 226, and 229”);
WANG in view of Roberts, ZITLAW and Wilson do not explicitly teach set a second valid flag in the first cache entry of the second cache, wherein the first metadata, the first tag, and the second valid flag are stored in always-on cells of the second cache; and
in response to receiving the first indication, store the first metadata and the first tag in the memory.
Therefore It would have been obvious to someone of ordinary skill in the art
before the effective filing date of the claimed invention to have combined WANG in view of Roberts, and ZITLAW teaching of claim 12 with Wilson teaching because Wilson teaching of, “Content Addressable Memory (CAM) based cache (e.g., a cache that stores a tag at each line of a CAM array and, in response to a tag hit, returns information from a data array line that corresponds to the hit CAM line) the metadata can include information identifying the corresponding line of a cache memory that would otherwise have been identified by a tag lookup operation.”, (see Wilson par.0064).
In this instance examiner notes the teaching of prior art reference Dutta.
With regards of applicant’s claim limitation elements of, set a second valid flag in the first cache entry of the second cache (see Dutta par.0056: “cache or data cache that stores memory blocks in cache lines. Herein, unless indicated otherwise, the address or an instruction or data in memory is referred to as a pointer, and the first address stored in a cache line is referred to as the pointer of the cache line or corresponding memory block.”), wherein the first metadata, the first tag, and the second valid flag are stored in always-on cells of the second cache (see Dutta par.0057: “cache 400 includes two main building blocks: a data array 410 and a tag array 420. The data array 410 stores the cache lines, while the tag array 420 is used in order to match pointers into data array entries.”, par.0059: “pointer” may be used to refer to the address of a memory block in memory. As illustrated in FIG. 5, the pointer 500, in order to map a memory block into a cache, is partitioned into the following fields: P-tag, P-index, and P-offset. Here, the leading “P” is the shorthand for “pointer”); and
Therefore It would have been obvious to someone of ordinary skill in the art
before the effective filing date of the claimed invention to have combined WANG in view of Roberts, ZITLAW, and Wilson teaching described above with Dutta teaching because Dutta teaching of, “ If the P-tag bits of the j-th entry in the set Si match, then the correct data is in the j-th cache line of the corresponding data array in the set Si (this is called a “cache hit”). If no P-tags in the set Si match in the tag array, then the requested cache line does not reside in the cache”, (see Dutta par.0064).
WANG in view of Roberts, ZITLAW, Wilson, and Dutta do not explicitly teach in response to receiving the first indication, store the first metadata and the first tag in the memory.
In this instance examiner notes the teaching of prior art reference Flynn.
With regards of applicant’s claim limitation elements of, in response to receiving the first indication, store the first metadata and the first tag in the memory (see Flynn par.0319-0320: “A failure condition causes the contents of the buffers 1013 to be committed to the solid-state storage 1502 cache. When the failure condition is cleared, the cached data in the solid-state storage 1502… auto-commit buffers 1013 of the ACM 1011 may be leveraged as a memory write-back cache by an operating system, virtual memory system, and/or one or more CPUs of the host 1014. Data cached in the auto-commit buffers 1013 as part of a CPU write-back cache may be armed to commit as a group. When committed, the auto-commit buffers 1013 may commit both data and the associated cache tags.”).
Therefore It would have been obvious to someone of ordinary skill in the art
before the effective filing date of the claimed invention to have combined WANG in view of Roberts, ZITLAW, Wilson, and Dutta teaching described above with Flynn teaching because Flynn teaching of, “In the event of a power disruption, it may be useful to move data through the write data pipeline 106 even if a buffer, packet, or page at one or more stages is not filled, to flush the data to the nonvolatile memory 110, or the like.”, (see Flynn par.0190).
Claim 16 is rejected under 35 U.S.C. 103 as being unpatentable over Roberts in view of Drehmel as applied to claim 14, in further view of WANG et al. (US-20200264980-A1 hereafter WANG), in further view of ZITLAW et al. (US-20240184875-A1 hereafter ZITLAW).
Regarding claim 16 Roberts in view of Drehmel disclose the method of claim 14, Roberts in view of Drehmel do not explicitly teach however WANG teaches further comprising:
in the power-off process (see WANG par.0027-0028: “responsive to a trigger event to perform the determination of the subset of the plurality of entries to be used to store persistent data items. The trigger event can take a variety of forms, for example it can be one or more of: a boot procedure performed on the apparatus;”), storing tag data, associated with the plaintext data of one or more cache entries of the first plurality of cache entries having the first persistent valid flag, in the memory system, wherein the tag data is stored in persistent cells of the first cache (see WANG par.0051: “the cache 20 that are allowed to be used to store persistent data. As will be discussed in more detail later, as a result of the determination performed by the cache usage determination circuitry, usage control information is provided to the cache 20 to identify the subset of entries that can be used to store persistent data items. This usage control information may in one embodiment directly identify the entries that are to be used to store such persistent data (always-on cell), or alternatively can indicate a maximum number of entries that can be used to store such persistent data, with additional information then being retained by the cache to identify the actual entries that are used to store persistent data.”, par.0057-0058: “the page tables 45 having a number of entries 50 for storing address translation information for associated pages in memory, for example to enable virtual addresses specified by the processing circuitry to be translated into physical addresses within the memory system. Such page table entries can also store associated attributes of the pages in memory, and in one embodiment each entry includes a persistence bit identifying whether the data stored within that page in memory is persistent data or non-persistent data…persistence cache 20 is managed by the operating system, the operating system would have full knowledge from the persistence bit 52 (a first tag) whether the data to be allocated is persistent data or not.”), wherein, in the power-on process (see WANG par.0027-0028: “responsive to a trigger event to perform the determination of the subset of the plurality of entries to be used to store persistent data items. The trigger event can take a variety of forms, for example it can be one or more of: an indication received from the backup energy source providing an updated indication of capacity.”): and
storing the plaintext data in the one or more cache entries with the tag data (see WANG par.0051: “the cache 20 that are allowed to be used to store persistent data. As will be discussed in more detail later, as a result of the determination performed by the cache usage determination circuitry, usage control information is provided to the cache 20 to identify the subset of entries that can be used to store persistent data items. This usage control information may in one embodiment directly identify the entries that are to be used to store such persistent data (always-on cell), or alternatively can indicate a maximum number of entries that can be used to store such persistent data, with additional information then being retained by the cache to identify the actual entries that are used to store persistent data.”, par.0057-0058: “the page tables 45 having a number of entries 50 for storing address translation information for associated pages in memory, for example to enable virtual addresses specified by the processing circuitry to be translated into physical addresses within the memory system. Such page table entries can also store associated attributes of the pages in memory, and in one embodiment each entry includes a persistence bit identifying whether the data stored within that page in memory is persistent data or non-persistent data…persistence cache 20 is managed by the operating system, the operating system would have full knowledge from the persistence bit 52 (a first tag) whether the data to be allocated is persistent data or not.”).
Therefore It would have been obvious to someone of ordinary skill in the art
before the effective filing date of the claimed invention to have combined Roberts in view of Drehmel teaching of claim 14 with WANG teaching because WANG teaching of, “ the content of each cache entry will have an associated memory address and analysis of at least a portion of that memory address can be used to determine whether that entry is considered to be within the persistent region or the non-persistent region.”, (see WANG par.0035).
Roberts in view of Drehmel, and WANG do not explicitly however ZITLAW teaches loading the ciphertext data from the memory system comprises loading the ciphertext data using the tag data stored in the persistent cells of the first cache (see ZITLAW par.0071 “various tags and authentication values shown in FIGS. 2A to 2G can be per transaction values, not single-event time authentication values, such as those generated on power-on or reset.”, par.0077: “a memory device can return encrypted data with a separate tag in a transaction (e.g., read operation). FIGS. 4A to 4D are diagrams showing transaction data orders according to embodiments.”);
Therefore It would have been obvious to someone of ordinary skill in the art
before the effective filing date of the claimed invention to have combined Roberts in view of Drehmel, and WANG teaching described above with ZITLAW teaching because ZITLAW teaching of, “a transaction can be authenticated with encrypted data and an encrypted tag, which can further authenticate the data and/or the device.”, (see ZITLAW l par.0064). The reason to combined would have been provide an authentication method using the tag.
Claim 17 is rejected under 35 U.S.C. 103 as being unpatentable over Roberts in view of Drehmel, as applied to claim 14, in further view of MEDWED et al. (US 20200380140 A1 hereafter MEDWED), in further view of WANG et al. (US-20200264980-A1 hereafter WANG).
Regarding claim 17 Roberts in view of Drehmel disclose the method of claim 14, Roberts in view of Drehmel do not explicitly teach However MEDWED teaches further comprising:
storing, in a second cache, a second persistent valid flag and metadata associated with the respective plaintext data of the corresponding cache entry of the first cache, [wherein the second persistent valid flag and metadata are stored in persistent cells of the first cache] (see MEDWED par.0057-0060: “a second cache (L2) 520… cache L2 stores the data in encrypted form and cache L1 stores the data both in encrypted and decrypted form. Cache L1 (or a different storage area) may also store memory safety tags for the data stored in the L2 cache and metadata… each pointer may include an address and a memory safety tag. The address may correspond to a cache line in L2, which stores data which is encrypted using the key and a unique memory safety tag. …The metadata may include a first control bit T and a second control bit A. The first control bit T may keep track of the tag that was used to decrypt the data stored in the L1 cache. The second control bit A may provide an indication of whether the data has been accessed by the first processor (e.g., CPU) 10… the L1 cache to have two slots for each cache line 610 in the second cache L2. The first slot 620 stores a copy of the encrypted data stored in a corresponding cache line in L2. The second slot 630 stores the decrypted version of the cache line data, e.g., the cache line data from L2 that has been decrypted by the cipher engine 30. The first cache L1 also stores the metadata T and A for each cache line.”).
Therefore It would have been obvious to someone of ordinary skill in the art
before the effective filing date of the claimed invention to have combined Roberts in view Drehmel teaching of claim 14 with MEDWED teaching because of MEDWED teaching of, “ the content of each cache entry will have an associated memory address and analysis of at least a portion of that memory address can be used to determine whether that entry is considered to be within the persistent region or the non-persistent region.”, (see WANG par.0035).
Roberts in view of Drehmel, and MEDWED do not explicitly teach However WANG teaches wherein the second persistent valid flag and metadata are stored in persistent cells of the first cache (see WANG par.0051: “the cache 20 that are allowed to be used to store persistent data. As will be discussed in more detail later, as a result of the determination performed by the cache usage determination circuitry, usage control information is provided to the cache 20 to identify the subset of entries that can be used to store persistent data items. This usage control information may in one embodiment directly identify the entries that are to be used to store such persistent data (always-on cell), or alternatively can indicate a maximum number of entries that can be used to store such persistent data, with additional information then being retained by the cache to identify the actual entries that are used to store persistent data.”, par.0057-0058: “the page tables 45 having a number of entries 50 for storing address translation information for associated pages in memory, for example to enable virtual addresses specified by the processing circuitry to be translated into physical addresses within the memory system. Such page table entries can also store associated attributes of the pages in memory, and in one embodiment each entry includes a persistence bit identifying whether the data stored within that page in memory is persistent data or non-persistent data…persistence cache 20 is managed by the operating system, the operating system would have full knowledge from the persistence bit 52 (tag) whether the data to be allocated is persistent data or not.”).
Therefore It would have been obvious to someone of ordinary skill in the art
before the effective filing date of the claimed invention to have combined Roberts in view Drehmel, and MEDWED teaching described above with WANG teaching because of WANG teaching of, “The metadata T and A may be used to resolve problems which arise, for example, when an attempt is made to access and decrypt data from the L2 cache using an incorrect or unintended memory safety tag, e.g., prefetching could request a cache line which does not belong to the pointer that was used to encrypt the data at that cache line.”, (see MEDWED par.0059).
Claim 18 is rejected under 35 U.S.C. 103 as being unpatentable over Roberts in view of Drehmel, MEDWED, and WANG as applied to claim 17, in further view of Erickson et al. (US-20240143197-A1 hereafter Erickson).
Regarding 18 Roberts in view of Drehmel, MEDWED, and WANG disclose the method of claim 17, Roberts in view of Drehmel, MEDWED, and WANG appear to be silence however Erickson teaches wherein the metadata comprises a message authentication code (MAC) of the respective plaintext data of the corresponding cache entry of the first plurality of cache entries (see Erickson Fig 3. And par.0037: “a cache line 202 in which a MAC 122 is stored and transferred in side-band metadata 204 associated with cache line data 206 and a cache line 208 in which a MAC 122 is stored and transferred as in-band metadata 210 associated with cache line data 212, according to various embodiments. In general, the metadata includes ECC symbols and the MAC 122. The metadata can be stored as side-band metadata 204 or in-band metadata 210.”).
Therefore It would have been obvious to someone of ordinary skill in the art
before the effective filing date of the claimed invention to have combined Roberts in view of Drehmel, MEDWED, and WANG teaching of claim 17 with Erickson teaching because of, “The IME circuit can generate a MAC as described herein that can be used to detect and track errors caused by attacks.”, (see Erickson par.0019).
Claim 19 is rejected under 35 U.S.C. 103 as being unpatentable over Roberts in view of Drehmel, as applied to claim 14, in further view of WANG et al. (US-20200264980-A1 hereafter WANG) in further view of Wilson et al. (US-20150046658-A1 hereafter Wilson), in further view of ZITLAW et al. (US-20240184875-A1 hereafter ZITLAW)..
Regarding claim 19 Roberts in view of Drehmel disclose the method of claim 14, Roberts in view of Drehmel do not explicitly teach however WANG teaches further comprising:
storing, in the first cache, tag data associated with the plain text data of the first plurality of cache entries, wherein the tag data is stored in persistent cells of the first cache (see WANG par.0051: “the cache 20 that are allowed to be used to store persistent data. As will be discussed in more detail later, as a result of the determination performed by the cache usage determination circuitry, usage control information is provided to the cache 20 to identify the subset of entries that can be used to store persistent data items. This usage control information may in one embodiment directly identify the entries that are to be used to store such persistent data (always-on cell), or alternatively can indicate a maximum number of entries that can be used to store such persistent data, with additional information then being retained by the cache to identify the actual entries that are used to store persistent data.”, par.0057-0058: “the page tables 45 having a number of entries 50 for storing address translation information for associated pages in memory, for example to enable virtual addresses specified by the processing circuitry to be translated into physical addresses within the memory system. Such page table entries can also store associated attributes of the pages in memory, and in one embodiment each entry includes a persistence bit identifying whether the data stored within that page in memory is persistent data or non-persistent data…persistence cache 20 is managed by the operating system, the operating system would have full knowledge from the persistence bit 52 (a first tag) whether the data to be allocated is persistent data or not.”); and
in the power-off process (see WANG par.0027-0028: “responsive to a trigger event to perform the determination of the subset of the plurality of entries to be used to store persistent data items. The trigger event can take a variety of forms, for example it can be one or more of: a boot procedure performed on the apparatus;”), storing tag data, associated with the plaintext data of one or more cache entries of the first plurality of cache entries having the first persistent valid flag, in the memory system (see WANG par.0051: “the cache 20 that are allowed to be used to store persistent data. As will be discussed in more detail later, as a result of the determination performed by the cache usage determination circuitry, usage control information is provided to the cache 20 to identify the subset of entries that can be used to store persistent data items. This usage control information may in one embodiment directly identify the entries that are to be used to store such persistent data (always-on cell), or alternatively can indicate a maximum number of entries that can be used to store such persistent data, with additional information then being retained by the cache to identify the actual entries that are used to store persistent data.”, par.0057-0058: “the page tables 45 having a number of entries 50 for storing address translation information for associated pages in memory, for example to enable virtual addresses specified by the processing circuitry to be translated into physical addresses within the memory system. Such page table entries can also store associated attributes of the pages in memory, and in one embodiment each entry includes a persistence bit identifying whether the data stored within that page in memory is persistent data or non-persistent data…persistence cache 20 is managed by the operating system, the operating system would have full knowledge from the persistence bit 52 (a first tag) whether the data to be allocated is persistent data or not.”); and
in the power-on process (see WANG par.0027-0028: “responsive to a trigger event to perform the determination of the subset of the plurality of entries to be used to store persistent data items. The trigger event can take a variety of forms, for example it can be one or more of: an indication received from the backup energy source providing an updated indication of capacity.”): and
storing the plaintext data in the one or more cache entries with the tag data (see WANG par.0051: “the cache 20 that are allowed to be used to store persistent data. As will be discussed in more detail later, as a result of the determination performed by the cache usage determination circuitry, usage control information is provided to the cache 20 to identify the subset of entries that can be used to store persistent data items. This usage control information may in one embodiment directly identify the entries that are to be used to store such persistent data (always-on cell), or alternatively can indicate a maximum number of entries that can be used to store such persistent data, with additional information then being retained by the cache to identify the actual entries that are used to store persistent data.”, par.0057-0058: “the page tables 45 having a number of entries 50 for storing address translation information for associated pages in memory, for example to enable virtual addresses specified by the processing circuitry to be translated into physical addresses within the memory system. Such page table entries can also store associated attributes of the pages in memory, and in one embodiment each entry includes a persistence bit identifying whether the data stored within that page in memory is persistent data or non-persistent data…persistence cache 20 is managed by the operating system, the operating system would have full knowledge from the persistence bit 52 (a first tag) whether the data to be allocated is persistent data or not.”).
Therefore It would have been obvious to someone of ordinary skill in the art
before the effective filing date of the claimed invention to have combined Roberts in view of Drehmel, teaching of claim 14 with WANG teaching because WANG teaching of, “ the content of each cache entry will have an associated memory address and analysis of at least a portion of that memory address can be used to determine whether that entry is considered to be within the persistent region or the non-persistent region.”, (see WANG par.0035).
Roberts in view of Drehmel in view of WANG do not explicitly teach
storing, in a second cache, the tag data, wherein the tag data is stored in persistent cells of the second cache, and wherein:
loading the ciphertext data from the memory system comprises loading the
ciphertext data using the tag data stored in the persistent cells of the first cache.
However Wilson teaches storing, in a second cache, the tag data, wherein the tag data is stored in persistent cells of the second cache (see Wilson par.0028: “Each tag of cache tag array 201 is associated with a respective cache line of cache data array 202, as shown by connections 207, 210, 213, 216, 219, 222, 225, and 228… Connection 228 connects tag 227 to cache line 229. Line select lines 204 from metadata connect individually to cache lines 208, 211, 214, 217, 220, 223, 226, and 229”), and wherein:
Therefore It would have been obvious to someone of ordinary skill in the art
before the effective filing date of the claimed invention to have combined Roberts in view of Drehmel, and WANG teaching described above with Wilson teaching because Wilson teaching of, “Content Addressable Memory (CAM) based cache (e.g., a cache that stores a tag at each line of a CAM array and, in response to a tag hit, returns information from a data array line that corresponds to the hit CAM line) the metadata can include information identifying the corresponding line of a cache memory that would otherwise have been identified by a tag lookup operation.”, (see Wilson par.0064).
Roberts in view of Drehmel in view of WANG, and Wilson do not explicitly teach however ZITLAW teaches loading the ciphertext data from the memory system comprises loading the ciphertext data using the tag data stored in the persistent cells of the first cache (see ZITLAW par.0071 “various tags and authentication values shown in FIGS. 2A to 2G can be per transaction values, not single-event time authentication values, such as those generated on power-on or reset.”, par.0077: “a memory device can return encrypted data with a separate tag in a transaction (e.g., read operation). FIGS. 4A to 4D are diagrams showing transaction data orders according to embodiments.”).
Therefore It would have been obvious to someone of ordinary skill in the art
before the effective filing date of the claimed invention to have combined Roberts in view of Drehmel, WANG, and Wilson teaching described above with ZITLAW teaching because ZITLAW teaching of, “a transaction can be authenticated with encrypted data and an encrypted tag, which can further authenticate the data and/or the device.”, (see ZITLAW l par.0064). The reason to combined would have been provide an authentication method using the tag.
Conclusion
The prior art made of record and not relied upon is considered pertinent to
applicant's disclosure:
Kumar et al. (US-20160179687-A1) memory system that helps transactions to persistent memory survive failures without leaving data inconsistent. The system uses a volatile cache as a staging area for writes before they are made durable in persistent memory. Each cache line used by a transaction carries a status such as free, uncommitted, or committed. When a failure event occurs, the cache controller checks that status and either writes the cache line’s contents out to persistent memory or discards them. The near-memory cache is configured with flush-on-fail behavior so it can be processed during a reset or failure.
Avanzi et al. (US 20240346155 A1) The system sits between a system cache and a memory system and encrypts data before it is stored off-chip, then decrypts it when it is brought back. The encryption depends on changing encryption metadata, such as counters. When that metadata changes, any data encrypted with the old value may need to be updated. If the affected data is not currently in the system cache, the apparatus pulls it from memory, updates the encryption, and writes it back. If the data is already in the system cache, the system may either write it back immediately under the new encryption or simply mark it modified for later write-back.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to DUILIO MUNGUIA whose telephone number is (571)270-5277. The examiner can normally be reached M-F 9:30AM - 5:00Pm.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Eleni A Shiferaw can be reached at (571) 272-3867. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/DUILIO MUNGUIA/Examiner, Art Unit 2497 /ELENI A SHIFERAW/Supervisory Patent Examiner, Art Unit 2497
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