DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Priority
Applicant’s claim for the benefit of a provisional application 63/640,072 filed on 04/29/2024 is acknowledged.
Claim Interpretation
Method claims 8, 10 recite the limitation “when the DRAM metadata indicates that the target data is not stored in the DRAM cache line”, claim 11 recites the limitation “when the DRAM metadata indicates that the target data is not in the DRAM cache line and is in a tiered memory cache line of the subset of tiered memory regions”, “when the DRAM metadata indicates that the target data is not in the DRAM cache line and not in a tiered memory cache line of the subset of tiered memory regions”, claim 12 recites the limitation “when loading a new tiered memory cache line into the DRAM”. Since these are contingent limitations, the BRI of the claim only requires the steps to be performed when the contingent condition is met. The Office suggests positively reciting the limitations.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claim(s) 6 rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 6 recites the limitation “and swap the contents of the DRAM cache line and the tiered memory cache line of the owning tiered memory region before the loading the tiered memory cache line containing the target data into the DRAM and the loading the DRAM cache line into the identified tiered memory region.”
A person of ordinary skill in the art would not have known the meets and bounds of “swap the contents of the DRAM cache line and the tiered memory cache line of the owning tiered memory region before the loading the tiered memory cache line containing the target data into the DRAM and the loading the DRAM cache line into the identified tiered memory region.”
Specifically, for the limitation “the loading the tiered memory cache line containing the target data into the DRAM and the loading the DRAM cache line into the identified tiered memory region”, does it mean the target data is in the identified tiered memory region prior to “the loading…and the loading”? Does the “the loading …and the loading” mean a swap of content of the tiered memory cache line containing the target data with the content of the DRAM cache line? For the limitation “swap the contents of the DRAM cache line and the tiered memory cache line of the owning tiered memory region before the loading …and the loading…”, does it mean a swap before another swap? OR a swap before a loading and another loading?
Correction/clarification is required to show these limitations are manifested in the
technology such that one of ordinary skill would have known the meets and bounds of the limitations.
Allowable Subject Matter
Claim 4-6, 11-12, 19-20 objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. Also, claim 6 would be allowable contingent on overcoming 112 (b) rejection.
REASONS FOR ALLOWANCE
For claim 4, the prior art does not teach the limitations when view in combination with limitations from the base claims from which claim 4 depends.
For claim 5, the prior art does not teach the limitations when view in combination with limitations from the base claims from which claim 5 depends. Additionally, claim 5 is allowable based on dependency from claim 4.
For claim 6, the prior art does not teach the limitations when view in combination with limitations from the base claims from which claim 6 depends.
For claim 11, the prior art does not teach the limitations when view in combination with limitations from the base claims from which claim 11 depends.
For claim 12, the prior art does not teach the limitations when view in combination with limitations from the base claims from which claim 12 depends. Additionally, claim 12 is allowable based on dependency from claim 11.
For claim 19, the prior art does not teach the limitations when view in combination with limitations from the base claims from which claim 19 depends.
For claim 20, the prior art does not teach the limitations when view in combination with limitations from the base claims from which claim 20 depends. Additionally, claim 20 is allowable based on dependency from claim 19.
Any comments considered necessary by applicant must be submitted no later than the payment of the issue fee and, to avoid processing delays, should preferably accompany the issue fee. Such submissions should be clearly labeled “Comments on Statement of Reasons for Allowance.”
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1-2, 8-9, 13-14, 16-17 is/are rejected under 35 U.S.C. 103 as being unpatentable over Butcher (US 20190227709), in view of Ware (US 20200250090).
Regarding Claim 1, Butcher teaches
A computer system comprising: a memory including: dynamic random access memory (DRAM) including a memory tiering portion having a fixed memory tiering block size; (Butcher [0003] A non-volatile dual in-line memory module (NVDIMM) may include a dynamic random access memory (DRAM) block, [0025] DRAM block 230 is organized into pages 232. For example, where DRAM block 230 represents a 32 GB DRAM memory, the DRAM block can be organized into four pages of 8 GB each, into eight pages of 4 GB each, into 16 pages of 2 GB each, or into another number of pages, as needed or desired.) (i.e. DRAM block is memory tiering portion having a fixed block size)
and multiple regions of tiered memory, each tiered memory region having the fixed memory tiering block size; (Butcher [0003] A non-volatile dual in-line memory module (NVDIMM) may include a plurality of non-volatile random access memory (NVRAM) blocks [0025] Similarly, NVRAM blocks 240, 250, 260, and 270 are each organized into respective pages 242, 252, 262, and 272, where the NVRAM blocks each include the same number of pages as DRAM block 230.)(i.e., NVRAM blocks are multiple regions of tiered memory each having the fixed block size)
and a processor operatively coupled to the memory and configured to: send a memory operation indicating a DRAM cache line stored in the DRAM; (Butcher [0022] Memory controller 212 represents a portion of the processor complex that is dedicated to the management of the data storage and retrieval from the memory devices of information handling system 200 [0023] NVDIMM 220 represents a memory device of information handling system 200. NVDIMM 220 includes a dynamic random access memory (DRAM) block 230 [0025] DRAM block 230 is organized into pages 232 [0026] pages 232 are n-way set associatively mapped to pages 242, 252, 262, and 272, when memory controller 212 makes a memory access to a byte address within a page that is copied into one of pages 232, the memory transaction is serviced by DRAM block 230 directly. [0028] when processor complex 210 issues a memory transaction, memory controller 212 first checks page table 214 to determine if the byte address of the memory transaction is associated with a page 242, 252, 262, or 272, that is currently copied into DRAM block 230.) (i.e., memory controller is part of processor complex operatively couplet to memory, DRAM page has a cache line stored in the DRAM)
receive DRAM metadata stored in the DRAM for the DRAM cache line; (Butcher [0027] memory controller 212 includes a page table 214 that maintains information as to the current state of DRAM block 230 [0028] memory controller 212 first checks page table 214 to determine if the byte address of the memory transaction is associated with a page 242, 252, 262, or 272, that is currently copied into DRAM block 230.) (i.e., page table 214 is DRAM metadata)
identify a tiered memory region of the multiple tiered memory regions storing a tiered memory cache line containing target data of the memory operation when the DRAM metadata indicates that the target data is not stored in the DRAM cache line; (Butcher [0028] memory controller 212 first checks page table 214 to determine if the byte address of the memory transaction is associated with a page 242, 252, 262, or 272, that is currently copied into DRAM block 230. [0029] if the check indicates that the memory transaction is not to a page that is copied to DRAM block 230 )
and load the tiered memory cache line containing the target data into the DRAM and load the DRAM cache line into the identified tiered memory region (Butcher [0029] then memory controller 212 sends a swap page command to NVDIMM controller 222 on the command/address bus directing the NVDIMM controller to evict the particular copied page of pages 232 back to the source page of pages 242, 252, 262, or 272, and to copy the addressed page of pages 242, 252, 262, or 272 into the associated page of pages 232.)(i.e., swap page is load target data in the DRAM and load DRAM cache line into tiered memory region)
and update the DRAM metadata. (Butcher [0032] NVDIMM controller 222 is illustrated as including a page table 224 similar to page table 214, and including page table entries 226 similar to page table entries 216. Here, NVDIMM controller 222 will maintain page table 224 to mirror the contents of page table 214, and when memory controller 212 issues a swap page command, the NVDIMM controller will also update page table entries 226 to maintain consistency between the page tables.)
Butcher does not teach DRAM metadata stored in the DRAM for the DRAM cache line
However, Ware teaches DRAM metadata stored in the DRAM for the DRAM cache line (Ware [0010] The operating system maintains a page table in DRAM cache 105 or elsewhere that stores a mapping between virtual addresses VA and physical addresses PA)
Butcher and Ware are analogous art because they are from the same field of memory control. Before the effective filing date of the invention, it would have been obvious to a person of ordinary skill in the art, having the teaching of Butcher and Ware to modify Butcher‘s DRAM metadata (page table) with Ware’s teaching of maintains a page table in DRAM cache. The motivation for doing so would be (Ware [0009]) for improved speed performance.
Regarding Claim 2, Butcher and Ware teach
Butcher teaches wherein each tiered memory region stores a tiered memory cache line corresponding to the DRAM cache line, (Butcher [0025 DRAM block 230 is organized into pages 232. Similarly, NVRAM blocks 240, 250, 260, and 270 are each organized into respective pages 242, 252, 262, and 272, [0026] pages 232 are n-way set associatively mapped to pages 242, 252, 262, and 272) (
and each tiered memory cache line belongs to a different portion of a virtual address space of the memory; (Butcher [0025] NVRAM blocks 240, 250, 260, and 270 are each organized into respective pages 242, 252, 262, and 272 [0033] where NVRAM blocks 240, 250, 260, and 270 consist of a single NVRAM device, the NVRAM device may be organized such that different memory portions of the NVRAM device are organized into the various NVRAM blocks)
wherein the DRAM metadata for the DRAM cache line identifies to which portion of the virtual address space the DRAM cache line belongs and identifies to which portion of the virtual address space the corresponding tiered memory cache lines belong; (Butcher [0027] memory controller 212 includes a page table 214 that maintains information as to the current state of DRAM block 230. Thus each page table entry 216 is associated with a page, and includes an identifier of the NVRAM block 240, 250, 260, and 270 that is currently copied into the associated page 232 of DRAM block 230)
and wherein the processor is configured to identify the tiered memory cache line storing the target data using the DRAM metadata for the DRAM cache line. (Butcher [0028] memory controller 212 first checks page table 214 to determine if the byte address of the memory transaction is associated with a page 242, 252, 262, or 272, that is currently copied into DRAM block 230.)
Butcher teaches page table, but Butcher does not explicitly teach virtual address space. However, Ware teaches virtual address space (Ware [0010] Memory module 100 serves as physical memory in support of a computer operating system that, using a combination of hardware and software, maps memory addresses used by a program, called virtual addresses, into physical addresses PA of memory module 100. The operating system maintains a page table in DRAM cache 105 or elsewhere that stores a mapping between virtual addresses VA and physical addresses PA. Module controller 115 maintains mapping tables within DRAM cache 105 that associate physical addresses PA with NVM addresses FA.)
Butcher and Ware are analogous art because they are from the same field of memory control. Before the effective filing date of the invention, it would have been obvious to a person of ordinary skill in the art, having the teaching of Butcher and Ware to modify Butcher‘s DRAM metadata (page table) with Ware’s teaching of maintains a page table in DRAM cache. The motivation for doing so would be (Ware [0009]) for improved speed performance.
Regarding Claim 8, Butcher teaches
A method of operating a computing system, the method comprising: sending, by an application executing on a processor of the computing system to a dynamic random access memory (DRAM), a memory operation indicating a DRAM cache line stored in the DRAM; (Butcher [0013] Information handling system 100 includes a processors 102 and 104, a chipset 110, a memory 120. The host environment operates to execute machine-executable code, including applications to perform the data processing tasks associated with information handling system 100. [0022] Memory controller 212 represents a portion of the processor complex that is dedicated to the management of the data storage and retrieval from the memory devices of information handling system 200 [0023] NVDIMM 220 represents a memory device of information handling system 200. NVDIMM 220 includes a dynamic random access memory (DRAM) block 230 [0025] DRAM block 230 is organized into pages 232 [0026] pages 232 are n-way set associatively mapped to pages 242, 252, 262, and 272, when memory controller 212 makes a memory access to a byte address within a page that is copied into one of pages 232, the memory transaction is serviced by DRAM block 230 directly. [0028] when processor complex 210 issues a memory transaction, memory controller 212 first checks page table 214 to determine if the byte address of the memory transaction is associated with a page 242, 252, 262, or 272, that is currently copied into DRAM block 230.) (i.e., memory controller is part of processor complex operatively couplet to memory, DRAM page has a cache line stored in the DRAM)
receiving, by the processor, DRAM metadata stored in the DRAM for the DRAM cache line; (Butcher [0027] memory controller 212 includes a page table 214 that maintains information as to the current state of DRAM block 230 [0028] memory controller 212 first checks page table 214 to determine if the byte address of the memory transaction is associated with a page 242, 252, 262, or 272, that is currently copied into DRAM block 230.) (i.e., page table 214 is DRAM metadata)
identifying, by the processor, a tiered memory region of multiple tiered memory regions storing a tiered memory cache line containing target data of the memory operation when the DRAM metadata indicates that the target data is not stored in the DRAM cache line; (Butcher [0028] memory controller 212 first checks page table 214 to determine if the byte address of the memory transaction is associated with a page 242, 252, 262, or 272, that is currently copied into DRAM block 230. [0029] if the check indicates that the memory transaction is not to a page that is copied to DRAM block 230)
and loading the tiered memory cache line containing the target data into the DRAM, loading the DRAM cache line into the identified tiered memory region, (Butcher [0029] then memory controller 212 sends a swap page command to NVDIMM controller 222 on the command/address bus directing the NVDIMM controller to evict the particular copied page of pages 232 back to the source page of pages 242, 252, 262, or 272, and to copy the addressed page of pages 242, 252, 262, or 272 into the associated page of pages 232.)(i.e., swap page is load target data in the DRAM and load DRAM cache line into tiered memory region)
and updating the DRAM metadata. (Butcher [0032] NVDIMM controller 222 is illustrated as including a page table 224 similar to page table 214, and including page table entries 226 similar to page table entries 216. Here, NVDIMM controller 222 will maintain page table 224 to mirror the contents of page table 214, and when memory controller 212 issues a swap page command, the NVDIMM controller will also update page table entries 226 to maintain consistency between the page tables.)
Butcher does not teach DRAM metadata stored in the DRAM for the DRAM cache line
However, Ware teaches DRAM metadata stored in the DRAM for the DRAM cache line (Ware [0010] The operating system maintains a page table in DRAM cache 105 or elsewhere that stores a mapping between virtual addresses VA and physical addresses PA)
Butcher and Ware are analogous art because they are from the same field of memory control. Before the effective filing date of the invention, it would have been obvious to a person of ordinary skill in the art, having the teaching of Butcher and Ware to modify Butcher‘s DRAM metadata (page table) with Ware’s teaching of maintains a page table in DRAM cache. The motivation for doing so would be (Ware [0009]) for improved speed performance.
Regarding Claim 9, Butcher and Ware teach
Butcher teaches storing a tiered memory cache line corresponding to the DRAM cache line in each tiered memory region, wherein each corresponding tiered memory cache line belongs to a different portion of a virtual address space of the memory; (Butcher [0025 DRAM block 230 is organized into pages 232. Similarly, NVRAM blocks 240, 250, 260, and 270 are each organized into respective pages 242, 252, 262, and 272, [0026] pages 232 are n-way set associatively mapped to pages 242, 252, 262, and 272)
and wherein the identifying the tiered memory region storing the tiered memory cache line containing the target data includes: identifying, using the DRAM metadata, to which portion of the virtual address space the DRAM cache line belongs and to which portion of the virtual address space the corresponding tiered memory cache lines belong; (Butcher [0027] memory controller 212 includes a page table 214 that maintains information as to the current state of DRAM block 230. Thus each page table entry 216 is associated with a page, and includes an identifier of the NVRAM block 240, 250, 260, and 270 that is currently copied into the associated page 232 of DRAM block 230)
and identifying the cache line containing the target data according to which portion of the virtual address space the target data belongs. (Butcher [0027] Each page table entry 216 includes a valid bit to identify whether or not the currently mapped entry of the page table entries is valid, that is, that the page table entry correctly identifies which page 242, 252, 262, or 272 is currently copied to page 232.)
Butcher teaches page table, but Butcher does not explicitly teach virtual address space. However, Ware teaches virtual address space (Ware [0010] Memory module 100 serves as physical memory in support of a computer operating system that, using a combination of hardware and software, maps memory addresses used by a program, called virtual addresses, into physical addresses PA of memory module 100. The operating system maintains a page table in DRAM cache 105 or elsewhere that stores a mapping between virtual addresses VA and physical addresses PA. Module controller 115 maintains mapping tables within DRAM cache 105 that associate physical addresses PA with NVM addresses FA.)
Butcher and Ware are analogous art because they are from the same field of memory control. Before the effective filing date of the invention, it would have been obvious to a person of ordinary skill in the art, having the teaching of Butcher and Ware to modify Butcher‘s DRAM metadata (page table) with Ware’s teaching of maintains a page table in DRAM cache. The motivation for doing so would be (Ware [0009]) for improved speed performance.
Regarding Claim 13, Butcher and Ware teach
Butcher teaches wherein the sending the memory operation to the DRAM includes sending a memory operation (Butcher [0028] when processor complex 210 issues a memory transaction, memory controller 212 first checks page table 214 to determine if the byte address of the memory transaction is associated with a page 242, 252, 262, or 272, that is currently copied into DRAM block 230)
Butcher does not teach but Ware teaches designating a cache line size larger than sixty-four bytes (64B). (Ware [0021] Memory module 100 communicates 80B cache lines with the requesting host. These 80B cache lines provide an access granularity of 72B, 64B for data and 8B for error-detection and correction (EDC). DRAM pages 125 store 80B cache lines and accommodate the host's 72B access granularity.) (i.e., 80B cache line is larger than 64B)
Butcher and Ware are analogous art because they are from the same field of memory control. Before the effective filing date of the invention, it would have been obvious to a person of ordinary skill in the art, having the teaching of Butcher and Ware to modify Butcher‘s DRAM metadata (page table) with Ware’s teaching of maintains a page table in DRAM cache. The motivation for doing so would be (Ware [0009]) for improved speed performance.
Regarding Claim 14, Butcher and Ware teach
The method of claim 8, wherein the sending the memory operation from the processor includes sending a memory operation including an address of a cache line stored in a memory tier portion of the DRAM or in a tiered memory region of multiple tiered memory regions that are each a size of the memory tier portion of the DRAM. (Butcher [0028] when processor complex 210 issues a memory transaction, memory controller 212 first checks page table 214 to determine if the byte address of the memory transaction is associated with a page 242, 252, 262, or 272, that is currently copied into DRAM block 230. Here, memory controller 212 first determines that the byte address is within the memory range one of NVRAM blocks 240, 250, 260, and 270 [0025] NVRAM blocks 240, 250, 260, and 270 are each organized into respective pages 242, 252, 262, and 272, where the NVRAM blocks each include the same number of pages as DRAM block 230)
Regarding Claim 16, Butcher teaches
A host device comprising: a host processor configured to: send a memory operation from an application executing on the host processor to a dynamic random access memory (DRAM) of a memory system, wherein the memory operation includes an address of a DRAM cache line stored in the DRAM; (Butcher [0013] Information handling system 100 includes a processors 102 and 104, a chipset 110, a memory 120. The host environment operates to execute machine-executable code, including applications to perform the data processing tasks associated with information handling system 100. [0022] Memory controller 212 represents a portion of the processor complex that is dedicated to the management of the data storage and retrieval from the memory devices of information handling system 200 [0023] NVDIMM 220 represents a memory device of information handling system 200. NVDIMM 220 includes a dynamic random access memory (DRAM) block 230 [0025] DRAM block 230 is organized into pages 232 [0026] pages 232 are n-way set associatively mapped to pages 242, 252, 262, and 272, when memory controller 212 makes a memory access to a byte address within a page that is copied into one of pages 232, the memory transaction is serviced by DRAM block 230 directly. [0028] when processor complex 210 issues a memory transaction, memory controller 212 first checks page table 214 to determine if the byte address of the memory transaction is associated with a page 242, 252, 262, or 272, that is currently copied into DRAM block 230.) (i.e., memory controller is part of processor complex operatively couplet to memory, DRAM page has a cache line stored in the DRAM)
decode DRAM metadata stored in the DRAM for the DRAM cache line; (Butcher [0027] memory controller 212 includes a page table 214 that maintains information as to the current state of DRAM block 230 [0028] memory controller 212 first checks page table 214 to determine if the byte address of the memory transaction is associated with a page 242, 252, 262, or 272, that is currently copied into DRAM block 230.) (i.e., page table 214 is DRAM metadata)
identify a tiered memory region, of multiple tiered memory regions of the memory system, storing a tiered memory cache line containing target data of the memory operation when the DRAM metadata indicates that the target data is not stored in the DRAM cache line; (Butcher [0028] memory controller 212 first checks page table 214 to determine if the byte address of the memory transaction is associated with a page 242, 252, 262, or 272, that is currently copied into DRAM block 230. [0029] if the check indicates that the memory transaction is not to a page that is copied to DRAM block 230 )
and swap data of the tiered memory cache line of identified tiered memory region and the DRAM cache line (Butcher [0029] then memory controller 212 sends a swap page command to NVDIMM controller 222 on the command/address bus directing the NVDIMM controller to evict the particular copied page of pages 232 back to the source page of pages 242, 252, 262, or 272, and to copy the addressed page of pages 242, 252, 262, or 272 into the associated page of pages 232.)(i.e., swap page is swap data of tiered memory region and DRAM cache line)
in response to receiving the metadata. (Butcher [0032] NVDIMM controller 222 is illustrated as including a page table 224 similar to page table 214, and including page table entries 226 similar to page table entries 216. Here, NVDIMM controller 222 will maintain page table 224 to mirror the contents of page table 214, and when memory controller 212 issues a swap page command, the NVDIMM controller will also update page table entries 226 to maintain consistency between the page tables.)
Butcher does not teach DRAM metadata stored in the DRAM for the DRAM cache line
However, Ware teaches DRAM metadata stored in the DRAM for the DRAM cache line (Ware [0010] The operating system maintains a page table in DRAM cache 105 or elsewhere that stores a mapping between virtual addresses VA and physical addresses PA)
Butcher and Ware are analogous art because they are from the same field of memory control. Before the effective filing date of the invention, it would have been obvious to a person of ordinary skill in the art, having the teaching of Butcher and Ware to modify Butcher‘s DRAM metadata (page table) with Ware’s teaching of maintains a page table in DRAM cache. The motivation for doing so would be (Ware [0009]) for improved speed performance.
Regarding Claim 17, Butcher and Ware teach
Butcher teaches identify a portion of a virtual address space of the memory system that includes the target data; (Butcher [0027] memory controller 212 includes a page table 214 that maintains information as to the current state of DRAM block 230. Thus each page table entry 216 is associated with a page, and includes an identifier of the NVRAM block 240, 250, 260, and 270 that is currently copied into the associated page 232 of DRAM block 230)
and decode, in the DRAM metadata, a tiered memory cache line corresponding to the DRAM cache line for the identified portion of the virtual memory address space and the tiered memory region storing the identified tiered memory cache line. (Butcher [0027] Each page table entry 216 includes a valid bit to identify whether or not the currently mapped entry of the page table entries is valid, that is, that the page table entry correctly identifies which page 242, 252, 262, or 272 is currently copied to page 232.)
Butcher teaches page table, but Butcher does not explicitly teach virtual address space. However, Ware teaches virtual address space (Ware [0010] Memory module 100 serves as physical memory in support of a computer operating system that, using a combination of hardware and software, maps memory addresses used by a program, called virtual addresses, into physical addresses PA of memory module 100. The operating system maintains a page table in DRAM cache 105 or elsewhere that stores a mapping between virtual addresses VA and physical addresses PA. Module controller 115 maintains mapping tables within DRAM cache 105 that associate physical addresses PA with NVM addresses FA.)
Butcher and Ware are analogous art because they are from the same field of memory control. Before the effective filing date of the invention, it would have been obvious to a person of ordinary skill in the art, having the teaching of Butcher and Ware to modify Butcher‘s DRAM metadata (page table) with Ware’s teaching of maintains a page table in DRAM cache. The motivation for doing so would be (Ware [0009]) for improved speed performance.
Claim(s) 3, 7, 10, 15, 18 is/are rejected under 35 U.S.C. 103 as being unpatentable over Butcher (US 20190227709), in view of Ware (US 20200250090), further in view of Benhase (US 20140208018).
Regarding Claim 3, Butcher and Ware teach
Butcher teaches wherein the DRAM metadata for the DRAM cache line identifies to which portion of a virtual address space of the memory the cache line in the DRAM belongs; (Butcher [0027] To manage the operations of NVDIMM 220, memory controller 212 includes a page table 214 that maintains information as to the current state of DRAM block 230.)
and wherein the processor is configured to search tiered memory metadata stored in the tiered memory regions to identify which tiered memory region of the multiple tiered memory regions includes a tiered memory cache line containing the target data when the DRAM metadata indicates that the target data is not stored in the DRAM cache line. (Butcher [0022] Memory controller 212 represents a portion of the processor complex [0028] memory controller 212 first checks page table 214 to determine if the byte address of the memory transaction is associated with a page 242, 252, 262, or 272, that is currently copied into DRAM block 230 [0026] when memory controller 212 makes a memory access to a byte address within a page that is not copied into one of pages 232, then the memory controller directs NVDIMM controller 222 to evict the particular copied page of pages 232 back to the source page of pages 242, 252, 262, or 272, and to copy the addressed page of pages 242, 252, 262, or 272 into the associated page of pages 232, before servicing the memory access directly from DRAM block 230.)(i.e., memory controller 212 is part of the processor complex, memory controller 212 checks page table 214 is processor search metadata)
Butcher teaches page table, but Butcher does not explicitly teach virtual address space. However, Ware teaches virtual address space (Ware [0010] Memory module 100 serves as physical memory in support of a computer operating system that, using a combination of hardware and software, maps memory addresses used by a program, called virtual addresses, into physical addresses PA of memory module 100. The operating system maintains a page table in DRAM cache 105 or elsewhere that stores a mapping between virtual addresses VA and physical addresses PA. Module controller 115 maintains mapping tables within DRAM cache 105 that associate physical addresses PA with NVM addresses FA.)
Butcher and Ware are analogous art because they are from the same field of memory control. Before the effective filing date of the invention, it would have been obvious to a person of ordinary skill in the art, having the teaching of Butcher and Ware to modify Butcher‘s DRAM metadata (page table) with Ware’s teaching of maintains a page table in DRAM cache. The motivation for doing so would be (Ware [0009]) for improved speed performance.
Butcher-Ware teaches two metadata/page tables: page table 214 and page table 224 (Butcher [0027] memory controller 212 includes a page table 214 that maintains information as to the current state of DRAM block 230. [0032] NVDIMM controller 222 is illustrated as including a page table 224 similar to page table 214. NVDIMM controller 222 will maintain page table 224 to mirror the contents of page table 214). (i.e., page table 214 is DRAM metadata. page table 224, mirror the content of page table 214, is also DRAM metadata)
Butcher-Ware does not teach tiered memory metadata stored in the tiered memory regions.
However, Benhase teaches tiered memory metadata stored in the tiered memory regions (Benhase FIG. 3 metadata 304a for primary cache, 304b for secondary cache [0035] the primary cache may be referred to as a high-speed or higher-speed cache (as it typically has access to the fastest Dynamic Read Only Memory or DRAM architectures), and the secondary, Flash Cache may be referred to as a low-speed or lower-speed cache (in comparison to the primary, DRAM cache)) (i.e., metadata 304a is DRAM metadata, metadata 304b is tiered memory metadata stored in the tired memory regions)
Butcher, Ware and Benhase are analogous art because they are from the same field of memory control. Before the effective filing date of the invention, it would have been obvious to a person of ordinary skill in the art, having the teaching of Butcher, Ware and Benhase to modify Butcher-Ware‘s metadata with Benhase’s teaching of tiering caching with metadata at tiered levels of storage. The motivation for doing so would be that (Benhase [0007]) in tiered storage architectures, the overall performance of the storage environment may be further enhanced.
Regarding Claim 7, Butcher and Ware teach
Butcher-Ware teaches wherein the memory tiering portion of the DRAM is a level two (L2) cache for the computing system; (Butcher [0003] A non-volatile dual in-line memory module (NVDIMM) may include a dynamic random access memory (DRAM) block)
and wherein the multiple tiered memory regions are a level three (L3) cache for the computing system (Butcher [0003] A non-volatile dual in-line memory module (NVDIMM) may include a plurality of non-volatile random access memory (NVRAM) blocks)
Butcher-Ware does not teach a level two (L2) cache for the computing system; a level three (L3) cache for the computing system.
However, Benhase teaches a level two (L2) cache for the computing system; a level three (L3) cache for the computing system [0053] A certain Flash Cache may be configured with 1-128 block cache, level 2 (L2), an upper tier, and a lower tier having 1 GB migrate HDD on L3)
Butcher, Ware and Benhase are analogous art because they are from the same field of memory control. Before the effective filing date of the invention, it would have been obvious to a person of ordinary skill in the art, having the teaching of Butcher, Ware and Benhase to modify Butcher-Ware‘s metadata with Benhase’s teaching of tiering caching with metadata at tiered levels of storage. The motivation for doing so would be that (Benhase [0007]) in tiered storage architectures, the overall performance of the storage environment may be further enhanced.
Regarding Claim 10, Butcher and Ware teach
Butcher teaches wherein the identifying the tiered memory region that contains the target data includes: identifying, using the DRAM metadata, to which portion of a virtual address space of the memory the DRAM cache line belongs; (Butcher [0027] To manage the operations of NVDIMM 220, memory controller 212 includes a page table 214 that maintains information as to the current state of DRAM block 230.)
and searching, by the processor, metadata stored in the tiered memory regions to identify which tiered memory region of the multiple tiered memory regions includes a tiered memory cache line containing the target data when the DRAM metadata indicates that the target data is not stored in the DRAM cache line. (Butcher [0022] Memory controller 212 represents a portion of the processor complex [0028] memory controller 212 first checks page table 214 to determine if the byte address of the memory transaction is associated with a page 242, 252, 262, or 272, that is currently copied into DRAM block 230 [0026] when memory controller 212 makes a memory access to a byte address within a page that is not copied into one of pages 232, then the memory controller directs NVDIMM controller 222 to evict the particular copied page of pages 232 back to the source page of pages 242, 252, 262, or 272, and to copy the addressed page of pages 242, 252, 262, or 272 into the associated page of pages 232, before servicing the memory access directly from DRAM block 230.)(i.e., memory controller 212 is part of the processor complex, memory controller 212 checks page table 214 is processor search metadata)
Butcher teaches page table, but Butcher does not explicitly teach virtual address space. However, Ware teaches virtual address space (Ware [0010] Memory module 100 serves as physical memory in support of a computer operating system that, using a combination of hardware and software, maps memory addresses used by a program, called virtual addresses, into physical addresses PA of memory module 100. The operating system maintains a page table in DRAM cache 105 or elsewhere that stores a mapping between virtual addresses VA and physical addresses PA. Module controller 115 maintains mapping tables within DRAM cache 105 that associate physical addresses PA with NVM addresses FA.)
Butcher and Ware are analogous art because they are from the same field of memory control. Before the effective filing date of the invention, it would have been obvious to a person of ordinary skill in the art, having the teaching of Butcher and Ware to modify Butcher‘s DRAM metadata (page table) with Ware’s teaching of maintains a page table in DRAM cache. The motivation for doing so would be (Ware [0009]) for improved speed performance.
Butcher-Ware teaches two metadata/page tables: page table 214 and page table 224 (Butcher [0027] memory controller 212 includes a page table 214 that maintains information as to the current state of DRAM block 230. [0032] NVDIMM controller 222 is illustrated as including a page table 224 similar to page table 214. NVDIMM controller 222 will maintain page table 224 to mirror the contents of page table 214). (i.e., page table 214 is DRAM metadata. page table 224, mirror the content of page table 214, is also DRAM metadata)
Butcher-Ware does not teach tiered memory metadata stored in the tiered memory regions.
However, Benhase teaches metadata stored in the tiered memory regions (Benhase FIG. 3 metadata 304a for primary cache, 304b for secondary cache [0035] the primary cache may be referred to as a high-speed or higher-speed cache (as it typically has access to the fastest Dynamic Read Only Memory or DRAM architectures), and the secondary, Flash Cache may be referred to as a low-speed or lower-speed cache (in comparison to the primary, DRAM cache)) (i.e., metadata 304a is DRAM metadata, metadata 304b is tiered memory metadata stored in the tired memory regions)
Butcher, Ware and Benhase are analogous art because they are from the same field of memory control. Before the effective filing date of the invention, it would have been obvious to a person of ordinary skill in the art, having the teaching of Butcher, Ware and Benhase to modify Butcher-Ware‘s metadata with Benhase’s teaching of tiering caching with metadata at tiered levels of storage. The motivation for doing so would be that (Benhase [0007]) in tiered storage architectures, the overall performance of the storage environment may be further enhanced.
Regarding Claim 15, Butcher and Ware teach
Butcher-Ware teaches wherein the sending the memory operation to the DRAM includes sending the memory operation to a level two (L2) cache in the DRAM; (Butcher [0003] A non-volatile dual in-line memory module (NVDIMM) may include a dynamic random access memory (DRAM) block [0028] when processor complex 210 issues a memory transaction, memory controller 212 first checks page table 214 to determine if the byte address of the memory transaction is associated with a page 242, 252, 262, or 272, that is currently copied into DRAM block 230)
and wherein the identifying the tiered memory region including the target data includes identifying the tiered memory region of multiple tiered memory regions of a level three (L3) cache that includes the target data. (Butcher [0003] A non-volatile dual in-line memory module (NVDIMM) may include a plurality of non-volatile random access memory (NVRAM) blocks [0028] when processor complex 210 issues a memory transaction, memory controller 212 first checks page table 214, memory controller 212 first determines that the byte address is within the memory range one of NVRAM blocks 240, 250, 260, and 270)
Butcher-Ware does not teach a level two (L2) cache; a level three (L3) cache
However, Benhase teaches a level two (L2) cache; a level three (L3) cache (Benhase [0053] A certain Flash Cache may be configured with 1-128 block cache, level 2 (L2), an upper tier, and a lower tier having 1 GB migrate HDD on L3)
Butcher, Ware and Benhase are analogous art because they are from the same field of memory control. Before the effective filing date of the invention, it would have been obvious to a person of ordinary skill in the art, having the teaching of Butcher, Ware and Benhase to modify Butcher-Ware‘s metadata with Benhase’s teaching of tiering caching with metadata at tiered levels of storage. The motivation for doing so would be that (Benhase [0007]) in tiered storage architectures, the overall performance of the storage environment may be further enhanced.
Regarding Claim 18, Butcher and Ware teach
Butcher teaches identify a portion of a virtual address space of the memory that contains the target data; (Butcher [0027] To manage the operations of NVDIMM 220, memory controller 212 includes a page table 214 that maintains information as to the current state of DRAM block 230.)
and search tiered memory metadata stored in the tiered memory regions to identify which tiered memory cache line of the multiple tiered memory regions contains the target data when the target data is not in the DRAM cache line. (Butcher [0022] Memory controller 212 represents a portion of the processor complex [0028] memory controller 212 first checks page table 214 to determine if the byte address of the memory transaction is associated with a page 242, 252, 262, or 272, that is currently copied into DRAM block 230 [0026] when memory controller 212 makes a memory access to a byte address within a page that is not copied into one of pages 232, then the memory controller directs NVDIMM controller 222 to evict the particular copied page of pages 232 back to the source page of pages 242, 252, 262, or 272, and to copy the addressed page of pages 242, 252, 262, or 272 into the associated page of pages 232, before servicing the memory access directly from DRAM block 230.)(i.e., memory controller 212 is part of the processor complex, memory controller 212 checks page table 214 is processor search metadata)
Butcher teaches page table, but Butcher does not explicitly teach virtual address space. However, Ware teaches virtual address space (Ware [0010] Memory module 100 serves as physical memory in support of a computer operating system that, using a combination of hardware and software, maps memory addresses used by a program, called virtual addresses, into physical addresses PA of memory module 100. The operating system maintains a page table in DRAM cache 105 or elsewhere that stores a mapping between virtual addresses VA and physical addresses PA. Module controller 115 maintains mapping tables within DRAM cache 105 that associate physical addresses PA with NVM addresses FA.)
Butcher and Ware are analogous art because they are from the same field of memory control. Before the effective filing date of the invention, it would have been obvious to a person of ordinary skill in the art, having the teaching of Butcher and Ware to modify Butcher‘s DRAM metadata (page table) with Ware’s teaching of maintains a page table in DRAM cache. The motivation for doing so would be (Ware [0009]) for improved speed performance.
Butcher-Ware teaches two metadata/page tables: page table 214 and page table 224 (Butcher [0027] memory controller 212 includes a page table 214 that maintains information as to the current state of DRAM block 230. [0032] NVDIMM controller 222 is illustrated as including a page table 224 similar to page table 214. NVDIMM controller 222 will maintain page table 224 to mirror the contents of page table 214). (i.e., page table 214 is DRAM metadata. page table 224, mirror the content of page table 214, is also DRAM metadata)
Butcher-Ware does not teach tiered memory metadata stored in the tiered memory regions.
However, Benhase teaches tiered memory metadata stored in the tiered memory regions (Benhase FIG. 3 metadata 304a for primary cache, 304b for secondary cache [0035] the primary cache may be referred to as a high-speed or higher-speed cache (as it typically has access to the fastest Dynamic Read Only Memory or DRAM architectures), and the secondary, Flash Cache may be referred to as a low-speed or lower-speed cache (in comparison to the primary, DRAM cache)) (i.e., metadata 304a is DRAM metadata, metadata 304b is tiered memory metadata stored in the tired memory regions)
Butcher, Ware and Benhase are analogous art because they are from the same field of memory control. Before the effective filing date of the invention, it would have been obvious to a person of ordinary skill in the art, having the teaching of Butcher, Ware and Benhase to modify Butcher-Ware‘s metadata with Benhase’s teaching of tiering caching with metadata at tiered levels of storage. The motivation for doing so would be that (Benhase [0007]) in tiered storage architectures, the overall performance of the storage environment may be further enhanced.
Butcher, Ware and Benhase are analogous art because they are from the same field of memory control. Before the effective filing date of the invention, it would have been obvious to a person of ordinary skill in the art, having the teaching of Butcher, Ware and Benhase to modify Butcher-Ware‘s metadata with Benhase’s teaching of tiering caching with metadata at tiered levels of storage. The motivation for doing so would be that (Benhase [0007]) in tiered storage architectures, the overall performance of the storage environment may be further enhanced.
Relevant Prior Art
The prior art made of record and not relied upon is considered pertinent to applicant’s disclosure.
Haghighi (US 20190369879) teaches Unified addressing and hierarchical heterogeneous storage and memory
Talagala (US 20130262752) teaches a multi-tiered cache manager.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to WEI MA whose telephone number is (571)272-2468. The examiner can normally be reached Monday through Friday from 8am to 5pm.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, JARED RUTZ can be reached at 571-272-5535. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/WEI MA/Examiner, Art Unit 2135
Prosecution Insights