DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 04/29/2025 and 01/28/2026 are in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Claim Interpretation
The following is a quotation of 35 U.S.C. 112(f):
(f) Element in Claim for a Combination. – An element in a claim for a combination may be expressed as a means or step for performing a specified function without the recital of structure, material, or acts in support thereof, and such claim shall be construed to cover the corresponding structure, material, or acts described in the specification and equivalents thereof.
The following is a quotation of pre-AIA 35 U.S.C. 112, sixth paragraph:
An element in a claim for a combination may be expressed as a means or step for performing a specified function without the recital of structure, material, or acts in support thereof, and such claim shall be construed to cover the corresponding structure, material, or acts described in the specification and equivalents thereof.
The claims in this application are given their broadest reasonable interpretation using the plain meaning of the claim language in light of the specification as it would be understood by one of ordinary skill in the art. The broadest reasonable interpretation of a claim element (also commonly referred to as a claim limitation) is limited by the description in the specification when 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, is invoked.
As explained in MPEP § 2181, subsection I, claim limitations that meet the following three-prong test will be interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph:
(A) the claim limitation uses the term “means” or “step” or a term used as a substitute for “means” that is a generic placeholder (also called a nonce term or a non-structural term having no specific structural meaning) for performing the claimed function;
(B) the term “means” or “step” or the generic placeholder is modified by functional language, typically, but not always linked by the transition word “for” (e.g., “means for”) or another linking word or phrase, such as “configured to” or “so that”; and
(C) the term “means” or “step” or the generic placeholder is not modified by sufficient structure, material, or acts for performing the claimed function.
Use of the word “means” (or “step”) in a claim with functional language creates a rebuttable presumption that the claim limitation is to be treated in accordance with 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph. The presumption that the claim limitation is interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, is rebutted when the claim limitation recites sufficient structure, material, or acts to entirely perform the recited function.
Absence of the word “means” (or “step”) in a claim creates a rebuttable presumption that the claim limitation is not to be treated in accordance with 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph. The presumption that the claim limitation is not interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, is rebutted when the claim limitation recites function without reciting sufficient structure, material or acts to entirely perform the recited function.
Claim limitations in this application that use the word “means” (or “step”) are being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, except as otherwise indicated in an Office action. Conversely, claim limitations in this application that do not use the word “means” (or “step”) are not being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, except as otherwise indicated in an Office action.
This application includes one or more claim limitations that do not use the word “means,” but are nonetheless being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, because the claim limitation(s) uses a generic placeholder that is coupled with functional language without reciting sufficient structure to perform the recited function and the generic placeholder is not preceded by a structural modifier. Such claim limitation(s) is/are:
“speculatively executing, by a computing device, instructions…” in claim 11, which will be interpreted as execution units 126 (shown in Fig. 1)
“recording, by the computing device, information indicating a determined direction…” in claim 11, which will be interpreted as a branch information table and branch re-use table according to [0026] of the specification
“storing, by the computing device, a mask field…” in claim 11, which will be interpreted as live-out mask vector 430 according to [0059] of the specification
“setting, by the computing device, a given indicator in the mask field to a first value…” in claim 11, which will be interpreted as re-use control 410 according to [0059] of the specification
“setting, by the computing device, a given indicator in the mask field to a second value…” in claim 11, which will be interpreted as re-use control 410 according to [0059] of the specification
“determining, by the computing device… that the second control transfer instruction does not depend on data…” in claim 11, which will be interpreted as re-use control 410 according to [0055] of the specification
“fetching and executing, by the computing device… one or more instructions…” in claim 11, which will be interpreted as instruction fetch unit 102 and execution units 126, according to [0029] of the specification
Because this/these claim limitation(s) is/are being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, it/they is/are being interpreted to cover the corresponding structure described in the specification as performing the claimed function, and equivalents thereof.
If applicant does not intend to have this/these limitation(s) interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, applicant may: (1) amend the claim limitation(s) to avoid it/them being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph (e.g., by reciting sufficient structure to perform the claimed function); or (2) present a sufficient showing that the claim limitation(s) recite(s) sufficient structure to perform the claimed function so as to avoid it/them being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph.
Claim Objections
Claims 1, 16, and 20 are objected to because of the following informalities:
Claim 1 line 3- insert --to-- before “predict”
Claim 16 line 2-3- “re-determines” appears to be a typo and should be corrected to “re-determine”
Claim 20 line 7- insert --to-- before “predict”
Appropriate correction is required.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 1-10 and 20 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 1 recites “control circuitry configured to… fetch and execute one or more instructions” in the last limitation. However, claim 1 also recites front-end circuitry configured to fetch instructions and execution circuitry configured to speculatively execute instructions. It is thus unclear which circuitry fetches and executes instructions. For purposes of examination, this limitation will be interpreted as any circuitry that fetches and executes instructions.
Claim 20 recites the same limitations and is rejected for the same reasons.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1, 5-6, 8-9, 11, 15-16, and 18-20 are rejected under 35 U.S.C. 103 as being unpatentable over Pusdesris US 10,990,403 in view of Srinivasan US 2005/0138480.
Regarding claim 1, Pusdesris teaches:
1. An apparatus, comprising:
processor front-end circuitry configured to fetch and decode instructions (Fig. 1, 108/116);
prediction circuitry (Fig. 1, 102) configured predict directions of control transfer instructions (col 9 lines 10-18 and col 10 lines 12-15 describes that the base predictor predicts branch outcomes which are taken/not taken directions);
execution circuitry (Fig. 1, 122) configured to speculatively execute instructions based on a predicted direction of a first control transfer instruction (col 9 lines 10-21: instructions are fetched and executed based on the predicted direction of the first control transfer instruction 202);
result storage circuitry (Fig. 3, 302a) configured to record information indicating a determined direction for a speculatively-executed second control transfer instruction that is younger than the first control transfer instruction (col 9 lines 22-42 and 50-60: the prediction storage circuitry 302a records an outcome/determined direction of a later/younger instruction 208 (i.e., a second control transfer instruction) that was speculatively executed on an incorrect control path of the first control transfer instruction 202, see also col 9 lines 5-6 disclosing that the later instruction 208 may be a control flow path altering instruction);
control circuitry (Fig. 1, 104);
and to fetch and execute one or more instructions using a recorded direction from the speculative execution of the second control transfer instruction (col 9 lines 22-42 and lines 50-60 describe using the stored outcome of the later instruction (i.e., a recorded direction from speculative execution of the second control transfer instruction) to re-execute the later instruction and col 7 lines 30-33 describes that subsequent instructions are executed based on the predicted outcome from the replay predictor, thus any subsequent instruction on the predicted path of the later instruction is fetched and executed based on/using the stored outcome/recorded direction of the second instruction).
Although Pusdesris teaches that its technique is particularly beneficial when the later instruction does not directly depend on the outcome of the earlier instruction and is thus on both the incorrect and correct control flow path (col 3 lines 40-44), Pusdesris does not explicitly teach:
control circuitry configured to:
store a mask field that includes a respective indicator per architectural register for a set of architectural registers supported by the apparatus;
set a given indicator in the mask field to a first value in response to a write to the corresponding architectural register by an instruction between the first control transfer instruction and a reconvergence point for the first control transfer instruction;
set a given indicator in the mask field to a second value in response to a write to the corresponding architectural register by an instruction subsequent to the reconvergence point that does not depend on any instruction between the first control transfer instruction and the reconvergence point;
in response to a misprediction by the prediction circuitry for the first control transfer instruction, determine that the second control transfer instruction does not depend on data from any instruction between the first control transfer instruction and the reconvergence point based on one or more indicators in the mask field, that correspond to one or more input operands of the second control transfer instruction; and
based on the determination, fetch and execute one or more instructions using a recorded direction from the speculative execution of the second control transfer instruction.
However, Srinivasan teaches:
control circuitry (Fig. 3 ATB 322 and the scoreboard, see [0026]) configured to:
store a mask field that includes a respective indicator per architectural register for a set of architectural registers supported by the apparatus ([0026]: the scoreboard (i.e., a mask field) includes a flag (i.e., a respective indicator) for each of the physical registers);
set a given indicator in the mask field to a first value in response to a write to the corresponding architectural register by an instruction between the first control transfer instruction and a reconvergence point for the first control transfer instruction ([0026]: the flag is set (i.e., to a first value) when a corresponding register is written by an instruction on the non-convergent mispredicted path (i.e., an instruction between the first control transfer instruction and the reconvergence point));
set a given indicator in the mask field to a second value in response to a write to the corresponding architectural register by an instruction subsequent to the reconvergence point that does not depend on any instruction between the first control transfer instruction and the reconvergence point ([0026]: a flag may be cleared (i.e., set to a second value) when a subsequent convergent instruction (i.e., any instruction subsequent to the reconvergence point, including instructions that do not depend on any instruction between the first control transfer instruction and the reconvergence point) writes to the corresponding register);
in response to a misprediction by the prediction circuitry for the first control transfer instruction, determine that the second control transfer instruction does not depend on data from any instruction between the first control transfer instruction and the reconvergence point based on one or more indicators in the mask field, that correspond to one or more input operands of the second control transfer instruction ([0026] describes re-executing convergent instructions along the mispredicted path (i.e., in response to a misprediction for the first control transfer instruction) if their source registers are flagged and that the source registers are flagged when they are written by a recovery move on the non-convergent path and are cleared when subsequent convergent instructions write to them, this indicates that the flags of source registers used by a convergent instruction (i.e., one or more indicators that correspond to one or more input operands of the second control transfer instruction) are used to determine whether the convergent instruction depends on data from instructions between the first control transfer instruction and the reconvergence point (if so, the flag is set by a non-convergent path instruction and if not, the flag would not be reset));
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to modify the replay predictor of Pusdesris to include the ATB and scoreboard of Srinivasan such that the combination would use the ATB to determine reconvergence points and use the scoreboard to determine when the later/second control transfer instruction does not depend on an instruction between the earlier/first control transfer instruction and can reuse its stored outcome based on that determination to continue fetch and execute instructions on the stored outcome path of the second control transfer instruction. One of ordinary skill in the art would have been motivated to modify Pusdesris to use the known technique of Srinivasan (i.e., using an ATB to determine exact convergence and using a scoreboard to determine instruction dependency) on the known device of Pusdesris as this would have yielded predictable results and resulted in an improved system (i.e., by allowing the system to determine when the later instruction is independent and may reuse its results).
Claim 11 is directed to a method performing the steps of the apparatus of claim 1 and is rejected for the same reasons. Claim 20 is directed to a non-transitory computer readable storage medium for implementing the apparatus of claim 1 and is rejected for similar reasons.
Regarding claim 5, Pusdesris in view of Srinivasan teaches:
5. The apparatus of claim 1,
Pusdesris in view of Srinivasan, as currently mapped, does not explicitly teach:
wherein the control circuitry is further configured to use, based on the determination, use a recorded destination for the second control transfer instruction.
However, Srinivasan further teaches predicting branch target addresses, see [0020].
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to modify the replay predictor of Pusdesris to predict branch target addresses as taught by Srinivasan. In this combination, the replay predictor of Pusdesris will store a branch target address outcome (in addition to the taken/not taken direction outcome) for the later branch in its prediction storage circuitry for use in predicting the target/destination of the later instruction (based on determining that the later instruction may reuse its outcome). One of ordinary skill in the art would have been motivated to make this modification to speed up execution since predicting a branch target address would allow for fetching and executing instructions at the target address to begin without waiting for the actual target address to be generated.
Claim 15 is directed to a method performing the steps of the apparatus of claim 5 and is rejected for the same reasons.
Regarding claim 6, Pusdesris in view of Srinivasan teaches:
6. The apparatus of claim 1, wherein the fetch and execution using the recorded direction is performed after a flush and replay of the second control transfer instruction (Pusdesris col 9 lines 22-42: the later instruction is flushed and then re-executed/replayed using the recorded outcome, which would include fetching and executing instructions on the path of the later instruction), wherein the apparatus is configured not to re-determine a direction for the second control transfer instruction based on use of the recorded direction (Pusdesris col 9 lines 22-42: by reusing the stored outcome, the apparatus does not re-determine the direction for the later/second control transfer instruction, see also col 11 lines 34-40 describing that the stored prediction from the replay predictor overrides the base predictor, indicating that the apparatus does not change/re-determine the direction for the later/second control transfer instruction from the stored direction which was previously determined).
Claim 16 is directed to a method performing the steps of the apparatus of claim 16 and is rejected for the same reasons.
Regarding claim 8, Pusdesris in view of Srinivasan teaches:
8. The apparatus of claim 1, wherein the fetch and execution of the one or more instructions is based on a mispredict redirect based on the recorded direction (Pusdesris col 7 lines 30-33 describes that subsequent instructions are executed on the basis of the prediction provided by the replay predictor and Fig. 1 shows that the replay predictor may supply its prediction to the fetch stage, this indicates that the recorded direction for the later/second control transfer instruction is used to redirect fetching to fetch and execute one or more instructions, and this redirect is a mispredict redirect since the recorded direction is used in response to a misprediction and re-execution of the later/second control transfer instruction, see col 9 lines 22-42).
Claim 18 is directed to a method performing the steps of the apparatus of claim 8 and is rejected for the same reasons.
Regarding claim 9, Pusdesris in view of Srinivasan teaches:
9. The apparatus of claim 1, wherein the control circuitry is also configured to store and use a recorded direction for a third control transfer instruction that was speculatively executed subsequent to a speculatively-executed incorrect load operation (since Pusdesris stores the predicted direction of later instructions (that were speculatively executed) in its storage circuitry for use in predicting the later instructions upon re-execution, see col 9 lines 50-60, any later instruction other than the second control transfer instruction (for example, a later instruction corresponding to another stream of instructions having control flow paths as shown in Fig. 2) is a third control transfer instruction; further, Srinivasan [0025] teaches that there may be instructions that write to registers on the non-convergent mispredicted path and Pusdesris col 8 lines 10-12 teaches load operations that may load data to registers, this indicates that the later instructions may be speculatively executed after a speculatively executed incorrect load operation in the mispredicted path).
Claim 19 is directed to a method performing the steps of the apparatus of claim 9 and is rejected for the same reasons.
Claims 2 and 12 are rejected under 35 U.S.C. 103 as being unpatentable over Pusdesris US 10,990,403 in view of Srinivasan US 2005/0138480 and Chauhan US 2020/0004542.
Regarding claim 2, Pusderis in view of Srinivasan teaches:
2. The apparatus of claim 1,
Pusdesris in view of Srinivasan does not teach:
wherein the control circuitry is further configured to:
determine the reconvergence point, including to:
store instruction address information corresponding to one or more executed instructions between control transfer instructions; and
during replay of instructions subsequent to misprediction of the first control transfer instruction, determine the reconvergence point based on a match between a current program counter and the stored instruction address information.
However, Chauhan teaches a branch instruction buffer that stores speculatively-fetched instructions to detect convergence, see [0054], where instructions that are fetched after a misprediction are compared to the IPs in the instruction buffer to determine whether there is an IP intersection/ convergence, and if so, the matching IP is recorded in a branch IP table, and when the confidence for the entry in the table reaches a threshold a flag is set to indicate the convergent branch, see [0066]-[0067] and Fig. 3.
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to modify Pusdesris in view of Srinivasan to detect reconvergence using the branch instruction buffer and branch IP table as taught by Chauhan. In this combination, the branch instruction buffer and branch IP table are part of the control circuitry, the branch instruction buffer stores instruction address information corresponding to executed instructions between control transfer instructions, and during replay of instructions the reconvergence point will be detected based on a match between a current program counter and one of the IPs/stored instruction address information in the branch instruction buffer. One of ordinary skill in the art would have been motivated to make this modification to more efficiently determine reconvergence points since comparing program counters to IPs in the branch instruction buffer only when there is a misprediction is more efficient than always comparing the program counter of each subsequent instruction to an alternate target address (as done in Srinivasan).
Claim 12 is directed to a method performing the steps of the apparatus of claim 2 and is rejected for the same reasons.
Claims 3 and 13 are rejected under 35 U.S.C. 103 as being unpatentable over Pusdesris US 10,990,403 in view of Srinivasan US 2005/0138480, Chauhan US 2020/0004542, and Hoyt US 5,903,751.
Regarding claim 3, Pusdesris in view of Srinivasan and Chauhan teaches:
3. The apparatus of claim 2, wherein the control circuitry is configured to store the determined reconvergence point in a reconvergence table in an entry (Chauhan Fig. 2B shows the branch IP table (which is a reconvergence table that is part of the control circuitry of the combination) storing a convergence IP (i.e., the determined reconvergence point) in an entry)
Pusdesris in view of Srinivasan and Chauhan does not teach:
the entry in the reconvergence table being tagged with a hashed program counter of the first control transfer instruction.
However, Hoyt teaches tagging entries in a branch target buffer cache (analogous to the branch IP table of Chauhan) with a hashed program counter of a branch instruction, see Fig. 7 and col 9 lines 8-17.
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to modify the entries of the reconvergence/branch IP table of Pusdesris in view of Srinivasan and Chauhan to be tagged with a hashed program counter of branch instructions as taught by Hoyt such that the combination would tag an entry in the reconvergence tagged with a hashed PC of the first control transfer instruction. One of ordinary skill in the art would have been motivated to make this modification to reduce the number of bits required for addressing entries in the table, which would simplify/reduce hardware requirements.
Claim 13 is directed to a method performing the steps of the apparatus of claim 3 and is rejected for the same reasons.
Claims 7 and 17 are rejected under 35 U.S.C. 103 as being unpatentable over Pusdesris US 10,990,403 in view of Srinivasan US 2005/0138480 and Yeh US 2005/0149698.
Regarding claim 7, Pusdesris in view of Srinivasan teaches:
7. The apparatus of claim 1, wherein the control circuitry is configured to copy the mask field to re-use storage circuitry in response to the misprediction.
Pusdesris in view of Srinivasan does not teach:
wherein the control circuitry is configured to copy the mask field to re-use storage circuitry in response to the misprediction.
However, Yeh teaches a replay scoreboard and an issue scoreboard, see [0047], where the contents of the replay scoreboard are copied to the issue scoreboard (i.e., re-use storage circuitry) in response to a replay due to branch misprediction, see [0076].
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to modify Pusdesris to keep a replay scoreboard and an issue scoreboard and to copy the contents (i.e., the flags taught by Srinivasan) from the replay scoreboard to the issue scoreboard in response to a misprediction as taught by Yeh. One of ordinary skill in the art would have been motivated to make this modification to track pending updates to registers (to properly handle dependencies between instructions), see Yeh [0046], while ensuring that updates to registers due to instructions that were issued but canceled are deleted, see Yeh [0076].
Claim 17 is directed to a method performing the steps of the apparatus of claim 7 and is rejected for the same reasons.
Claim 10 is rejected under 35 U.S.C. 103 as being unpatentable over Pusdesris US 10,990,403 in view of Srinivasan US 2005/0138480 and Reddy US 2016/0350116.
Regarding claim 10, Pusdesris in view of Srinivasan teaches:
10. The apparatus of claim 1, wherein the apparatus is a computing device (Pusdesris Fig. 1, 100) that further includes:
a processor that includes the processor front-end circuitry and the control circuitry (Fig. 1, components except for L2 112 and memory 112 are a processor that includes the front end and control circuitry);
Pusdesris in view of Srinivasan does not teach:
network interface circuitry.
However, Reddy teaches a computing device (Fig. 4) that includes network interface circuitry (Fig. 4, wireless controller 440).
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to modify the apparatus of Pusdesris to include the display and wireless controller of Reddy. One of ordinary skill in the art would have been motivated to combine the known elements of Reddy with the known apparatus of Pusdesris according to known methods as each element would perform the same function as it does separately and the results of the combination would have been predictable (MPEP 2143 A).
Allowable Subject Matter
Claim 14 is objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. While no prior art rejection is given for claim 4, this claim is currently rejected under 112(b) and is not allowable at the current point. The following is a statement of reasons for the indication of allowable subject matter/prior art considerations for claims 4 and 14:
The known prior art of record, taken alone or in combination, was not found to teach, in combination with other limitations in the claims, control circuitry that, for a portion of instructions decoded in a first cycle, processes a set of one or more mask field indicators as set to the first value regardless of their actual value, wherein the set of one or more mask field indicators correspond to targets of one or more other instructions decoded in the first cycle, as described in claims 4 and 14.
The closest prior art of record was found to be:
Srinivasan (US 2005/0138480), which teaches a scoreboard including flags which are set when their corresponding registers are written by instructions before a convergent point and cleared when their corresponding registers are written by instructions after the convergent point, see [0026]
Yeh (US 2005/0149698), which teaches a scoreboard that sets a bit to indicate a register is busy and clears the bit to indicate the register is not busy, see [0068]
Tran (US 5,185,868), which teaches decoder units that concurrently decode instructions, see Abstract
However, these references, taken alone or in combination, do not teach or suggest decoding instructions in a first cycle and processing mask field indicators as set to the first value regardless of their actual value for a portion of instructions decoded in the first cycle, wherein the set of one or more mask field indicators correspond to targets of other instructions decoded in the first cycle, as described in claims 4 and 14.
Conclusion
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/ANDREW CALDWELL/Supervisory Patent Examiner, Art Unit 2182
/KASIM ALLI/Examiner, Art Unit 2183
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