DETAILED ACTION
Status of the Claims
The response filed 7/9/26 is entered. Claims 1, 2, 4, 5, 13, 17, and 18 are elected. Claims 1-20 are pending.
Foreign Priority
Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55.
Information Disclosure Statements
The information disclosure statements (IDS) submitted on 4/29/25 and 4/10/26 are in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1, 2, 4, 17, and 18 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Gu, US-20170200412
In regards to claim 1, Gu discloses a pixel circuit (Fig. 45, 4500 pixel circuit) comprising: a driving transistor (Fig. 7 and 9, 706 driving transistor) configured to generate a current (Fig. 7 and 9, 706 driving transistor generates currents for light emitting elements D1 and D2); and a first light-emitting element (Fig. 7 and 9, D1 light emitting element) and a second light-emitting element (Fig. 7 and 9, D2 light emitting element) electrically connected in parallel or in series to the driving transistor (Fig. 7 and 9, 706 driving transistor), wherein the first light-emitting element (Fig. 7 and 9, D1 light emitting element) and the second light-emitting element (Fig. 7 and 9, D2 light emitting element) are alternately driven by the current from the driving transistor (Fig. 7 and 9, 706 driving transistor; Fig. 8; Par. 0104-0105 alternately driving the first group of subpixels and second group of subpixels using control signals EM1 and EM2).
In regards to claim 18, Gu discloses a display device (Par. 0002 display device) comprising: a display panel (Fig. 4, display panel) including a plurality of data lines (Fig. 4, data lines), a plurality of gate lines (Fig. 4, data lines), and a plurality of pixel circuits (Fig. 4, 400 array of subpixels; Fig. 45, 4500 pixel circuit); a data driving circuit (Fig. 4, 406 source writing driver) connected to the plurality of data lines (Fig. 4, data lines); and a gate driving circuit (Fig. 4, 404 gate scanning driver) connected to the plurality of gate lines (Fig. 4, data lines), wherein each of the plurality of pixel circuits (Fig. 45, 4500 pixel circuit) includes: a driving transistor (Fig. 7 and 9, 706 driving transistor) configured to generate a current (Fig. 7 and 9, 706 driving transistor generates currents for light emitting elements D1 and D2); and a first light-emitting element (Fig. 7 and 9, D1 light emitting element) and a second light-emitting element (Fig. 7 and 9, D2 light emitting element) electrically connected in parallel or in series to the driving transistor (Fig. 7 and 9, 706 driving transistor), and wherein the first light-emitting element (Fig. 7 and 9, D1 light emitting element) and the second light-emitting element (Fig. 7 and 9, D2 light emitting element) are alternately driven by the current from the driving transistor (Fig. 7 and 9, 706 driving transistor; Fig. 8; Par. 0104-0105 alternately driving the first group of subpixels and second group of subpixels using control signals EM1 and EM2).
In regards to claim 2, Gu discloses a first switch transistor (Fig. 7 and 9, 708-1 transistor); a second switch transistor (Fig. 7 and 9, 708-2 transistor); and a third switch transistor (Fig. 7 and 9, 704 transistor), wherein the first light-emitting element (Fig. 7 and 9, D1 light emitting element) and the second light-emitting element (Fig. 7 and 9, D2 light emitting element) are connected in parallel to the driving transistor (Fig. 7 and 9, 706 driving transistor) through the first switch transistor (Fig. 7 and 9, 708-1 transistor), the second switch transistor (Fig. 7 and 9, 708-2 transistor), and the third switch transistor (Fig. 7 and 9, 704 transistor), wherein the first switch transistor (Fig. 7 and 9, 708-1 transistor) is connected to the third switch transistor (Fig. 7 and 9, 704 transistor) and an anode electrode of the first light-emitting element (Fig. 7 and 9, D1 light emitting element), and is turned on in response to a first control signal (Fig. 7 and 9, EM1; Fig. 8; Par. 0104-0105 alternately driving the first group of subpixels and second group of subpixels using control signals EM1 and EM2) applied to a gate electrode of the first switch transistor (Fig. 7 and 9, 708-1 transistor), wherein the second switch transistor (Fig. 7 and 9, 708-2 transistor) is connected to the third switch transistor (Fig. 7 and 9, 704 transistor) and an anode electrode of the second light-emitting element (Fig. 7 and 9, D2 light emitting element), and is turned on in response to a second control signal (Fig. 7 and 9, EM2; Fig. 8; Par. 0104-0105 alternately driving the first group of subpixels and second group of subpixels using control signals EM1 and EM2) applied to a gate electrode of the second switch transistor (Fig. 7 and 9, 708-2 transistor), and wherein the third switch transistor (Fig. 7 and 9, 704 transistor) electrically connects the driving transistor (Fig. 7 and 9, 706 driving transistor) to the first switch transistor (Fig. 7 and 9, 708-1 transistor) or the second switch transistor (Fig. 7 and 9, 708-2 transistor) when turned on in response to a third control signal (Fig. 7 and 9, EMC; Fig. 8; Par. 0104-0105 alternately driving the first group of subpixels and second group of subpixels using control signals EM1 and EM2 when EMC is applied) applied to a gate electrode of the third switch transistor (Fig. 7 and 9, 704 transistor).
In regards to claim 4, Gu discloses the driving transistor (Fig. 7 and 9, 706 driving transistor) includes a first electrode connected to a first node (Fig. 7 and 9, 706 driving transistor first node), a gate electrode connected to a second node (Fig. 7 and 9, 706 driving transistor second node), and a second electrode connected to a third node (Fig. 7 and 9, 706 driving transistor third node).
In regards to claim 17, Gu discloses voltages of the first control signal (Fig. 7 and 9, EM1) and the second control signal are alternately inverted in a periodicity of one frame period (Fig. 7 and 9, 706 driving transistor; Fig. 8; Par. 0104-0105 EM1 and EM2 alternately inverted in a periodicity of one frame period).
Allowable Subject Matter
Claims 5 and 13 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
In regards to claim 5, the prior art of record fails to disclose, teach or fairly suggest to one of ordinary skill in the art, in conjunction with all the other claimed limitations: a pixel circuit and specifically including “a fourth switch transistor including a first electrode connected to a data line to which a data voltage is applied, a gate electrode to which a first scan signal is applied, and a second electrode connected to a fifth node; a fifth switch transistor including a first electrode connected to the second node, a gate electrode to which the first scan signal is applied, and a second electrode connected to the third node; a sixth switch transistor including a first electrode connected to the fifth node, a gate electrode to which the emission signal is applied, and a second electrode to which a reference voltage is applied; a seventh switch transistor including a first electrode connected to the second node, a gate electrode to which a second scan signal is applied, and a second electrode to which the reference voltage is applied; an eighth switch transistor including a first electrode connected to the data line, a gate electrode to which the second scan signal is applied, and a second electrode connected to the fifth node; and a capacitor connected to the second node and the fifth node, wherein the first light-emitting element includes an anode electrode connected to the second electrode of the first switch transistor and a cathode electrode to which a ground voltage is applied, and wherein the second light-emitting element includes an anode electrode connected to the second electrode of the second switch transistor and a cathode electrode to which the ground voltage is applied.”
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to CORY A ALMEIDA whose telephone number is (571)270-3143. The examiner can normally be reached M-Th 9AM-730PM.
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/CORY A ALMEIDA/Primary Examiner, Art Unit 2628 7/24/26
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