Prosecution Insights
Last updated: August 16, 2026
Application No. 19/193,555

FAILSAFE BACKUP MODE IN AN IMPLANTABLE MEDICAL DEVICE

Non-Final OA §112
Filed
Apr 29, 2025
Priority
May 23, 2024 — provisional 63/651,333
Examiner
KUDIRKA, JOSEPH R
Art Unit
Tech Center
Assignee
Pacesetter Inc.
OA Round
1 (Non-Final)
91%
Grant Probability
Favorable
1-2
OA Rounds
11m
Est. Remaining
99%
With Interview

Examiner Intelligence

Grants 91% — above average
91%
Career Allowance Rate
565 granted / 622 resolved
+30.8% vs TC avg
Moderate +10% lift
Without
With
+9.7%
Interview Lift
resolved cases with interview
Typical timeline
2y 2m
Avg Prosecution
15 currently pending
Career history
634
Total Applications
across all art units

Statute-Specific Performance

§101
18.8%
-21.2% vs TC avg
§103
28.8%
-11.2% vs TC avg
§102
24.1%
-15.9% vs TC avg
§112
25.2%
-14.8% vs TC avg
Black line = Tech Center average estimate • Based on career data from 622 resolved cases

Office Action

§112
DETAILED ACTION The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Information Disclosure Statement The Information Disclosure Statements (IDS) submitted on 04/29/2025 and 11/05/2025 are in compliance with the provisions of 37 CFR 1.97, 37 CFR 1.98, and MPEP § 609. They have been placed in the application file, and the information referred to therein has been considered as to the merits. Claim Objections Claims 1, 6, and 18 are objected to because of the following informalities: Claim 1: Change to “…wherein while the processor operates the IMD in accordance with the backup mode, the processor stores and accesses variables in one of the RAM blocks; and…” (page 1). Claim 6: Change to “…after the device reset operation is performed that results in the counter being incremented, the processor and/or further circuitry of the IMD is configured to perform a memory test on the one of the RAM blocks selected using the counter; and…” (page 2). Claim 18: Change to “…a processor that executes the backup mode firmware to operate the IMD in accordance with a backup mode, wherein when the processor operates the IMD in the backup mode, the processor stores and accesses variables in one of the RAM blocks; and…” (page 4). Appropriate correction is required. Claim Rejections - 35 USC § 112 The following is a quotation of 35 U.S.C. 112(b): (b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention. The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph: The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention. Claims 1-17 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention. Claim 1 recites the limitation "should cause" in page 1. The term “should” is indefinite because it fails to point out what is included or excluded by the claim language. When a malfunction is detected, does the claimed IMD operate in accordance with the backup mode, or does it not? Because Claims 2-10 depend upon Claim 1, Claims 2-10 are additionally rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite. Claim 11 recites the limitation "should cause" in page 3. The term “should” is indefinite because it fails to point out what is included or excluded by the claim language. When a malfunction is detected, does the claimed IMD operate in accordance with the backup mode, or does it not? Because Claims 12-17 depend upon Claim 11, Claims 12-17 are additionally rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite. Allowable Subject Matter Claims 1-17 would be allowable if rewritten or amended to overcome the rejection(s) under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), 2nd paragraph, set forth in this Office action. Claims 18-20 are allowed. The following is a statement of reasons for the indication of allowable subject matter: The elements of independent Claims 1, 11, and 18 were neither found through a search of the prior art nor considered obvious by the Examiner. In particular, the prior art of record does not teach or suggest, in combination with the remaining limitations and in the context of their claims as a whole: Claim 1: “…a counter that is selectively incremented and used to select which one of the RAM blocks the variables are stored within while the processor executes the backup mode firmware to operate the IMD in accordance with the backup mode.” Claim 11: “…while the processor is executing the backup mode firmware and thereby operating the IMD in accordance with the backup mode, the processor storing and accessing variables in one of the RAM blocks identified using the counter following the incrementing of the counter.” Claim 18: “…a counter that is selectively incremented after a reset operation and used to select which one of the RAM blocks the variables are stored within while the processor operates the IMD in the backup mode.” From a search of the prior art, one reference was found and considered by the Examiner to be the most-related prior art with regards to the claimed invention of the instant application: Nair et al. (U.S. Patent No. US 9,092,552 B2), hereinafter “Nair.” Nair: Fig. 1 and Nair: col. 4, lines 26-59 teach that a system monitor includes or has access to a plurality of memory locations. Although the memory locations are illustrated in FIG. 1 as being part of the system monitor, in other embodiments, the memory locations may be separate from the system monitor. For example, the memory locations may be part of a system memory. In other embodiments, the memory locations are dedicated registers within the system monitor or within other circuitry of the IMD. One or more of the memory locations may be associated with a corresponding monitored module. For example, a module of the IMD that is associated with a particular memory location may provide an enable signal to the memory location (e.g., to enable a particular register). During a monitoring period, a monitored module corresponding to a particular memory location may provide the enable signal to the memory location and may set a value at the particular memory location. At an expiration of the monitoring period, the system monitor may determine whether each of the memory locations (or each enabled memory location) has a first value (e.g., a one (1)) indicating that the corresponding monitored module is functioning properly. If each of the memory locations (or each enabled memory location) has the first value indicating that the corresponding monitored module is functioning properly, the system monitor may reset the values at the memory locations to a second value (e.g., zero (0)) and may start a new monitoring period (e.g., reset a timer or counter). The second value may indicate an error condition. Thus, when a monitored module fails to store the first value at its corresponding memory location during the monitoring period, the corresponding memory location may store the second value at the expiration of the monitoring period, indicating an error condition at the monitored module. Although conceptually similar to the claimed invention of the instant application, Nair does not teach: …a counter that is selectively incremented and used to select which one of the RAM blocks the variables are stored within while the processor executes the backup mode firmware to operate the IMD in accordance with the backup mode; …while the processor is executing the backup mode firmware and thereby operating the IMD in accordance with the backup mode, the processor storing and accessing variables in one of the RAM blocks identified using the counter following the incrementing of the counter; and/or …a counter that is selectively incremented after a reset operation and used to select which one of the RAM blocks the variables are stored within while the processor operates the IMD in the backup mode. Conclusion The prior art made of record and not relied upon is considered pertinent to applicant's disclosure: Nair (see above). Huelskamp et al. (U.S. Patent No. US 9,320,883 B2); teaching, per Fig. 3; col. 3, lines 53-67; and col. 4, lines 1-7 a flow diagram of an example of an operating an IMD to perform auto-configuration of the device. A reset signal is generated in the IMD. The reset signal may be generated in response to a detected error or in response to the power supply rising to a specified voltage (e.g. a device startup). Normal control flow of the IMD is disabled in response to the generated reset signal. This may involve disabling a portion of the electronics unit, such as by maintaining the portion in a reset state, or by disabling clock signals provided to the portion of the electronics unit. Auto-configuration data is transferred from a configuration portion of non-volatile memory of the IMD to one or more configuration registers when the normal control flow of the IMD is disabled. In certain variations, the configuration registers can be a portion of non-volatile memory. Writing values into the configuration registers configures the IMD for the safety mode operation. Writing different values enables and disables different features. Thus, the auto-configuration can be made flexible by changing the auto-configuration data. Using non-volatile memory for the configuration data reduces the number of errors. This reads similarly to the claimed “backup mode” found in at least the independent claims of the instant application. Any inquiry concerning this communication or earlier communications from the examiner should be directed to JOSEPH KUDIRKA whose telephone number is (571)270-7126. The examiner can normally be reached M-F 7:30am - 5pm ET. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Ashish Thomas can be reached at (571) 272-0631. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /JOSEPH R KUDIRKA/Primary Patent Examiner, Art Unit 2114
Read full office action

Prosecution Timeline

Apr 29, 2025
Application Filed
Aug 04, 2026
Non-Final Rejection mailed — §112 (current)

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Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

1-2
Expected OA Rounds
91%
Grant Probability
99%
With Interview (+9.7%)
2y 2m (~11m remaining)
Median Time to Grant
Low
PTA Risk
Based on 622 resolved cases by this examiner. Grant probability derived from career allowance rate.

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