DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Arguments
Applicant’s arguments with respect to claim(s) 21 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 21-23, 27 and 30 are rejected under 35 U.S.C. 103 as being unpatentable over Moon et al. US 2020/0295310 in view of Wang et al. US 2020/0083309.
As to claim 21, Moon teaches a device (a device, see title, abstract and Fig 9),
a substrate (100, ¶89);
a first thin-film transistor in a first region (at least one transistor T1 in the display area DA has a first region P1, ¶83)
a second thin-film transistor in a second region (at least one transistor T1 in the display area DA has a second region P3, ¶83, figure 9)
a storage capacitor in a third region, the third region being between the first region and the second region (a storage capacitor Cst in a third region P2, the third region P2 being between the first region P1 and the second region P3, ¶ 84, figure 9);
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a protective layer (220, ¶163) on the first thin-film transistor (the at least on transistor T1), the storage capacitor (Cst), and the second thin-film transistor (the at least one transistor T1);
a bank layer (a pixel defining layer PVX, ¶126) on the protective layer (220), at least a portion of the bank layer (the pixel defining layer PVX) is in the third region (P3);
a touch sensor layer (700, ¶174 ) on the protective layer (220), at least a portion of the touch sensor layer (700) is in the third region (P2).
Moon does not teach wherein the first blocking layer and second blocking layer are disposed on different layers such that the second blocking layer is further from the substrate than the first blocking layer, wherein the first blocking layer and second blocking layer do not overlap each other.
Figure 2D of Wang teaches the first shielding layer 120 and second shielding layer 130d are disposed on multi-layer structure/different layers such that the second shielding layer 130d is further from the substrate 110 than the first shielding layer 120, the first shielding layer 120 and second shielding layer 130d do not overlap each other. See at least Wang ¶10 and ¶83.
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention (AIA ), to implement the first shielding layer 120 and second shielding layer 130d are disposed on multi-layer structure such that the second shielding layer 130d is further from the substrate 110 than the first shielding layer 120, the first shielding layer 120 and second shielding layer 130d do not overlap each other, as Wang teaches to, modify the display device of Moon. The motivation for doing so would have been to improve the characteristics of the transistor, and improve the high quality of the image being displayed. Wang ¶4-¶6.
As to claim 22, Wang modified teaches the device of claim 21 wherein the substrate is a flexible substrate and a distance from the first blocking layer to the substrate is smaller than a distance from the second blocking layer to the substrate. (Wang teaches a flexible substrate. See ¶137 and ¶83).
As to claim 23, Moon teaches the device of claim 21 wherein the touch sensor layer is further from the substrate than the bank layer. (Fig 9 of Moon shows the touch layer 700 is further from the substrate 100 than the pixel defining layer 119).
As to claim 27, Wang teaches the device of claim 21 the first thin-film transistor includes a silicon semiconductor layer and the second thin-film transistor includes an oxide semiconductor layer, the first blocking layer is aligned with the first thin-film transistor and the second blocking layer is aligned with the second thin-film transistor. (Wang ¶8).
As to claim 30, Wang teaches the device of claim 21 wherein a first electrode (41) of the storage capacitor (Cst), a first gate (22) of the first thin-film transistor (M1), and a second gate (32) of a second thin-film transistor (M2) are formed on a same layer. (See Wang Figure 2D, ¶15).
Claim 24 is rejected under 35 U.S.C. 103 as being unpatentable over Moon and Wang as applied to claim 21 above, and further in view of Choi et al. 2021/0399059 herein after Choi '059.
As to claim 24, Moon and Wang fail to teach the touch sensor layer includes at least a portion in the second region and overlaps the second thin-film transistor.
Choi '059 teaches the touch sensor layer including the sensing electrode 410 includes at least a portion in the second region A2 and overlaps the thin-film transistor TFT of pixel circuit PC. See Choi '059 ¶ 113, ¶133 and Fig 17.
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention (AIA ), to implement the sensing electrode 410 includes at least a portion in the second region A2 and overlaps the thin-film transistor TFT, as Choi '059 teaches, to modify the device of Moon and Wang. The motivation for doing so would improve faster response time of the touch point on the touchscreen, while increasing measurement time for high accuracy.
Claim(s) 25-26 are rejected under 35 U.S.C. 103 as being unpatentable over Moon and Wang as applied to claim 21 above, and further in view of Ahn et al. US 2016/0172633.
As to claim 25, Moon and Wang fail to teach a portion of the second blocking layer is in the third region and another portion of the second blocking layer is in the second region.
Ahn teaches a portion of the second blocking member 120 is in the third region (pixel region I ) and another portion of the second blocking layer 120 is in the second region (a transparent region II). See Ahn ¶10-¶11, ¶43-¶44 and Fig 3.
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention (AIA ), to implement a portion of the second blocking member 120 is in the third region (pixel region I ) and another portion of the second blocking layer 120 is in the second region (a transparent region II), as Ahn teaches, to modify the device of Moon and Wang. The motivation for doing so would prevent light interference with the display light. Ahn ¶ 6.
As to claim 26, Wang modified teaches the device of claim 25 wherein the portion of the second blocking layer that is in the third region is coupled to a source/drain electrode of the second thin-film transistor. (Wang teaches the shielding layer 120/130a is electrically connected to the source/drain electrode of the transistor. See Wang at least ¶140 and Fig 10).
Claim 28 is rejected under 35 U.S.C. 103 as being unpatentable over Moon and Wang as applied to claim 21 above, and further in view of Zhou et al. US 2021/0408095.
As to claim 28, Moon and Wang fail to teach the device of claim 27 wherein a source/drain region of the first thin-film transistor is closer to the substrate than a source/drain region of the second thin-film transistor.
Zhou teaches a source/drain region of the first thin-film transistor 10 is closer to the substrate 100 than a source/drain region of the second thin-film transistor 20. See Zhou ¶ 70, and Fig 3.
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention (AIA ), to implement a source/drain region of the first thin-film transistor 10 is closer to the substrate 100 than a source/drain region of the second thin-film transistor 20, as Zhao teaches, to modify the device of Moon and Wang. The motivation for doing so would improve uniformity and stability of a control unit composed of a first transistor and a second transistor. Zhao ¶5.
Claim 29 is rejected under 35 U.S.C. 103 as being unpatentable over Moon and Wang as applied to claim 21 above, and further in view of Chen et al. US 2019/0171050.
As to claim 29, Moon and Wang do not teach buffer layer between the first blocking layer and the second blocking layer.
Chen teaches a buffer layer 73 between the first blocking layer 71 and the second blocking layer 72. See Chen ¶37 and Fig 4.
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention (AIA ), to implement a buffer layer 73 between the first blocking layer 71 and the second blocking layer 72, as Chen teaches, to modify the device of Moon and Wang. The motivation for doing so would prevent light interference with the display light. Chen ¶5.
Allowable Subject Matter
Claims 1-20 are allowed.
Regarding claim 1, None of prior art of record teaches:
1. A light-emitting display apparatus, comprising:
a flexible substrate including a display area and a non-display area, the display area including:
a first thin-film transistor in a first region of the flexible substrate, the first thin-film transistor including a first gate electrode, a first source electrode, and a first drain electrode;
a second thin-film transistor in a second region of the flexible substrate, the second thin-film transistor including a second gate electrode, a second source electrode, and a second drain electrode;
a storage capacitor in a third region of the flexible substrate;
a first planarization layer on the first thin-film transistor and second thin-film transistor;
a second planarization layer on the first thin-film transistor and second thin-film transistor;
a bank layer on the second planarization layer;
a light-emitting element layer on the bank layer;
a connection electrode between the first planarization layer and the second planarization layer, the connection electrode electrically connected to the second thin-film transistor and the light-emitting element layer;
a protective layer on the light-emitting element layer; and
a touch sensor layer on the protective layer, the storage capacitor overlaps the bank layer and the touch sensor layer;
a first blocking layer below the first thin-film transistor; and
a second blocking layer below the second thin-film transistor.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to KEVIN M NGUYEN whose telephone number is (571)272-7697, and email is kevin.nguyen2@uspto.gov. The examiner can normally be reached M-T 8am-5pm Eastern Time.
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KEVIN M NGUYEN
Examiner, Art Unit 2628
/Kevin M Nguyen/Primary Examiner, Art Unit 2628
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