DETAILED ACTION
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim 1, 2-8, 14, and 16, is/are rejected under 35 U.S.C. 103 as being unpatentable over to Lim (US 2020/0349064) – previously sited and Olarig (US 11,741,040).
As per claim 1, Lim teaches an
an interface configured to transfer data between a host and the SSD device;
a first port linking up with a first host using a first path ([0106], when the dual-port is selected in the PCIe type, the 5th, 7th, 11th, and 13th connection terminals 5, 7, 11, and 13 may form a first lane of a first port of the dual port. Whereas the 17th, 19th, 23rd, and 25th connection terminals 17, 19, 23, and 25 may form a first lane of a 0-th port of the dual-port); a second port linking up with the host through a second path ([0106], the 29th, 31st, 35th, and 37th connection terminals 29, 31, 35, and 37 may form a first lane of a 0-th port of the dual-port. Whereas, the 41st, 43rd, 47th, and 49th connection terminals 41, 43, 47, and 49 may form a 0-th lane of the 0th port of the dual port); and a port mode controller configured to change an operating mode from a dual port mode to a single port mode when a path failure occurs in the second path or the second port. ([0112], the controller, 120 may select the single port when the voltage of the third detection node DN3 is maintained. Note Fig. 11, wherein the controller, 120 may configure the connection terminals of the connector, 102 to correspond to the single port, [0107], note the 48th connection terminal 48 that may be used to receive or transmit an additional reset signal PERST #1. The additional reset signal PERST #1 may be used to dynamically change the dual-port to the single port or vice versa).
Lim does not expressly teach that the PCIe device is SSD device. Nonetheless, Lim’s discloses that storage device may store data on a magnetic disk (e.g., a hard disk drive (HDD)) or store data on a semiconductor memory, in particular, a nonvolatile memory (e.g., a solid-state drive (SSD) or a memory card). However, regarding to the use of a SSD device when reading the preamble in the context of the entire claim, the recitation ‘SSD’ is not limiting because the body of the claim describes a complete invention and the language recited solely in the preamble does not provide any distinct definition of any of the claimed invention’s limitations. Thus, the preamble of the claim(s) is not considered a limitation and is of no significance to claim construction. See Pitney Bowes, Inc. v. Hewlett-Packard Co., 182 F.3d 1298, 1305, 51 USPQ2d 1161, 1165 (Fed. Cir. 1999). See MPEP § 2111.02.
Therein, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention that Lim’s non-volatile memory storage device could be implemented using a SSD because utilizing a SSD is well known in the art at the time the invention was made, therein, implementing a SSD bus interface in Lim would have been obvious to one skilled in the art. "Under the correct analysis, any need or problem known in the field of endeavor at the time of invention and addressed by the patent can provide a reason for combining the elements in the manner claimed." Id. 11742.
In another analogous art, Olarig discloses dual-mode SSD that is connected (with FPGA, Fig. 1) to an external host device via a first interface or a second interface. The SSD is configured based on a stated of a signal pin (RFU Pin, step 402, Fig. 4) to operate in a first mode or a second mode. Specifically, when the state of the signal is HIGH the SSD operates in NVMe-oF mode (404, Fig.4) and when the state of the signal is LOW then each of a NVMe mode (416, Fig. 4) and the if the dual port pin is HIGH NVMe mode can operating in a single port, respectfully. Therein, wherein the port mode controller (SSD device 200 resets at 401, Fig.4) controls the second port (see status of ‘Check for RFU pin, step 402, Fig. 4) to reset the second link in a state in which the first port transmits or receives data through the first link. (col. 17, lines 66-col. 19, lines 1-39)
Before the effective filing date of the claim invention, it would have been obvious to a person of ordinary skill in the art to combine the elements of Lim to incorporate the teaching of Olarig to provide a storage device having a port mode controller that communicates a reset in which a second port (mode) is now placed into another state whereby allowing for a first port (mode) to now transmits or receives a first link. Doing so would improve the device performance of Lim by having a method to further determine a status of a dual port pin of the host device in order to determine if the storage device will be operating in a single port mode or a dual port mode. (Olarig, col. 7-22)
As per claim 2, Lim-Olarig discloses further comprising: a second interface configured to transfer data between a controller and a memory device, wherein the controller includes the interface, the first port, and the second port. Olarig discloses wherein port mode controller (SSD device 200 resets at 401, Fig.4) controls the second port (see status of ‘Check for RFU pin, step 402, Fig. 4) to reset the second link in a state in which the first port transmits or receives data through the first link. (col. 17, lines 66-col. 19, lines 1-39)
As per claim 14 and 16, Olarig’040 discloses dual-mode SSD that is connected (with FPGA, Fig. 1) to an external host device via a first interface or a second interface wherein a type of port controller that controls the second port in which the path failure occurs to reset a link. The SSD is configured based on a stated of a signal pin (RFU Pin, step 402, Fig. 4) to operate in a first mode or a second mode. Specifically, when the state of the signal is HIGH the SSD operates in NVMe-oF mode (404, Fig.4) and when the state of the signal is LOW then each of a NVMe mode (416, Fig. 4) and the if the dual port pin is HIGH NVMe mode can operating in a single port, respectfully. Therein, wherein the port mode controller (SSD device 200 resets at 401, Fig.4) controls the second port (see status of ‘Check for RFU pin, step 402, Fig. 4) to reset the second link in a state in which the first port transmits or receives data through the first link. (col. 17, lines 66-col. 19, lines 1-39)
As per claim 3-8, see the rejection for claims 1, 2, and 14.
Claims 9-13, 15, and 17-24 is/are rejected under 35 U.S.C. 103 as being unpatentable over to Lim (US 2020/0349064) – previously sited and Olarig (US 11,741,040) and in further view Wong (US 2006/0090014) – previously sited.
As per claim 9, 17 and 24, Lim-Olarig does not expressly teach wherein the first port comprises a first link training module changing a status of the first link, and wherein the second port comprises a second link training module changing a status of the second link. Nonetheless, Wong discloses link training and status state machine 500 changing that handles link training on ports (Note Wong [0056-0057]). It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to combine the storage device of Lim-Olarig with the teachings of Wong’s system of a first link training module changing a status of the first link, and wherein the second port comprises a second link training module changing a status of the second link. By allowing of the alternating and resetting/changing of the modules for each port would provide an optimized way for Lim-Olarig to handle lane reconfiguration. (Wong, [0056-0057])
As per claim 10, Lim-Olarig in view of Wong wherein the first link training operation and the second link training operation operate independently. Wong discloses link training and status state machine 500 changing that handles link training on ports (Note Wong [0056-0057]). It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to combine the storage device of Lim-Olarig with the teachings of Wong’s system of a first link training module changing a status of the first link, and wherein the second port comprises a second link training module changing a status of the second link. By allowing of the alternating and resetting/changing of the modules for each port would provide an optimized way for Lim-Olarig to handle lane reconfiguration. (Wong, [0056-0057])
As per claim 11, Lim-Olarig in view of Wong wherein the first link training operation and the second link training operation operate substantially at the same time. Wong discloses link training and status state machine 500 changing that handles link training on ports (Note Wong [0056-0057]). It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to combine the storage device of Lim-Olarig with the teachings of Wong’s system of a first link training module changing a status of the first link, and wherein the second port comprises a second link training module changing a status of the second link. By allowing of the alternating and resetting/changing of the modules for each port would provide an optimized way for Lim-Olarig to handle lane reconfiguration. (Wong, [0056-0057])
As per claim 12 and 15, Lim-Olarig in view of Wong wherein the first link training operation starts before the second link training operation starts. Wong discloses link training and status state machine 500 changing that handles link training on ports (Note Wong [0056-0057]). Wong teaches that by allowing of the alternating and resetting/changing of the modules for each port would provide an optimized way for Lim-Olarig to handle lane reconfiguration. (Wong, [0056-0057])
As per claim 18 and 22, Lim-Olarig in view of Wong wherein the port mode controller controls the second link training module to reset the second link when the first link is linked up, and controls the first link training module to extend a lane width of the first link when the second link reset is completed (Lim, note [0107], the 48th connection terminal 48 may be used to receive or transmit an additional reset signal PERST #1. The additional reset signal PERST #1 may be used to dynamically change the dual-port to the single port or vice versa. Further, note Lim [0105], whereas when the single port is selected in the PCle communication type, the 22nd, 24th, and 46th connection terminals 22, 24, and 46 may be not connected N/C or may not be used. The 5th, 7th, 11th, and 13th connection terminals 5, 7, 11, and 13 may form a third lane of the single port. The 17th, 19th, 23rd, and 25th connection terminals 17, 19, 23, and 25 may form a second lane of the single port. The 29th, 31st, 35th, and 37th connection terminals 29, 31, 35, and 37 may form a first lane of the single port. The 41st, 43rd, 47th, and 49th connection terminals 41, 43, 47, and 49 may form a0-th lane of the single port. The 53rd and 55th connection terminals 53 and 55 may be used to receive or transmit reference clocks REFCLKn and REFCLKp of the single port, respectively. That is, the storage device 100 may form a single port 4- lane with the connection terminals of the connector 102).
As per claim 19, Lim-Olarig in view of Wong teaches wherein the first link training module performs an up-configure operation to increase the lane width of the first link in response to the control of the port mode controller. (Note Lim [0105], whereas when the single port is selected in the PCle communication type, the 22nd, 24th, and 46th connection terminals 22, 24, and 46 may be not connected N/C or may not be used. The 5th, 7th, 11th, and 13th connection terminals 5, 7, 11, and 13 may form a third lane of the single port. The 17th, 19th, 23rd, and 25th connection terminals 17, 19, 23, and 25 may form a second lane of the single port. The 29th, 31st, 35th, and 37th connection terminals 29, 31, 35, and 37 may form a first lane of the single port. The 41st, 43rd, 47th, and 49th connection terminals 41, 43, 47, and 49 may form a0-th lane of the single port. The 53rd and 55th connection terminals 53 and 55 may be used to receive or transmit reference clocks REFCLKn and REFCLKp of the single port, respectively)
As per claim 20, Lim-Olarig in view of Wong teaches wherein the first link training module changes the status of the first link sequentially to an L0 state, a recovery state, a configuration state, and the L0 state. (Note Wong: Fig. 5, [0062-0063], the state machine transitions to a RECOVERY state 510 from L0. During RECOVERY 510, the ports attempt to perform retraining of the link. If CONFIG 508 is successful, then the state machine transitions to L0 for normal operation)
As per claim 21, Lim-Olarig in view of Wong teaches wherein each of the first port and the second port comprises a Peripheral Component Interconnect Express (PCIe) interface (Lim, [0059], note that the communication type of storage device, 100 is PCIe, further the controller, 120 and external host may use the connection terminals of the connector, 102 according to the PCIe standard) including a transaction layer, a data link layer, and a physical layer operating in a status of a link according to PCIe standards in response to the respective control of each of the first link training module and the second link training module. (Wong discloses a transaction layer, a data link layer, and a physical layer operating in a status of a link according to PCle standards in response to the respective control of each of the first link training module and the second link training module ([0056-0061], transaction layer, a data link layer, and a physical layer and training module).
As per claim 23, Lim-Olarig’040-Wong and in further view of Olarig’157 teaches operating in a single port mode using the first port when the lane increase operation is completed (Lim, [0112], The controller 120 may select the single port when the voltage of the third detection node DN3is maintained. As described with reference to FIG. 11, the controller 120 may configure the connection terminals of the connector 102 to correspond to the single port)
RELEVENT ART CITED BY THE EXAMINER
The following prior art made of record and relied upon is citied to establish the level of skill in the applicant's art and those arts considered reasonably pertinent to applicant's disclosure. See MPEP 707.05(c). 3. The following references Jeon et al., (US 12,536,116) teaches peripheral Component Interconnect Express (PCIe) interface or USB interface dual connections with first and second host controllers. (entire document)
Conclusion
The examiner requests, in response to this office action, support be shown for language added to any original claims on amendment and any new claims. That is, indicate support for newly added claim language by specifically pointing to page(s) and line number(s) in the specification and/or drawing figure(s). This will assist the examiner in prosecuting the application. When responding to this office action, applicant is advised to clearly point out the patentable novelty which he or she thinks the claims present, in view of the state of art disclosed by the references cited or the objections made. He or she must also show how the amendments avoid such references or objections. See 37 C.F.R.I .Hi(c). In amending in reply to a rejection of claims in an application or patent under reexamination, the applicant or patent owner must clearly point out the patentable novelty which he or she thinks the claims present in view the state of the art disclosed by the references cited or the objections made. The applicant or patent owner must also show how the amendments avoid such references or objections. Any inquiry concerning this communication or earlier communications from the examiner should be directed to TAMMARA R PEYTON whose telephone number is (571)272-4157. The examiner can normally be reached on 9am-5pm, EST M-F. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Henry Tsai can be reached on 571-272-4176. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of an application may be obtained from the Patent Application Information Retrieval (PAIR) system. Status information for published applications may be obtained from either Private PAIR or Public PAIR. Status information for unpublished applications is available through Private PAIR only. For more information about the PAIR system, see http://pair-direct.uspto.gov. Should you have questions on access to the Private PAIR system, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative or access to the automated information system, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/TAMMARA R PEYTON/Primary Examiner, Art Unit 2184 June 27, 2025
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