Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
This action is in response to the application filed on 04/29/2025.
Information Disclosure Statement
The information disclosure statements (IDS) submitted on 04/29/2025 and 08/31/2026 are in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statements are being considered by the examiner.
Drawings
The drawings are objected to as failing to comply with 37 CFR 1.84(p)(5) because they do not include the following reference signs mentioned in the description: 415 (see paragraphs [0022]-[0024] and [0036]) and A (see paragraphs [0025] and [0026]).
Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. The figure or figure number of an amended drawing should not be labeled as “amended.” If a drawing figure is to be canceled, the appropriate figure must be removed from the replacement sheet, and where necessary, the remaining figures must be renumbered and appropriate changes made to the brief description of the several views of the drawings for consistency. Additional replacement sheets may be necessary to show the renumbering of the remaining figures. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Specification
The abstract of the disclosure is objected to because of the following informalities:
In the seventh sentence, “The counter is can provide” appears that it should read as “The counter can provide”, because of a grammatical error;
in the eighth sentence, “A drive strength has a drive circuit input” appears that it should read as “A drive circuit has a drive circuit input”, because of a typographical error (the ninth and tenth sentences refer to the drive circuit input and the drive circuit).
A corrected abstract of the disclosure is required and must be presented on a separate sheet, apart from any other text. See MPEP § 608.01(b).
The disclosure is objected to because of the following informalities:
In paragraph [0001], “U.S. Nonprovisional Application No. 17/697,008 filed March 17, 2022” appears that it should read as “U.S. Nonprovisional Application No. 17/697,008 filed March 17, 2022, now U.S. Patent No. 12,323,057”, because the status of the parent application should be updated;
in paragraph [0003], “the high low side transistor” appears that it should read as “the high and low side transistors”, because of a grammatical error;
in paragraph [0009], “An inductor L1 is coupled to the switch” appears that it should read as “An inductor L1 is coupled to the switch node 110”, because the inductor L1 is coupled to the switch node 110 (see Fig. 1);
in paragraph [0010], “Lp-ls” appears that it should read as “Lp_ls”, because of an inconsistency with Fig. 1 and paragraph [0016];
in paragraph [0012], “at a application-specific frequency” appears that it should read as “at an application-specific frequency”, because of a grammatical error;
in paragraph [0012], “illustrating of a portion” appears that it should read as “illustrating a portion”, because of a grammatical error;
in paragraph [0013], “following the following edge 202” appears that it should read as “following the falling edge 202”, because edge 202 is the falling edge of LS_EN (see paragraph [0012]);
in paragraph [0013], “for the HS to fully turn on” appears that it should read as “for the HS transistor to fully turn on”, because of a missing word;
in paragraph [0013], “Waveforms 211 and 214 illustrate” appears that it should read as “Waveforms 211 and 213 illustrate”, because waveform 213 is the current I_hs, while waveform 214 is the switch node voltage Vsw (see Fig. 2);
in paragraph [0020], “the rate change of I_hs” appears that it should read as “the rate of change of I_hs”;
in paragraph [0020], “the voltage on drain of the HS transistor” appears that it should read as “the voltage on the drain of the HS transistor”;
in paragraph [0020], “exceeds the threshold. which indicates” appears that it should read as “exceeds the threshold, which indicates”;
in paragraphs [0023] and [0024], “programmable driver strength circuit 408” appears that it should read as “programmable drive strength circuit 408”, because of an inconsistency with the programmable drive strength circuit 408 recited in paragraphs [0021] and [0022];
in paragraph [0024], “the OR gate 414” appears that it should read as “the OR gate 412”, because of a typographical error (see paragraph [0022] and Fig. 4);
in paragraph [0025], “The combination of C1 and R1 form” appears that it should read as “The combination of C1 and R1 forms”;
in paragraph [0026], “the positive input comparators” appears that it should read as “the positive inputs of the comparators”;
in paragraph [0026], “the drain of the HS decreases” appears that it should read as “the drain of the HS transistor decreases”;
in paragraph [0031], “cause the Q output” appears that it should read as “causes the Q output”;
in paragraph [0031], “to be reset In some embodiments” appears that it should read as “to be reset. In some embodiments”;
in paragraph [0035], each occurrence of “the PFETS 451-454” appears that it should read as “the PFETs 451-454”;
in paragraph [0036], “(through OR gate 412 and NAND gate 414)” appears that it should read as “(through OR gate 412)”, because Fig. 4 does not show a NAND gate 414, and signal 415 is the output of the OR gate 412 (see paragraph [0022]);
in paragraph [0037], “multiplexer 466.The output 467” appears that it should read as “multiplexer 466. The output 467”, because of a missing space;
in paragraph [0038], “The drive delay compensation circuit 462” appears that it should read as “The driver delay compensation circuit 462”, because of an inconsistency with the driver delay compensation circuit 462 recited elsewhere in the paragraph;
in paragraph [0042], “the multiplexer 366” appears that it should read as “the multiplexer 466”, because of a typographical error (see Fig. 4);
in paragraph [0047], a closing quotation mark should be added after the term “pin”;
in paragraph [0050], “current flowing the transistor’s body-diode” appears that it should read as “current flowing through the transistor’s body-diode”. Appropriate correction is required.
Claim Objections
Claims 8, 10, 11, and 16 are objected to because of the following informalities: Regarding claim 8, in lines 6-7, “the adjusted count value” appears that it should read as “the changed count value”, because of antecedent basis (the count value is previously recited as being changed by adjusting the first logic circuit output or the second logic circuit output, and no adjusted count value is previously recited).
Regarding claim 10, in line 2, “a third flip-flop input” appears that it should read as “a third counter input”, because the recited input is an input of the second counter rather than of the flip-flop (the flip-flop of claim 9 already has a first flip-flop input and a second flip-flop input).
Regarding claim 11, in line 11, “the logic gate output, the second counter input” appears that it should read as “the logic gate output, and the second counter input”, because of a grammatical informality (missing conjunction before the last clause of the series).
Regarding claim 16, in line 13, “transitioning the device to a second phase” appears that it should read as “the device is configured to transition to a second phase”, because of a grammatical informality (the phrase lacks a subject and should parallel “the drive circuit is configured to provide” in line 11). Appropriate correction is required.
Double Patenting
A rejection based on double patenting of the “same invention” type finds its support in the language of 35 U.S.C. 101 which states that “whoever invents or discovers any new and useful process... may obtain a patent therefor...” (Emphasis added). Thus, the term “same invention,” in this context, means an invention drawn to identical subject matter. See Miller v. Eagle Mfg. Co., 151 U.S. 186 (1894); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Ockert, 245 F.2d 467, 114 USPQ 330 (CCPA 1957).
A statutory type (35 U.S.C. 101) double patenting rejection can be overcome by canceling or amending the claims that are directed to the same invention so they are no longer coextensive in scope. The filing of a terminal disclaimer cannot overcome a double patenting rejection based upon 35 U.S.C. 101.
Claims 1-20 are rejected under 35 U.S.C. 101 as claiming the same invention as that of claims 1-20 of prior U.S. Patent No. 12,323,057. This is a statutory double patenting rejection. The correspondence between the conflicting claims, limitation by limitation, is set forth in the table below.
19/193,810
U.S. Patent No. 12,323,057
Claim 1
(a) A device comprising:
(b) a sense circuit having a sense circuit output;
(c) a logic circuit having a logic circuit input, a first logic circuit output, and a second logic circuit output, the logic circuit input coupled to the sense circuit output, the logic circuit comprising an exclusive-NOR gate having a gate output coupled to the first logic circuit output;
(d) a counter having a first counter input, a second counter input, and a counter output, the first counter input coupled to the first logic circuit output, the second counter input coupled to the second logic circuit output, and the counter configured to provide a count value at the counter output; and
(e) a drive circuit having a drive circuit input coupled to the counter output, the drive circuit configured to produce a drive current based on the count value.
Claim 1
(a) A device comprising:
(b) a sense circuit having a sense circuit output;
(c) a logic circuit having a logic circuit input, a first logic circuit output, and a second logic circuit output, the logic circuit input coupled to the sense circuit output, the logic circuit comprising an exclusive-NOR gate having a gate output coupled to the first logic circuit output;
(d) a counter having a first counter input, a second counter input, and a counter output, the first counter input coupled to the first logic circuit output, the second counter input coupled to the second logic circuit output, and the counter configured to provide a count value at the counter output; and
(e) a drive circuit having a drive circuit input coupled to the counter output, the drive circuit configured to produce a drive current based on the count value.
Claim 2
The device of claim 1, further comprising a decoder coupled between the counter output and the drive circuit input.
Claim 2
The device of claim 1, further comprising a decoder coupled between the counter output and the drive circuit input.
Claim 3
(a) The device of claim 1, wherein the logic circuit is configured to: detect whether a rate of change of a drain current of a transistor is above a threshold; and
(b) responsive to the rate of change of the drain current being above the threshold, adjust the first logic circuit output or the second logic circuit output to change the count value.
Claim 3
(a) The device of claim 1, wherein the logic circuit is configured to: detect whether a rate of change of a drain current of a transistor is above a threshold; and
(b) responsive to the rate of change of the drain current being above the threshold, adjust the first logic circuit output or the second logic circuit output to change the count value.
Claim 4
(a) The device of claim 1, wherein the logic circuit is configured to:
(b) detect whether a signal indicative of a rate of change of a drain current of a transistor is above first and second thresholds;
(c) responsive to the signal being above the first and second thresholds, adjust the first logic circuit output or the second logic circuit output to increment the count value; and
(d) responsive to the signal being below the first and second thresholds, adjust the first logic circuit output or the second logic circuit output to decrement the count value.
Claim 4
(a) The device of claim 1, wherein the logic circuit is configured to:
(b) detect whether a signal indicative of a rate of change of a drain current of a transistor is above first and second thresholds;
(c) responsive to the signal being above the first and second thresholds, adjust the first logic circuit output or the second logic circuit output to increment the count value; and
(d) responsive to the signal being below the first and second thresholds, adjust the first logic circuit output or the second logic circuit output to decrement the count value.
Claim 5
The device of claim 4, wherein the logic circuit is configured to: responsive to the signal being between the first and second thresholds, adjust the first logic circuit output or the second logic circuit output to prevent the counter from incrementing or decrementing the count value.
Claim 5
The device of claim 4, wherein the logic circuit is configured to: responsive to the signal being between the first and second thresholds, adjust the first logic circuit output or the second logic circuit output to prevent the counter from incrementing or decrementing the count value.
Claim 6
The device of claim 1, wherein the sense circuit includes a high-pass filter.
Claim 6
The device of claim 1, wherein the sense circuit includes a high-pass filter.
Claim 7
(a) The device of claim 1, wherein the logic circuit further comprises:
(b) a first comparator having a comparator output and first and second comparator inputs, in which the comparator output is the second logic circuit output;
(c) a second comparator having a second comparator output and third and fourth comparator inputs; and
(d) a flip-flop having a flip-flop input and a flip-flop output, in which the flip-flop output is the first logic circuit output, and the flip-flop input is coupled to the gate output of the exclusive-NOR gate.
Claim 7
(a) The device of claim 1, wherein the logic circuit further comprises:
(b) a first comparator having a comparator output and first and second comparator inputs, in which the comparator output is the second logic circuit output;
(c) a second comparator having a second comparator output and third and fourth comparator inputs; and
(d) a flip-flop having a flip-flop input and a flip-flop output, in which the flip-flop output is the first logic circuit output, and the flip-flop input is coupled to the gate output of the exclusive-NOR gate.
Claim 8
(a) The device of claim 1, wherein:
(b) the logic circuit is configured to: detect whether a rate of change of a drain current of a transistor is above a threshold; and responsive to the rate of change of the drain current being above the threshold, adjust the first logic circuit output or the second logic circuit output to change the count value;
(c) the drive circuit is configured to decrease the drive current responsive to the adjusted count value;
(d) the device further comprises a switch node transition detection circuit configured to: detect whether the transistor has turned on; and responsive to detecting that the transistor has turned on, provide a signal to the logic circuit; and
(e) the drive circuit is configured to increase the drive current at a control terminal of the transistor responsive to the provided signal.
Claim 8
(a) The device of claim 1, wherein:
(b) the logic circuit is configured to: detect whether a rate of change of a drain current of a transistor is above a threshold; and responsive to the rate of change of the drain current being above the threshold, adjust the first logic circuit output or the second logic circuit output to change the count value;
(c) the drive circuit is configured to decrease the drive current responsive to the adjusted count value;
(d) the device further comprises a switch node transition detection circuit configured to: detect whether the transistor has turned on; and responsive to detecting that the transistor has turned on, provide a signal to the logic circuit; and
(e) the drive circuit is configured to increase the drive current at a control terminal of the transistor responsive to the provided signal.
Claim 9
(a) The device of claim 1, further comprising:
(b) a comparator having a comparator output;
(c) a delay circuit having a delay circuit output; and
(d) a flip-flop having a first flip-flop input, a second flip-flop input, and a flip-flop output, the first flip-flop input coupled to the delay circuit output, and the second flip-flop input coupled to the comparator output.
Claim 9
(a) The device of claim 1, further comprising:
(b) a comparator having a comparator output;
(c) a delay circuit having a delay circuit output; and
(d) a flip-flop having a first flip-flop input, a second flip-flop input, and a flip-flop output, the first flip-flop input coupled to the delay circuit output, and the second flip-flop input coupled to the comparator output.
Claim 10
The device of claim 9, wherein the counter is a first counter, and the device further comprises a second counter having a third flip-flop input coupled to the flip-flop output.
Claim 10
The device of claim 9, wherein the counter is a first counter, and the device further comprises a second counter having a third flip-flop input coupled to the flip-flop output.
Claim 11
(a) A device comprising:
(b) a sense circuit having a sense circuit output;
(c) a first comparator having a first comparator output and a first comparator input, the first comparator input coupled to the sense circuit output;
(d) a second comparator having a second comparator output and a second comparator input, the second comparator input coupled to the sense circuit output;
(e) a logic gate having a logic gate output and first and second logic gate inputs, the first logic gate input coupled to the first comparator output, and the second logic gate input coupled to the second comparator output;
(f) a first counter having a first counter input, a second counter input, and a first counter output, the first counter input coupled to the logic gate output, the second counter input coupled to the second comparator output;
(g) a flip-flop having a flip-flop output;
(h) a second counter having a third counter input and a second counter output, the third counter input coupled to the flip-flop output; and
(i) a drive circuit having a drive circuit input, the drive circuit input coupled to the first counter output and the second counter output.
Claim 11
(a) A device comprising:
(b) a sense circuit having a sense circuit output;
(c) a first comparator having a first comparator output and a first comparator input, the first comparator input coupled to the sense circuit output;
(d) a second comparator having a second comparator output and a second comparator input, the second comparator input coupled to the sense circuit output;
(e) a logic gate having a logic gate output and first and second logic gate inputs, the first logic gate input coupled to the first comparator output, and the second logic gate input coupled to the second comparator output;
(f) a first counter having a first counter input, a second counter input, and a first counter output, the first counter input coupled to the logic gate output, the second counter input coupled to the second comparator output;
(g) a flip-flop having a flip-flop output;
(h) a second counter having a third counter input and a second counter output, the third counter input coupled to the flip-flop output; and
(i) a drive circuit having a drive circuit input, the drive circuit input coupled to the first counter output and the second counter output.
Claim 12
The device of claim 11, wherein the logic gate is an exclusive-NOR gate.
Claim 12
The device of claim 11, wherein the logic gate is an exclusive-NOR gate.
Claim 13
The device of claim 11, wherein the flip-flop is a first flip-flop, the device further comprising a second flip-flop having a flip-flop input, wherein the flip-flop input is coupled to the logic gate output.
Claim 13
The device of claim 11, wherein the flip-flop is a first flip-flop, the device further comprising a second flip-flop having a flip-flop input, wherein the flip-flop input is coupled to the logic gate output.
Claim 14
The device of claim 11, wherein the sense circuit includes a high-pass filter.
Claim 14
The device of claim 11, wherein the sense circuit includes a high-pass filter.
Claim 15
(a) The device of claim 11, further comprising:
(b) a delay circuit having a delay circuit input and a delay circuit output, the delay circuit input coupled to the first counter output and the delay circuit output coupled to the drive circuit input.
Claim 15
(a) The device of claim 11, further comprising:
(b) a delay circuit having a delay circuit input and a delay circuit output, the delay circuit input coupled to the first counter output and the delay circuit output coupled to the drive circuit input.
Claim 16
(a) A device comprising:
(b) a sense circuit having a sense circuit output;
(c) a logic circuit having a logic circuit input and first and second logic circuit outputs, the logic circuit input coupled to the sense circuit output;
(d) a drive circuit having a drive circuit input and a drive circuit output; and
(e) a counter having a first counter input, a second counter input, and a counter output, the first counter input coupled to the first logic circuit output, the second counter input coupled to the second logic circuit output, the counter output coupled to the drive circuit input, and the counter configured to provide a count value at the counter output; and wherein:
(f) during a first phase, the drive circuit is configured to provide a fixed level of a drive current responsive to receiving a pulse for a time duration; and
(g) responsive to the pulse ending, transitioning the device to a second phase, in which the drive circuit is configured to provide a variable level of the drive current at the drive circuit output responsive to the count value.
Claim 16
(a) A device comprising:
(b) a sense circuit having a sense circuit output;
(c) a logic circuit having a logic circuit input and first and second logic circuit outputs, the logic circuit input coupled to the sense circuit output;
(d) a drive circuit having a drive circuit input and a drive circuit output; and
(e) a counter having a first counter input, a second counter input, and a counter output, the first counter input coupled to the first logic circuit output, the second counter input coupled to the second logic circuit output, the counter output coupled to the drive circuit input, and the counter configured to provide a count value at the counter output; and wherein:
(f) during a first phase, the drive circuit is configured to provide a fixed level of a drive current responsive to receiving a pulse for a time duration; and
(g) responsive to the pulse ending, transitioning the device to a second phase, in which the drive circuit is configured to provide a variable level of the drive current at the drive circuit output responsive to the count value.
Claim 17
The device of claim 16, further comprising a decoder coupled between the counter output and the drive circuit input, in which the decoder is configured to convert the count value to a signal, and the drive circuit is configured to receive the signal at the drive circuit input.
Claim 17
The device of claim 16, further comprising a decoder coupled between the counter output and the drive circuit input, in which the decoder is configured to convert the count value to a signal, and the drive circuit is configured to receive the signal at the drive circuit input.
Claim 18
(a) The device of claim 16, wherein the logic circuit is configured to: detect whether a rate of change of a drain current at a transistor is above a threshold; and
(b) responsive to the rate of change of the drain current being above the threshold, adjust the first logic circuit output or the second logic circuit output to change the count value.
Claim 18
(a) The device of claim 16, wherein the logic circuit is configured to: detect whether a rate of change of a drain current at a transistor is above a threshold; and
(b) responsive to the rate of change of the drain current being above the threshold, adjust the first logic circuit output or the second logic circuit output to change the count value.
Claim 19
(a) The device of claim 16, wherein the logic circuit is configured to:
(b) detect whether a signal indicative of a rate of change of a drain current at a transistor is above first and second thresholds;
(c) responsive to the signal being above the first and second thresholds, adjust the first logic circuit output or the second logic circuit output to increment the count value;
(d) responsive to the signal being below the first and second thresholds, adjust the first logic circuit output or the second logic circuit output to decrement the count value; and
(e) responsive to the signal being between the first threshold and the second threshold, maintain the count value.
Claim 19
(a) The device of claim 16, wherein the logic circuit is configured to:
(b) detect whether a signal indicative of a rate of change of a drain current at a transistor is above first and second thresholds;
(c) responsive to the signal being above the first and second thresholds, adjust the first logic circuit output or the second logic circuit output to increment the count value;
(d) responsive to the signal being below the first and second thresholds, adjust the first logic circuit output or the second logic circuit output to decrement the count value; and
(e) responsive to the signal being between the first threshold and the second threshold, maintain the count value.
Claim 20
(a) The device of claim 16, further comprising:
(b) a comparator having a comparator output;
(c) a delay circuit having a delay circuit output; and
(d) a flip-flop having a flip-flop clock input, a data input and a flip-flop output, the flip-flop clock input coupled to the delay circuit output, and the data input coupled to the comparator output.
Claim 20
(a) The device of claim 16, further comprising:
(b) a comparator having a comparator output;
(c) a delay circuit having a delay circuit output; and
(d) a flip-flop having a flip-flop clock input, a data input and a flip-flop output, the flip-flop clock input coupled to the delay circuit output, and the data input coupled to the comparator output.
As shown above, each of claims 1-20 of the instant application recites, word for word, the same limitations as the correspondingly numbered claim of U.S. Patent No. 12,323,057, and each of claims 2-10, 12-15, and 17-20 depends from the same claim as its counterpart in U.S. Patent No. 12,323,057. Therefore, there is no embodiment that falls within the scope of a claim of the instant application but outside the scope of the corresponding claim of U.S. Patent No. 12,323,057, and the conflicting claims are coextensive in scope.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure: US 2018/0269869 A1 discloses a gate driver circuit with variable gate drive current. US 2020/0076292 A1 discloses a system for regulating semiconductor devices including a current regulator configured to regulate one or more currents provided to an insulated gate bipolar transistor (IGBT) by generating a current profile based at least in part on a collector voltage value associated with the IGBT, a rate of collector voltage change value associated with the IGBT. US 2014/0015571 A1 discloses a current regulator configured to regulate one or more currents provided to an insulated gate bipolar transistor (IGBT) by generating a current profile based at least in part on a collector voltage value associated with the IGBT, a rate of collector voltage change value associated with the IGBT. US 2017/0373676 A1 discloses a drive device and a power supply system capable of driving a power transistor with low power while reflecting variations in manufacture process and external environments. US Patent 10,461,732 B1 discloses a system for driving a power switch in combination with a regulated dI/dt and dV/dt. CN 114050712 A discloses a method for detecting a signal connected to a switching node of the power switch to increase the gate driving current.
Lobsiger et al. (Y. Lobsiger and J. W. Kolar, "Closed-loop IGBT gate drive featuring highly dynamic di/dt and dv/dt control," 2012 IEEE Energy Conversion Congress and Exposition (ECCE), Raleigh, NC, USA, 2012, pp. 4754-4761) discloses a closed-loop IGBT gate driver circuit.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to JYE-JUNE LEE whose telephone number is (571)270-7726. The examiner can normally be reached on M-F 9 AM - 5 PM.
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/JYE-JUNE LEE/Examiner, Art Unit 2838
/JUE ZHANG/Primary Examiner, Art Unit 2838
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