DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Priority
Examiner notes Applicant’s deletion of fig. 47 and the corresponding disclosure in the specification in order to maintain this application’s status as a continuation of the prior-filed application(s).
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 32-33 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Yang (WO 2019/037499, published 2/28/2019; *note: US 2020/0388214 will be relied upon as an English translation for WO 2019/037499, and Examiner will refer to the reference as Yang ‘214).
Regarding claim 32, Yang ‘214 discloses a display panel, comprising: a transmit driving circuit (abstract, figs. 7-10, ¶ 103-111, see also fig. 11, ¶ 129-136, scan circuits S and EM),
a pixel driving circuit (figs. 7-10, ¶ 103-111, see also fig. 11, ¶ 129-136),
and a light-emitting component (figs. 7-10, ¶ 103-111, light emitting device L);
wherein the pixel driving circuit comprises a driving transistor (figs. 7-10, ¶ 103-111, DTFT), a data writing module (figs. 7-10, ¶ 103-111, M6), an initialization module (figs. 7-10, ¶ 103-111, M1 and M2), and a light-emitting control module (figs. 7-10, ¶ 103-111, M3 and M4);
wherein the data writing module is configured for transmitting a data voltage signal to a control terminal of the driving transistor such that the driving transistor generates a driving current according to the data voltage signal provided by a data signal terminal (figs. 7-10, ¶ 103-124, e.g., see fig. 9);
wherein the initialization module is configured for providing an initialization voltage signal to at least one of the control terminal of the driving transistor or an anode of the light-emitting component (figs. 7-10, ¶ 103-124, e.g., see fig. 8);
wherein the light-emitting control module is connected in series between a positive power signal terminal and the light-emitting component (figs. 7-10, ¶ 103-124, e.g., see fig. 10);
and wherein a transistor in the initialization module is a P-type transistor and a transistor in the light-emitting control module is an N-type transistor, or a transistor in the initialization module is an N-type transistor and a transistor in the light-emitting control module is a P-type transistor (figs. 7-10, ¶ 103-124, e.g., see ¶ 111);
wherein a control terminal of the initialization module and a control terminal of the light-emitting control module are configured for receiving a transmit driving signal generated by a same transmit driving circuit (figs. 7-10, ¶ 103-124, e.g., S2 and S1; see also fig. 11, ¶ 129-136).
Regarding claim 33, Yang ‘214 discloses wherein the pixel driving circuit further comprises a first light-emitting control unit and a second light-emitting control unit (figs. 7-10, ¶ 103-111, M4 and M3);
the first light-emitting control unit is electrically connected between the positive power signal terminal and a first terminal of the driving transistor, and the second light-emitting control unit is electrically connected between a second terminal of the driving transistor and the light-emitting component (figs. 7-10, ¶ 103-111, M4 and M3).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 20-21 are rejected under 35 U.S.C. 103 as being unpatentable over Yang ‘214.
Regarding claim 20, Yang discloses a display panel, comprising: a transmit driving circuit (abstract, figs. 7-10, ¶ 103-111, see also fig. 11, ¶ 129-136, scan circuits S and EM),
a pixel driving circuit (figs. 7-10, ¶ 103-111, see also fig. 11, ¶ 129-136),
and a light-emitting component (figs. 7-10, ¶ 103-111, light emitting device L);
wherein the pixel driving circuit comprises a driving transistor (figs. 7-10, ¶ 103-111, DTFT), a data writing transistor (figs. 7-10, ¶ 103-111, M6), an initialization transistor (figs. 7-10, ¶ 103-111, M1 and M2), and a light-emitting control transistor (figs. 7-10, ¶ 103-111, M3 and M4);
wherein the data writing transistor is configured for transmitting a data voltage signal to a control terminal of the driving transistor such that the driving transistor generates a driving current according to the data voltage signal provided by a data signal terminal (figs. 7-10, ¶ 103-124, e.g., see fig. 9);
wherein the initialization transistor is configured for providing an initialization voltage signal for a gate of the driving transistor (figs. 7-10, ¶ 103-124, e.g., see fig. 8);
wherein the light-emitting control transistor is connected in series between a positive power signal terminal and the light-emitting component (figs. 7-10, ¶ 103-124, e.g., see fig. 10);
wherein a gate of the initialization transistor and a gate of the light-emitting control transistor are configured for receiving a transmit driving signal generated by a transmit driving circuit (figs. 7-10, ¶ 103-124, e.g., S2 and S1; see also fig. 11, ¶ 129-136).
Yang ‘214 fails to explicitly disclose a semiconductor oxide initialization transistor. However, Examiner takes official notice that the use of semiconductor oxide transistors is well known in the art. Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the device of Yang ‘214 with the well-known semiconductor oxide transistors since such a modification achieves the predictable result of utilizing well-known materials and manufacturing practices. Applicant has not traversed Examiner’s assertion of official notice in the reply filed 3/30/26, and thus the use of semiconductor oxide transistors is taken to be admitted prior art [see MPEP 2144.03].
Regarding claim 21, Yang ‘214 discloses wherein the light-emitting control transistor comprises a first light-emitting control transistor and a second light-emitting control transistor (figs. 7-10, ¶ 103-111, M4 and M3);
the first light-emitting control transistor is electrically connected between the positive power signal terminal and a first terminal of the driving transistor, and the second light-emitting control transistor is electrically connected between a second terminal of the driving transistor and the light-emitting component (figs. 7-10, ¶ 103-111, M4 and M3).
Claims 1-4 and 8-10 are rejected under 35 U.S.C. 103 as being unpatentable over Yang ‘214 in view of Lin et al. (US 2021/0193049).
Regarding claim 1, Yang ‘214 discloses a display panel, comprising: a gate driving circuit (abstract, figs. 7-10, ¶ 103-111, see also fig. 11, ¶ 129-136, scan circuits S and EM),
a pixel driving circuit (figs. 7-10, ¶ 103-111, see also fig. 11, ¶ 129-136),
and a light-emitting component (figs. 7-10, ¶ 103-111, light emitting device L);
wherein the pixel driving circuit comprises a driving transistor (figs. 7-10, ¶ 103-111, DTFT), a data writing module (figs. 7-10, ¶ 103-111, M6), an initialization module (figs. 7-10, ¶ 103-111, M1 and M2), and a light-emitting control module (figs. 7-10, ¶ 103-111, M3 and M4);
wherein the data writing module is configured for transmitting a data voltage signal to a control terminal of the driving transistor such that the driving transistor generates a driving current according to the data voltage signal provided by a data signal terminal (figs. 7-10, ¶ 103-124, e.g., see fig. 9);
wherein the initialization module is configured for providing an initialization voltage signal to at least one of the control terminal of the driving transistor or an anode of the light-emitting component (figs. 7-10, ¶ 103-124, e.g., see fig. 8);
wherein the light-emitting control module is connected in series between a positive power signal terminal and the light-emitting component (figs. 7-10, ¶ 103-124, e.g., see fig. 10);
wherein a transistor in the initialization module is a P-type transistor and a transistor in the light-emitting control module is an N-type transistor, or a transistor in the initialization module is an N-type transistor and a transistor in the light-emitting control module is a P-type transistor (figs. 7-10, ¶ 103-124, e.g., see ¶ 111);
wherein a control terminal of the initialization module and a control terminal of the light-emitting control module are configured for receiving a gate driving signal generated by a same gate driving circuit (figs. 7-10, ¶ 103-124, e.g., S2 and S1; see also fig. 11, ¶ 129-136),
and wherein the pixel driving circuit further comprises a second light-emitting control unit and an anode initialization transistor, the second light-emitting control unit is electrically connected between a second terminal of the driving transistor and the light-emitting component, the anode initialization transistor is electrically connected between an initialization signal terminal and the anode of the light-emitting component (figs. 7-10, ¶ 103-124, M3 and M2; see also fig. 11, ¶ 129-136);
the gate driving circuit comprises a transmit driving circuit, the transmit driving circuit comprises a plurality of cascaded transmit driving units (figs. 7-10, ¶ 103-111, see also fig. 11, ¶ 129-136, scan circuits S and EM);
a control terminal of the second light-emitting control unit is configured for receiving a transmit driving signal generated by a current-stage transmit driving unit (figs. 7-10, ¶ 103-124, S1; see also fig. 11, ¶ 129-136).
Yang ‘214 fails to disclose a control terminal of the anode initialization transistor is configured for receiving the transmit driving signal generated by the current-stage transmit driving unit.
Lin teaches a control terminal of the anode initialization transistor is configured for receiving the transmit driving signal generated by the current-stage transmit driving unit (fig. 3A, ¶ 47-53, transistors Tem2 and Tini controlled by the same signal EM(n)).
Yang ‘214 and Lin are both directed to pixel driving circuits for OLED displays. Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date to combine the device of Yang ‘214 with the device of Lin since such a modification enables fewer row control lines to be formed, which reduces routing complexity (Lin, ¶ 51).
Regarding claim 2, Yang ‘214 discloses wherein the gate driving signal is a transmit driving signal (figs. 7-10, ¶ 103-111, see also fig. 11, ¶ 129-136, scan circuits S and EM).
Regarding claim 3, Yang ‘214 discloses wherein the pixel driving circuit is configured for receiving at most two types of gate driving signals (figs. 7-10, ¶ 103-111, see also fig. 11, ¶ 129-136, scan circuits S and EM).
Regarding claim 4, Yang ‘214 discloses wherein the pixel driving circuit further comprises a first light-emitting control unit (figs. 7-10, ¶ 103-111, M4);
the first light-emitting control unit is electrically connected between the positive power signal terminal and a first terminal of the driving transistor (figs. 7-10, ¶ 103-111, M4).
Regarding claim 8, Yang ‘214 discloses wherein the pixel driving circuit further comprises a threshold compensation transistor electrically connected between the control terminal of the driving transistor and a second terminal of the driving transistor (figs. 7-10, ¶ 103-124, M5),
and the control terminal of the initialization module and a control terminal of the threshold compensation transistor are configured for receiving a gate driving signal generated by a same gate driving circuit (figs. 7-10, ¶ 103-124, e.g., S2 and S1; see also fig. 11, ¶ 129-136).
Regarding claim 9, Yang ‘214 discloses wherein the control terminal of the threshold compensation transistor is configured for receiving a transmit driving signal generated by a current-stage transmit driving unit (figs. 7-10, ¶ 103-124, scan circuits S and EM, e.g., S1; see also fig. 11, ¶ 129-136).
Regarding claim 10, Lin further teaches wherein a transistor in the initialization module and the threshold compensation transistor are each a semiconductor oxide transistor (fig. 3A, ¶ 47-53, semiconducting oxide transistors disclosed).
Claims 5, 14, 18, and 19 are rejected under 35 U.S.C. 103 as being unpatentable over Yang ‘214 in view of Lin as applied to claim 4 above, and further in view of Huangfu et al. (US 2023/0042603).
Regarding claim 5, Yang ‘214 discloses wherein the initialization module comprises a gate initialization transistor which is electrically connected between the initialization signal terminal and the control terminal of the driving transistor (figs. 7-10, ¶ 103-111, e.g., M1);
and a control terminal of the gate initialization transistor is configured for receiving a transmission driving signal generated by a previous-stage transmission driving unit (figs. 7-10, ¶ 103-124, S2; see also fig. 11, ¶ 129-136).
Yang ‘214 in view of Lin fails to disclose a control terminal of the first light-emitting control unit is configured for receiving a transmission driving signal generated by a previous-stage transmission driving unit.
Huangfu teaches a control terminal of the first light-emitting control unit is configured for receiving a transmission driving signal generated by a previous-stage transmission driving unit (figs. 3-6, ¶ 84-85, EM(n-1)).
Yang ‘214 in view of Lin and Huangfu are both directed to pixel driving circuits for OLED displays. Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date to combine the device of Yang ‘214 in view of Lin with the device of Huangfu since such a modification reduces manufacturing difficulty and cost (Huangfu, ¶ 85).
Regarding claim 14, this claim is rejected under the same rationale as claim 5.
Regarding claim 18, this claim is rejected under the same rationale as claim 10.
Regarding claim 19, Yang ‘214 discloses wherein the data writing module comprises a data writing transistor electrically connected between a data voltage signal terminal and the first terminal of the driving transistor (figs. 7-10, ¶ 103-111, M6; see also fig. 11, ¶ 129-136);
and the gate driving circuit further comprises a scan driving circuit (figs. 7-10, ¶ 103-111, see also fig. 11, ¶ 129-136, scan circuits S and EM),
a control terminal of the data writing transistor is configured for receiving a scan driving signal generated by a scan driving circuit (figs. 7-10, ¶ 103-111, S1; see also fig. 11, ¶ 129-136).
Claims 11 and 17 are rejected under 35 U.S.C. 103 as being unpatentable over Yang ‘214 in view Lin and Huangfu as applied to claims 5 and 14 above, and further in view of Yang et al. (US 2021/0358405; hereinafter referred to as Yang ‘405).
Regarding claim 11, Yang ‘214 in view of Lin and Huangfu fails to explicitly disclose wherein the gate initialization transistor is configured for initializing the anode of the light-emitting component.
Yang ‘405 teaches wherein the gate initialization transistor is configured for initializing the anode of the light-emitting component (figs. 6-9, ¶ 63-72, see also ¶ 77-80, Vref provided through T4 and T3 to reset nodes N3 and N1).
Yang’ 214 in view of Lin and Huangfu and Yang ‘405 are both directed to pixel driving circuits for OLED displays. Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date to combine the device of Yang ‘214 in view of Lin and Huangfu with the device of Yang ‘405 since such a modification reduces after image (Yang ‘405, ¶ 78) and improves contrast (Yang ‘405, ¶ 80).
Regarding claim 17, Yang ‘214 discloses wherein the pixel driving circuit further comprises an initialization phase, a data writing phase and a light-emitting phase (figs. 7-10, ¶ 112-124).
Yang ‘214 in view of Lin and Huangfu fails to explicitly disclose the initialization transistor is configured for initializing both the control terminal of the driving transistor and the anode of the light-emitting component during the initialization phase.
Yang ‘405 teaches the initialization transistor is configured for initializing both the control terminal of the driving transistor and the anode of the light-emitting component during the initialization phase (figs. 6-9, ¶ 63-72, see also ¶ 77-80, Vref provided through T4 and T3 to reset nodes N3 and N1).
Yang’ 214 in view of Lin and Huangfu and Yang ‘405 are both directed to pixel driving circuits for OLED displays. Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date to combine the device of Yang ‘214 in view of Lin Huangfu with the device of Yang ‘405 since such a modification reduces after image (Yang ‘405, ¶ 78) and improves contrast (Yang ‘405, ¶ 80).
Claims 22-23, 27-28, 30, 34, and 36-37 are rejected under 35 U.S.C. 103 as being unpatentable over Yang ‘214 in view of Huangfu.
Regarding claim 22, Yang ‘214 discloses wherein the semiconductor oxide initialization transistor is electrically connected between an initialization signal terminal and the gate of the driving transistor (figs. 7-10, ¶ 103-111, e.g., M1);
the transmit driving circuit comprises a plurality of cascaded transmit driving units (figs. 7-10, ¶ 103-111, see also fig. 11, ¶ 129-136, scan circuits S and EM);
and a gate of the semiconductor oxide initialization transistor is configured for receiving a transmit driving signal generated by a previous-stage transmit driving unit (figs. 7-10, ¶ 103-124, S2; see also fig. 11, ¶ 129-136).
Yang ‘214 fails to disclose a gate of the first light-emitting control transistor is configured for receiving a transmit driving signal generated by a previous-stage transmit driving unit.
Huangfu teaches a gate of the first light-emitting control transistor is configured for receiving a transmit driving signal generated by a previous-stage transmit driving unit (figs. 3-6, ¶ 84-85, EM(n-1)).
Yang ‘214 and Huangfu are both directed to pixel driving circuits for OLED displays. Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date to combine the device of Yang ‘214 with the device of Huangfu since such a modification reduces manufacturing difficulty and cost (Huangfu, ¶ 85).
Regarding claim 23, Yang ‘214 discloses wherein a gate of the second light-emitting control transistor is configured for receiving a transmit driving signal generated by a current-stage transmit driving unit (figs. 7-10, ¶ 103-124, S1; see also fig. 11, ¶ 129-136).
Regarding claim 27, Yang ‘214 discloses wherein the pixel driving circuit further comprises an anode initialization transistor which is electrically connected between the initialization signal terminal and an anode of the light-emitting component (figs. 7-10, ¶ 103-124, M2; see also fig. 11, ¶ 129-136);
wherein the display panel further comprises a scan driving circuit (figs. 7-10, ¶ 103-111, see also fig. 11, ¶ 129-136, scan circuits S and EM),
a gate of the anode initialization transistor is configured for receiving a scan driving signal generated by a scan driving circuit (figs. 7-10, ¶ 103-124, S2; see also fig. 11, ¶ 129-136).
Regarding claim 28, this claim is rejected under the same rationale as claim 8.
Regarding claim 30, this claim is rejected under the same rationale as claim 19.
Regarding claim 34, Yang ‘214 discloses wherein the initialization module comprises a gate initialization transistor which is electrically connected between an initialization signal terminal and the control terminal of the driving transistor (figs. 7-10, ¶ 103-111, e.g., M1);
the transmit driving circuit comprises a plurality of cascaded transmit driving units (figs. 7-10, ¶ 103-111, see also fig. 11, ¶ 129-136, scan circuits S and EM);
and a control terminal of the gate initialization transistor is configured for receiving a transmission driving signal generated by a previous-stage transmission driving unit (figs. 7-10, ¶ 103-124, S2; see also fig. 11, ¶ 129-136).
Yang ‘214 fails to disclose a control terminal of the first light-emitting control unit is configured for receiving a transmission driving signal generated by a previous-stage transmission driving unit.
Huangfu teaches a control terminal of the first light-emitting control unit is configured for receiving a transmission driving signal generated by a previous-stage transmission driving unit (figs. 3-6, ¶ 84-85, EM(n-1)).
Yang ‘214 and Huangfu are both directed to pixel driving circuits for OLED displays. Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date to combine the device of Yang ‘214 with the device of Huangfu since such a modification reduces manufacturing difficulty and cost (Huangfu, ¶ 85).
Regarding claim 36, Yang ‘214 discloses a scan driving circuit (figs. 7-10, ¶ 103-111, see also fig. 11, ¶ 129-136, scan circuits S and EM),
wherein the pixel driving circuit further comprises an anode initialization transistor electrically connected between the initialization signal terminal and the anode of the light-emitting component (figs. 7-10, ¶ 103-124, M2; see also fig. 11, ¶ 129-136);
and a control terminal of the anode initialization transistor is configured for receiving a scan driving signal generated by the scan driving circuit (figs. 7-10, ¶ 103-124, S2; see also fig. 11, ¶ 129-136).
Regarding claim 37, Yang ‘214 discloses wherein the initialization module comprises an initialization transistor electrically connected between an initialization signal terminal and the second terminal of the driving transistor (figs. 7-10, ¶ 103-111, e.g., M1);
the transmit driving circuit comprises a plurality of cascaded transmit driving units (figs. 7-10, ¶ 103-111, see also fig. 11, ¶ 129-136, scan circuits S and EM);
and a control terminal of the initialization transistor is configured for receiving a transmit driving signal generated by a previous-stage transmit driving unit (figs. 7-10, ¶ 103-124, S2; see also fig. 11, ¶ 129-136).
Yang ‘214 fails to disclose a control terminal of the first light-emitting control unit is configured for receiving a transmit driving signal generated by a previous-stage transmit driving unit.
Huangfu teaches a control terminal of the first light-emitting control unit is configured for receiving a transmit driving signal generated by a previous-stage transmit driving unit (figs. 3-6, ¶ 84-85, EM(n-1)).
Yang ‘214 and Huangfu are both directed to pixel driving circuits for OLED displays. Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date to combine the device of Yang ‘214 with the device of Huangfu since such a modification reduces manufacturing difficulty and cost (Huangfu, ¶ 85).
Claims 24-26, 29, 35, and 38 are rejected under 35 U.S.C. 103 as being unpatentable over Yang ‘214 in view of Huangfu as applied to claims 22, 34, and 37 above, and further in view of Zhu et al. (US 2017/0263187).
Regarding claim 24, Yang ‘214 in view of Huangfu fails to disclose wherein a gate of the second light-emitting control unit is configured for receiving a transmit driving signal generated by a subsequent-stage transmit driving unit.
Zhu teaches wherein a gate of the second light-emitting control unit is configured for receiving a transmit driving signal generated by a subsequent-stage transmit driving unit (figs 1-3, ¶ 22-32, T5 receives E2, see also fig. 9, ¶ 94, ¶ 99-103, a scanning signal line between two adjacent rows may be multiplexed).
Yang ‘214 in view of Huangfu and Zhu are both directed to pixel driving circuits for OLED displays. Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date to combine the device of Yang ‘214 in view of Huangfu with the device of Zhu since such a modification reduces the layout area occupied by the circuit (Zhu, ¶ 103).
Regarding claim 25, Yang ‘214 discloses wherein the pixel driving circuit comprises an initialization phase, a data writing phase and a light-emitting phase (figs. 7-10, ¶ 112-124).
Zhu further teaches the semiconductor oxide initialization transistor is configured for initializing an anode of the light-emitting component (figs 1-4, ¶ 48-50).
Regarding claim 26, Yang ‘214 discloses wherein the pixel driving circuit further comprises a semiconductor oxide anode initialization transistor which is electrically connected between an initialization signal terminal and an anode of the light-emitting component (figs. 7-10, ¶ 103-124, M2; see also fig. 11, ¶ 129-136),
Yang ‘214 in view of Huangfu fails to disclose a gate of the semiconductor oxide anode initialization transistor is configured for receiving a transmit driving signal generated by a current-stage transmit driving unit.
Zhu teaches a gate of the semiconductor oxide anode initialization transistor is configured for receiving a transmit driving signal generated by a current-stage transmit driving unit (figs 1-3, ¶ 22-32, T1 receives S1; see also fig. 9, ¶ 99-103).
Yang ‘214 in view of Huangfu and Zhu are both directed to pixel driving circuits for OLED displays. Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date to combine the device of Yang ‘214 in view of Huangfu with the device of Zhu since such a modification provides the voltage level of the anode may be more stable (¶ 27) and reduces the layout area occupied by the circuit (Zhu, ¶ 103).
Regarding claim 29, this claim is rejected under the same rationale as claim 26.
Regarding claim 35, Yang ‘214 in view of Huangfu fails to disclose wherein a control terminal of the second light-emitting control unit is configured for receiving a transmit driving signal generated by a subsequent-stage transmit driving unit.
Zhu teaches wherein a control terminal of the second light-emitting control unit is configured for receiving a transmit driving signal generated by a subsequent-stage transmit driving unit (figs 1-3, ¶ 22-32, T5 receives E2, see also fig. 9, ¶ 94, ¶ 99-103, a scanning signal line between two adjacent rows may be multiplexed).
Yang ‘214 in view of Huangfu and Zhu are both directed to pixel driving circuits for OLED displays. Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date to combine the device of Yang ‘214 in view of Huangfu with the device of Zhu since such a modification reduces the layout area occupied by the circuit (Zhu, ¶ 103).
Regarding claim 38, this claim is rejected under the same rationale as claim 35.
Response to Arguments
Applicant's arguments filed 3/30/26 have been fully considered but they are not persuasive. In response to applicant's argument that the references fail to show certain features of the invention, it is noted that the features upon which applicant relies (i.e., “receiv[ing] a transmit driving signal generated by the same transmit driving circuit” with respect to claim 20 [see Remarks, p. 19]; and receiving “identical” scan signals with respect to claim 32 [see Remarks, p. 21]) are not recited in the rejected claim(s). Although the claims are interpreted in light of the specification, limitations from the specification are not read into the claims. See In re Van Geuns, 988 F.2d 1181, 26 USPQ2d 1057 (Fed. Cir. 1993).
Applicant’s remaining arguments are moot in view of the new ground(s) of rejection.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to KEITH L CRAWLEY whose telephone number is (571)270-7616. The examiner can normally be reached Monday - Friday 10-6 ET.
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/KEITH L CRAWLEY/ Primary Examiner, Art Unit 2626
