DETAILED ACTION
I. Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
II. Priority
Applicant’s claim for the benefit of a prior-filed application under 35 U.S.C. 119(e) is acknowledged.
III. Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112:
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
Claim 2 is rejected under 35 U.S.C. 112(b) as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor regards as the invention. On line 5, claim 2 recites “the binary pixel sensor” (without “circuit assembly”) for which the claim lacks antecedent basis. Claim 1, on which claim 2 depends, only establishes “a binary pixel sensor circuit assembly.” Moreover, the specification does not delineate which part of the circuit assembly is the binary pixel sensor.
The examiner believes that applicant might have accidentally omitted “circuit assembly” in claim 2. Therefore, to overcome this rejection, the examiner would suggest inserting it on line 5, after “binary pixel sensor.”
IV. Claim Rejections - 35 USC § 103
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
A. Claims 1,13, and 14 are rejected under 35 U.S.C. 103 as being unpatentable over Berner et al. (US 2018/0191972 A1) in view of Kim et al. (US 2025/0232735 A1) and further in view of Sander et al. (US 2013/0193307 A1)
As to claim 1, Berner et al. teaches a binary pixel sensor circuit assembly (Fig. 3, two-dimensional array of pixels “100-n” and readout circuit “42”; [0105]), comprising:
a pixel array comprising a plurality of pixels (Fig. 3, two-dimensional array of pixels “100-n”), at least some of said plurality of pixels (Fig. 3) having a binarization module residing within said at least some of said plurality of pixels (Fig. 3, all circuitry within pixel “100” downstream from the photo sensor “PD”; [0105]), said binarization module comprising a “second” transistor (Figs. 1 and 16, any of transistors within comparator “A1”).
Berner et al. fails to disclose that the binarization module includes (1) a first transistor (2) that is electrically connected with the “second” transistor and (3) that is a hybrid phase transition field-effect transistor (HyperFET) (4) having a phase transition material (PTM) (5) at a source terminal thereof. However, the examiner submits that the following prior art discloses these features and that they are obvious additions to Berner’s pixels “100-n” where the memory “50” of Berner’s Fig. 1, which the reference discloses may be a digital memory element ([0100], lines 5-7), is construed as a phase change memory with a switching transistor that causes a phase change in a material of the memory.
More specifically, in the same field of endeavor as the instant application, Kim et al. discloses a mobile device (Fig. 1) including an array of interspersed display pixels and sensor pixels (Fig. 5, pixels “P”; [0148], lines 1-8). The display pixels include an in-pixel memory (Fig. 13, pixel memory “1240”) and a switching transistor (1) (Fig. 13, transistor “T2”). The in-pixel memory includes a phase change material (4) (Fig. 13, phase change material “1243”) at a source/drain terminal of the switching transistor (Fig. 13). A write signal is applied to a gate of the switching transistor, and a binary signal (0 or 1) is stored in the memory corresponding to a phase change in the material in accordance with a potential difference between the write signal voltage and a voltage at an opposite terminal of the phase change material ([0224]). Also, although not expressly disclosed by Kim et al., the examiner takes official notice to the use of either p-type MOSFETs or n-type MOSFETs as switching elements in pixel sensors as well known in the art, which would place the phase change material of Kim’s pixel memory at the source of the transistor “T2” depending on the chosen configuration (5).
Still, Kim et al. fails to disclose the specific nature of the phase change material, and the examiner stipulates that not any phase change material at the source/drain of a conventional MOSFET would result in the production of a HyperFET. However, further in the same field of endeavor as the instant application, Sander et al. discloses an image sensing pixel (Fig. 1) comprising an in-pixel phase change memory including chalcogenide glass as its phase change material (Fig. 1, non-volatile programmable memory; [0041], lines 21-26). Accordingly, the examiner submits that a MOSFET, like Kim’s transistor “T2”, with chalcogenide glass as the phase change material at its source (or drain) terminal would make it a HyperFET (4) as chalcogenides are common threshold switching materials with the steep change in phase emblematic of HyperFETs1.
Therefore, in light of the teaching of the teaching of Kim et al. and Sander et al. and the well-known use of p-type or n-type transistors in pixel sensors, the examiner submits that it would have been obvious to one of ordinary skill in the art before the effective filing date of the instant application to use a switching transistor whose gate is connected to a signal representing the output of the comparator (2) and whose source includes a chalcogen phase change material that stores bit information representing an on- or off-event indication from the comparator. One of ordinary skill in the art would recognize the numerous advantages that phase change memory cells provide as compared to Berner’s flip-flop or latch. For example, phase change cells are more energy-efficient by consuming power only during writing operations. Additionally, phase change memory cells can be fabricated more densely, which is particularly advantageous when providing memory for each of a large number of pixels.
As to claim 13, Berner et al., as modified by Kim et al. and Sander et al., teaches the binary pixel sensor circuit assembly as set forth in claim 1, wherein all of said plurality of pixels each have a dedicated said binarization module residing therein (see Berner et al., e.g., [0099], lines 1-4).
As to claim 14, Berner et al., as modified by Kim et al. and Sander et al., teaches an image sensor comprising said binary pixel sensor circuit assembly of claim 1 (see Berner et al., Fig. 3, sensor “8”).
B. Claim 15 is rejected under 35 U.S.C. 103 as being unpatentable over Berner et al. (US 2018/0191972 A1) in view of Kim et al. (US 2025/0232735 A1) in view of Sander et al. (US 2013/0193307 A1) and further in view of Moradi Khanshan et al. (US 2024/0137668 A1)
As to claim 15, Berner et al., as modified by Kim et al. and Sander et al., teaches the image sensor as set forth in claim 14. The claim differs from Berner et al., as modified by Kim et al. and Sander et al., in that it requires that the image sensor exhibits a stacked configuration with said binary pixel sensor circuit assembly situated at a first layer and a photodiode assembly situated at a second layer. However, in the same field of endeavor as the instant application, Moradi Khanshan et al. discloses an event sensing pixel (e.g., Figs. 1 and 5; [0031], lines 4-6) comprising a photodiode (Fig. 5, photodiode “132”) formed on first substrate (Figs. 1 and 5, pixel substrate “100”) stacked on a second substrate (Figs. 1 and 5, logic substrate “200”) on which downstream pixel circuitry is positioned (Fig. 5).
In light of the teaching of Moradi Khanshan et al., the examiner submits that it would have been obvious to one of ordinary skill in the art before the effective filing date of the instant application to fabricate the photo sensor of Berner’s pixel on a first substrate that is stacked on a second substrate on which the pixel’s downstream circuitry is fabricated. One of ordinary skill in the art would recognize that stacking substrates in this manner leads to decreased pixel signal noise, faster readout, and greater energy efficiency.
V. Allowable Subject Matter
A. Claims 16-20 are allowed, and the following is the examiner’s statement of reasons for allowance: As to claims 16 and 20, the prior art fails to disclose a binary pixel including a HyperFET having a phase transition material that acts as thresholding element for the binary pixel (i.e., event sensing pixel). Unlike claim 1, claims 16 and claim 20 expressly recite this thresholding function in the phase changes of the phase transition material in response to illumination levels. With the combination of Berner et al., Kim et al., and Sander et al., the examiner renders obvious the broader recitation of the instant invention but by showing that one of ordinary skill in the art would look to incorporate a phase change memory element utilizing a de facto HyperFET in an event sensing pixel. That is, phase changes of the memory element do not occur in response to illumination levels. Claims 17-19 are allowed because they depend on claim 16.
Any comments considered necessary by applicant must be submitted no later than the payment of the issue fee and, to avoid processing delays, should preferably accompany the issue fee. Such submissions should be clearly labeled “Comments on Statement of Reasons for Allowance.”
B. Claims 3-12 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. The following is the examiner’s statement of reasons for the indication of allowable subject matter: Similar to the reasons for allowance of claims 16 and 20 above, claims 3,5,6,8,9, and 10 recite reset, transistor deactivation, and latching operations associated with specific phase states that are wholly separate from the phase states associated with phase-change bit storage. Claims 4 and 7 are allowable because they depend on claims 3 and 6, respectively. Claims 11 and 12 recite limitations associated with the variance of a pulse width and a pulse time period at the second transistor’s gate that are unrelated to storing data using a phase change memory. In the examiner’s combination, the second transistor is part of a comparator.
VI. Additional Pertinent Prior Art
Seo et al. (US 2022/0094865 A1) teaches an event sensor having a binary pixel array and an ancillary phase change memory external to the pixel array. Castillo et al. (US # 11,614,642 B2) discloses a display pixel including a transistor and a phase change material at its source/drain terminal. The reference discloses that the phase change material may be a vanadium oxide, a common threshold switching material used in HyperFETs. However, Castillo et al. is not directed to any light-sensing endeavor; phase is changed to induce a specific optoelectronic effect.
VII. Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ANTHONY J DANIELS whose telephone number is (571)272-7362. The examiner can normally be reached M-F 9:00 AM - 5:00 PM.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Sinh Tran can be reached at 571-272-7564. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/ANTHONY J DANIELS/Primary Examiner, Art Unit 2637
6/23/2026
1 See attached publication from Purdue University, specifically listing chalcogenides as threshold switching materials (pp. 5 and 6).
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