DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 112
The following is a quotation of the first paragraph of 35 U.S.C. 112(a):
(a) IN GENERAL.—The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor or joint inventor of carrying out the invention.
The following is a quotation of the first paragraph of pre-AIA 35 U.S.C. 112:
The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor of carrying out his invention.
Claims 1-10 and 13-20 are rejected under 35 U.S.C. 112(a) or 35 U.S.C. 112 (pre-AIA ), first paragraph, as failing to comply with the written description requirement. The claim(s) contains subject matter which was not described in the specification in such a way as to reasonably convey to one skilled in the relevant art that the inventor or a joint inventor, or for applications subject to pre-AIA 35 U.S.C. 112, the inventor(s), at the time the application was filed, had possession of the claimed invention.
Claim 1 recites “a fifth transistor coupled to the first and second impedance.” Examiner notes that Applicant’s Figure 3 shows a first impedance (318), a second impedance (320), a first transistor (328), a second transistor (330), a third transistor (332) coupled to the first impedance, and a fourth transistor (334) coupled to the second impedance. Applicant’s Figure 3 does not show an additional fifth transistor coupled to the first and second impedance. For the purposes of examination, the limitation has been treated as “a fifth transistor coupled to the first and second transistors” to agree with Applicant’s Figure 3.
Claim 2 recites “third transistor.” Examiner notes that Applicant’s Figure 3 shows that the low voltage node (310) is connected to the third replica transistor (338), not the third transistor (332). For the purposes of examination, the limitation has been treated as “the third replica transistor” to agree with Applicant’s Figure 3.
Claim 2 further recites “the low voltage node is coupled to the…seventh transistor, and eighth transistor.” Examiner notes that Applicant’s Figure 3 shows a seventh transistor (324) and eighth transistor (326) coupled to the high voltage node (302). Applicant’s Figure 3 does not show the seventh and eighth transistor coupled to the low voltage node (310). For the purposes of examination, the limitation has been treated as “the low voltage node is coupled to the…fifth transistor, and sixth transistor” to agree with Applicant’s Figure 3.
Claims 3-10 are rejected for being dependent on claims 1 and 2.
Claim 13 recites “respective first drains or sources of the first and second transistors being coupled to the second drain or source of the first transistor.” Examiner notes that Applicant’s Figure 3 shows a first plurality of transistors (322, 324, 326) and a second plurality of transistors (336, 338, 340, 342). Applicant’s Figure 3 does not show respective first drains or sources of the first and second transistors (322, 324) being coupled to the second drain or source of the first transistor (322). For the purposes of examination, the limitation has been treated as “respective first drains or sources of the fourth and fifth transistors being coupled to the second drain or source of the first transistor” to agree with Applicant’s Figure 3.
Claim 14 recites “respective first drains or sources of the second and ninth and eleventh transistors being coupled to a second drain or source of the third transistor.” Examiner notes that Applicant’s Figure 3 shows second (326), third (324), eighth (328), ninth (330), tenth (332) and eleventh (334) transistors. Figure 3 does not show that the first drain or source of the second transistor (326) is coupled to the second drain or source of the third transistor (324). For the purposes of examination, the limitation has been treated as “respective first drains or sources of the ninth and eleventh transistors being coupled to a second drain or source of the second transistor” to agree with Applicant’s Figure 3.
Claims 15-20 are rejected for being dependent on claim 13.
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 1-10 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 1 recites the limitation "the third and fourth impedance.”. There is insufficient antecedent basis for this limitation in the claim. For the purposes of examination, the limitation has been treated as “the third and fourth transistors.”
Claims 2-10 are rejected for being dependent on claim 1.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 11 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Su et al. (U.S. Patent 6,242,963, hereafter Su).
Claim 11: Su teaches a current mixer (Figure 2) comprising:
a high voltage node (connected to 4 and 6);
a low voltage node (connected to 34);
a first plurality of transistors (20, 24) coupled to the high voltage node;
a second plurality of transistors (8, 10) coupled to the low voltage node; and
a third plurality of transistors (12, 14, 16, 18) coupled to the first plurality of transistors and to the second plurality of transistors.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1-4, 9, 10 and 12-17 is/are rejected under 35 U.S.C. 103 as being unpatentable over Su in view of Chakraborty et al. (U.S. Patent 11,777,496, hereafter Chakraborty).
Claim 1: Su teaches a current mixer (Figure 2) comprising:
a mixing section including a first impedance (22),
a second impedance (26),
a first transistor (12) coupled to the first impedance,
a second transistor (14) coupled to the second impedance,
a third transistor (16) coupled to the first impedance,
a fourth transistor (18) coupled to the second impedance,
a fifth transistor (8) coupled to the first and second transistors,
a sixth transistor (10) coupled to the third and fourth transistors,
a seventh transistor (20) coupled to the first impedance and to the first transistor, and
an eighth transistor (24) coupled to the second impedance and fourth transistor;
and a replica path (32; column 3 lines 21-24).
Su does not specifically teach the details of the replica path.
Chakraborty teaches a replica path (420; Figure 4 and column 17 lines 52-62) including a first replica transistor (432), a second replica transistor (434) coupled to the first replica transistor, and a third replica transistor (436) coupled to the first replica transistor (via 434).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to use the replica path taught by Chakraborty in the circuit of Su to provide a regulated linear voltage (column 18 lines 1-5).
Claim 2: The combined circuit further teaches that a high voltage node (connected to 4 and 6 in Su) and a low voltage node (connected to 34 in Su), wherein the high voltage node is coupled to the seventh transistor (20), the eighth transistor (24), and the first replica transistor (432 of Chakraborty via 430), and the low voltage node is coupled to the second replica transistor (434 of Chakraborty via 436), the third replica transistor (436 of Chakraborty), the fifth transistor (8 of Su via 34), and the sixth transistor (10 of Su via 34).
Claim 3: The combined circuit further teaches a first local oscillator connection (LO+) coupled to a gate of the first transistor and a gate of the fourth transistor and configured to provide a first time-varying signal to the gate of the first transistor and the gate of the fourth transistor.
Claim 4: The combined circuit further teaches a second local oscillator (LO-) connection coupled to a gate of the second transistor and a gate of the third transistor and configured to provide a second time-varying signal to the gate of the second transistor and to the gate of the third transistor.
Claim 9: The combined circuit further teaches that the first time-varying signal and the second time-varying signal are substantially identical and 180 degrees out of phase (column 3 lines 8-10).
Claim 10: The combined circuit further teaches a capacitor coupled in parallel with the first replica transistor (inherent drain-source capacitance of 432) between a high voltage node (VDD via 430), and the second replica transistor (434) and the third replica transistor (436 via 434).
Claim 12: Su teaches the limitations of claim 11 above. Su further teaches the first plurality of transistors includes a second transistor (24) and a third transistor (20), respective first drains or sources of the second transistor, and third transistor being coupled to the high voltage node.
Su does not specifically teach a first transistor having a first drain or source coupled to the high voltage node.
Chakraborty teaches a replica circuit (420; Figure 4 and column 17 lines 52-62) comprising a first transistor (432) having a first drain or source coupled to the high voltage node (VDD via 430).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to use the replica path taught by Chakraborty in the circuit of Su to provide a regulated linear voltage (column 18 lines 1-5).
Claim 13: The combined circuit further teaches that the second plurality of transistors includes a fourth transistor (434 of Chakraborty), a fifth transistor (436 of Chakraborty), a sixth transistor (8 of Su), and a seventh transistor (10 of Su), respective first drains or sources of the fourth and fifth transistors being coupled to a second drain or source of the first transistor (432 of Chakraborty), and respective second drains of the fourth, fifth, sixth, and seventh transistors being coupled to the low voltage node.
Claim 14. The combined circuit further teaches that the third plurality of transistors includes an eighth transistor (12 of Su), ninth transistor (14), tenth transistor (16), and eleventh transistor (18), respective first drains or sources of the eighth and tenth transistor being coupled to a second drain or source of the third transistor (20), respective first drains or sources of the ninth and eleventh transistors being coupled to a second drain or source of the second transistor (24), respective second drains or sources of the eighth and ninth transistors being coupled to a first drain or source of the sixth transistor (8), and respective second drains or sources of the tenth and eleventh transistors being coupled to a first drain or source of the seventh transistor (10).
Claim 15: The combined circuit further teaches a first impedance (26 of Su) and a second impedance (22 of Su), the first impedance coupled to each drain and source of the second transistor (24), and the second impedance coupled to each drain and source of the third transistor (22).
Claim 16: The combined circuit further teaches a first node configured to provide a first time-varying signal to respective gates of the eight transistor and the eleventh transistor (LO+).
Claim 17: The combined circuit further teaches a second node configured to provide a second time-varying signal to respective gates of the ninth transistor and tenth transistor (LO-).
Allowable Subject Matter
Claims 5-8 and 18-20 would be allowable if rewritten to overcome the rejection(s) under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), 1st and 2nd paragraphs, set forth in this Office action and to include all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
Regarding claim 5, the prior art does not fairly teach or suggest a first RF connection coupled to a gate of the fifth transistor and a gate of the second replica transistor, and configured to provide a third time-varying signal to the gate of the fifth transistor and the gate of the second replica transistor. Claim 18 is objected to for similar reasons.
Claims 6-8, 19 and 20 are objected to merely for being dependent on claims 5 and 18.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure: U.S. Patent 6,316,996 (Figure 4).
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/C.J.O/Examiner, Art Unit 2836
/Menatoallah Youssef/SPE, Art Unit 2836
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