DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Status of Claims
Claims 1-20 are pending, of which all pending claims are rejected.
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the claims at issue are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); and In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on a nonstatutory double patenting ground provided the reference application or patent either is shown to be commonly owned with this application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
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Claims 1-20 are rejected on the ground of nonstatutory double patenting as being unpatentable over Claims of US Patent No.11,469,776. Although the claims at issue are not identical, they are not patentably distinct from each other because Claims 1-20 of the present application are substantially equivalent (e.g., Claim 1: representative - an apparatus, comprising: at least one memory having processor-executable instructions stored thereon; and at least one processor configured to execute the processor-executable instructions to: obtain an input sequence to be decoded; and perform decoding on the input sequence based on a low density parity check (LDPC) matrix H; wherein the LDPC matrix H is determined according to a base matrix and a lifting factor Z, where Z is a positive integer; wherein the base matrix comprises elements in m rows with row index i = 0,1,2,...(m-1) of a first matrix, wherein the first matrix comprises 46 rows with row index i=0, 1,2,...45 and 68 columns with column index j=0,1,2,...67, and 5<m<46; and wherein the first matrix comprises the following elements (i, j) of row i and column j, i is a row index and j is a column index, each of the elements (i, j) corresponds to a circular permutation matrix of size ZxZ, the circular permutation matrix equals to a matrix obtained by circularly shifting an identity matrix of size ZxZ to the right for Pij times, wherein Pij = mod (V1j,Z), Vij is a value corresponding to each of the elements (i, j), each of the elements (i, j) and corresponding Vj are as follows, and any other element in the first matrix corresponds to an all-zero matrix of size ZxZ.) to claims of US Patent No. 11,469,776 (e.g., claim 7: representative- a communication apparatus comprising at least one processor and at least one non-transitory memory having processor-executable instructions stored thereon, wherein the at least one processor is configured to execute the processor-executable instructions to perform the following: obtaining an input sequence; decoding the input sequence using a matrix H to obtain a decoded sequence, wherein the decoded sequence comprises K bits, and wherein K>1; and outputting the decoded sequence; wherein the matrix H is determined according to a base matrix and a lifting factor Z, and wherein Z is a positive integer; wherein the base matrix comprises a plurality of rows and columns of a first matrix; wherein each element in the first matrix corresponds to a respective row index i and a respective column index j, where i≥0 and j≥0; wherein each element in the first matrix is either a zero-element or a non-zero-element; wherein each zero-element in the first matrix corresponds to an all-zero matrix of size Z×Z in the matrix H, and each non-zero-element at row i and column j corresponds to a circular permutation matrix of size Z×Z, wherein the circular permutation matrix is equal to a matrix obtained by circularly shifting an identity matrix of size Z×Z to the right for P.sub.i,j times, wherein P.sub.i,j=mod (V.sub.i,j,Z), wherein V.sub.i,j is a value corresponding to a non-zero-element at row i and column j).
Claims 1-20 are rejected on the ground of nonstatutory double patenting as being unpatentable over Claims of US Patent No. 12,323,162. Although the claims at issue are not identical, they are not patentably distinct from each other because Claims 1-20 of the present application are substantially equivalent (e.g., Claim 1: representative - an apparatus, comprising: at least one memory having processor-executable instructions stored thereon; and at least one processor configured to execute the processor-executable instructions to: obtain an input sequence to be decoded; and perform decoding on the input sequence based on a low density parity check (LDPC) matrix H; wherein the LDPC matrix H is determined according to a base matrix and a lifting factor Z, where Z is a positive integer; wherein the base matrix comprises elements in m rows with row index i = 0,1,2,...(m-1) of a first matrix, wherein the first matrix comprises 46 rows with row index i=0, 1,2,...45 and 68 columns with column index j=0,1,2,...67, and 5<m<46; and wherein the first matrix comprises the following elements (i, j) of row i and column j, i is a row index and j is a column index, each of the elements (i, j) corresponds to a circular permutation matrix of size ZxZ, the circular permutation matrix equals to a matrix obtained by circularly shifting an identity matrix of size ZxZ to the right for Pij times, wherein Pij = mod (V1j,Z), Vij is a value corresponding to each of the elements (i, j), each of the elements (i, j) and corresponding Vj are as follows, and any other element in the first matrix corresponds to an all-zero matrix of size ZxZ.) to claims of US Patent No. 12,323,162 (e.g., claim 1: representative- an apparatus, comprising: at least one memory having processor-executable instructions stored thereon; and at least one processor configured to execute the instructions to facilitate performance of the following by the apparatus: obtaining an input sequence to be encoded; and performing low density parity check (LDPC) encoding on the input sequence by using a matrix H to obtain an encoded sequence; wherein the matrix H is determined according to a base matrix and a lifting factor Z, where Z is a positive integer; wherein the base matrix comprises elements in m rows with row index i=0,1,2, . . . (m−1) of a first matrix, wherein the first matrix comprises 46 rows with row index i=0, 1,2, . . . 45 and 68 columns with column index j=0,1,2, . . . 67, and 5≤m≤46; and wherein the first matrix comprises the following elements (i, j) of row i and column j, i is a row index and j is a column index, each of the elements (i, j) corresponds to a circular permutation matrix of size Z×Z, the circular permutation matrix equals to a matrix obtained by circularly shifting an identity matrix of size Z×Z to the right for P.sub.i,j times, wherein P.sub.i,j=mod (V.sub.i,j,Z), V.sub.i,j is a value corresponding to each of the elements (i, j), each of the elements (i, j) and corresponding V.sub.i,j are as follows, and any other element in the first matrix corresponds to an all-zero matrix of size Z×Z), directed to encode data via H matrix, as one of ordinary skill in the art would be motivated to encode data before storing or transmission.
Claims 1-20 are rejected on the ground of nonstatutory double patenting as being unpatentable over Claims of US Patent No.11,770,135. Although the claims at issue are not identical, they are not patentably distinct from each other because Claims 1-20 of the present application are substantially equivalent (e.g., Claim 1: representative - an apparatus, comprising: at least one memory having processor-executable instructions stored thereon; and at least one processor configured to execute the processor-executable instructions to: obtain an input sequence to be decoded; and perform decoding on the input sequence based on a low density parity check (LDPC) matrix H; wherein the LDPC matrix H is determined according to a base matrix and a lifting factor Z, where Z is a positive integer; wherein the base matrix comprises elements in m rows with row index i = 0,1,2,...(m-1) of a first matrix, wherein the first matrix comprises 46 rows with row index i=0, 1,2,...45 and 68 columns with column index j=0,1,2,...67, and 5<m<46; and wherein the first matrix comprises the following elements (i, j) of row i and column j, i is a row index and j is a column index, each of the elements (i, j) corresponds to a circular permutation matrix of size ZxZ, the circular permutation matrix equals to a matrix obtained by circularly shifting an identity matrix of size ZxZ to the right for Pij times, wherein Pij = mod (V1j,Z), Vij is a value corresponding to each of the elements (i, j), each of the elements (i, j) and corresponding Vj are as follows, and any other element in the first matrix corresponds to an all-zero matrix of size ZxZ.) to claims of US Patent No. 11,770,135 (e.g., Claim 8: representative- 8. an apparatus for wireless communication, comprising at least one processor coupled to a memory having instructions stored thereon, wherein the at least one processor is configured to execute the instructions to perform the following: encoding an input sequence using a matrix H to obtain an encoded sequence, wherein the input sequence comprises K bits, wherein the encoded sequence comprises N bits, and wherein K>1 and N>1; and outputting the encoded sequence; wherein the matrix H is determined according to a base matrix and a lifting factor Z, and wherein Z is a positive integer; wherein the base matrix comprises a plurality of rows and columns of a first matrix; wherein each element in the first matrix corresponds to either an all-zero matrix of size Z×Z or a circular permutation matrix of size Z×Z, wherein a respective circular permutation matrix corresponding to a respective element at row i and column j of the first matrix is equal to a matrix obtained by circularly shifting an identity matrix of size Z×Z to the right for P.sub.i,j times, wherein P.sub.i,j=mod (V.sub.i,j,Z), wherein a plurality of V.sub.i,j values for respective elements of the first matrix corresponding to respective circular permutation matrices of size Z×Z), directed to encode data via H matrix, as one of ordinary skill in the art would be motivated to encode data before storing or transmission.
Claims 1-20 are rejected on the ground of nonstatutory double patenting as being unpatentable over Claims of US Patent No.10,784,893. Although the claims at issue are not identical, they are not patentably distinct from each other because Claims 1-20 of the present application are substantially equivalent (e.g., Claim 1: representative - an apparatus, comprising: at least one memory having processor-executable instructions stored thereon; and at least one processor configured to execute the processor-executable instructions to: obtain an input sequence to be decoded; and perform decoding on the input sequence based on a low density parity check (LDPC) matrix H; wherein the LDPC matrix H is determined according to a base matrix and a lifting factor Z, where Z is a positive integer; wherein the base matrix comprises elements in m rows with row index i = 0,1,2,...(m-1) of a first matrix, wherein the first matrix comprises 46 rows with row index i=0, 1,2,...45 and 68 columns with column index j=0,1,2,...67, and 5<m<46; and wherein the first matrix comprises the following elements (i, j) of row i and column j, i is a row index and j is a column index, each of the elements (i, j) corresponds to a circular permutation matrix of size ZxZ, the circular permutation matrix equals to a matrix obtained by circularly shifting an identity matrix of size ZxZ to the right for Pij times, wherein Pij = mod (V1j,Z), Vij is a value corresponding to each of the elements (i, j), each of the elements (i, j) and corresponding Vj are as follows, and any other element in the first matrix corresponds to an all-zero matrix of size ZxZ.) to claims of US Patent No. 10,784,893 (e.g., claim 9: representative- a communication apparatus comprising at least one processor configured to: obtain an input sequence, wherein the input sequence comprises K bits, and wherein K>1: encode the input sequence using a matrix H to obtain an encoded sequence, wherein the encoded sequence comprises N bits, and wherein N>1; and output the encoded sequence; wherein the matrix H is determined according to a base matrix and a lifting factor Z, and wherein Z is a positive integer; wherein the base matrix comprises m rows and n columns, wherein m and n are integers; wherein each element in the base matrix corresponds to a respective row index i and a respective column index j, where 0≤i<m and 0≤j<n; wherein each element in the base matrix is either a zero-element or a non-zero-element; wherein each zero-element in the base matrix corresponds to an all-zero matrix of size Z×Z in the matrix H, and each non-zero-element at row i and column j corresponds to a circular permutation matrix of size Z×Z, wherein the circular permutation matrix is equal to a matrix obtained by circularly shifting an identity matrix of size Z×Z to the right for P.sub.i,j times, wherein P.sub.i,j=mod (V.sub.i,j,Z), wherein V.sub.i,j is a value corresponding to a non-zero-element at row i and column j), directed to encode data via H matrix, as one of ordinary skill in the art would be motivated to encode data before storing or transmission.
Allowable Subject Matter
Claims 1-20 would be allowable if the pending obviousness double patenting rejection and all remaining pending objections and rejections (if any) are overcome.
Citation of Pertinent Prior Art
It is noted that any citations to specific, pages, columns, lines, or figures in the prior art references and any interpretation of the reference should not be considered to be limiting in any way. A reference is relevant for all it contains and may be relied upon for all that it would have reasonably suggested to one having ordinary skill in the art. See MPEP 2123.
Conclusion
The following prior arts made of record, listed on form PTO-892, and not relied upon, if any, are considered pertinent to applicant's disclosure:
Li et al. (US 11,683,051 B2) teaches a method and an apparatus for data processing with structured LDPC codes. The method includes: obtaining a code block size for structured LDPC coding; determining a coding expansion factor z based on at least one of the code block size, a parameter kb of a basic check matrix, a positive integer value p or the basic check matrix having mb rows and nb columns; and encoding a data sequence to be encoded, or decoding a data sequence to be decoded, based on the basic check matrix and the coding expansion factor. The present disclosure is capable of solving the problem in the related art associated with low flexibility in data processing with LDPC coding and improving the flexibility in data processing with LDPC coding.
When amending the claims, Applicants are respectfully requested to indicate the portion(s) of the specification which dictate(s) the structure relied on for proper interpretation and also to verify and ascertain the metes and bounds of the claimed invention.
Contact Information
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ENAMUL MD KABIR whose telephone number is (571)270-7256. The examiner can normally be reached on 10:00-6:30 pm.
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/ENAMUL M KABIR/
Examiner, Art Unit 2112
/ALBERT DECADY/Supervisory Patent Examiner, Art Unit 2112
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