DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Priority
Applicant’s claim for the benefit of a provisional application 63/660,139 filed on 06/14/2024 is acknowledged.
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 04/30/2025. The submission is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Allowable Subject Matter
Claim 3-12, 15-20 objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
REASONS FOR ALLOWANCE
For claim 3, the prior art does not teach the limitations when view in combination with limitations from the base claims from which claim 3 depends.
For claim 4, the prior art does not teach the limitations when view in combination with limitations from the base claims from which claim 4 depends. Additionally, claim 4 is allowable based on dependency from claim 3.
For claim 5, the prior art does not teach the limitations when view in combination with limitations from the base claims from which claim 5 depends. Additionally, claim 5 is allowable based on dependency from claim 4.
For claim 6, the prior art does not teach the limitations when view in combination with limitations from the base claims from which claim 6 depends. Additionally, claim 6 is allowable based on dependency from claim 4.
For claim 7, the prior art does not teach the limitations when view in combination with limitations from the base claims from which claim 7 depends. Additionally, claim 7 is allowable based on dependency from claim 4.
For claim 8, the prior art does not teach the limitations when view in combination with limitations from the base claims from which claim 8 depends.
For claim 9, the prior art does not teach the limitations when view in combination with limitations from the base claims from which claim 9 depends. Additionally, claim 9 is allowable based on dependency from claim 8.
For claim 10, the prior art does not teach the limitations when view in combination with limitations from the base claims from which claim 10 depends. Additionally, claim 10 is allowable based on dependency from claim 9.
For claim 11, the prior art does not teach the limitations when view in combination with limitations from the base claims from which claim 11 depends. Additionally, claim 11 is allowable based on dependency from claim 9.
For claim 12, the prior art does not teach the limitations when view in combination with limitations from the base claims from which claim 12 depends. Additionally, claim 12 is allowable based on dependency from claim 9.
For claim 15, the prior art does not teach the limitations when view in combination with limitations from the base claims from which claim 15 depends.
For claim 16, the prior art does not teach the limitations when view in combination with limitations from the base claims from which claim 16 depends. Additionally, claim 16 is allowable based on dependency from claim 15.
For claim 17, the prior art does not teach the limitations when view in combination with limitations from the base claims from which claim 17 depends. Additionally, claim 17 is allowable based on dependency from claim 15.
For claim 18, the prior art does not teach the limitations when view in combination with limitations from the base claims from which claim 18 depends. Additionally, claim 18 is allowable based on dependency from claim 15.
For claim 19, the prior art does not teach the limitations when view in combination with limitations from the base claims from which claim 19 depends.
For claim 20, the prior art does not teach the limitations when view in combination with limitations from the base claims from which claim 20 depends. Additionally, claim 20 is allowable based on dependency from claim 19.
Any comments considered necessary by applicant must be submitted no later than the payment of the issue fee and, to avoid processing delays, should preferably accompany the issue fee. Such submissions should be clearly labeled “Comments on Statement of Reasons for Allowance.”
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1, 13 is/are rejected under 35 U.S.C. 103 as being unpatentable over Benisty (US 20240095165), in view of Ballapuram (US 20230333976).
Regarding Claim 1, Benisty teaches
A method comprising: receiving, by a controller of a storage device, a command with a corresponding logical page number (LPN); (Benisty [0002] The data is provided by a host system which addresses each Logical Block with a logical block address (LBA). When the host system reads a particular LBA, the SSD looks up the PBA in the L2P table in order to retrieve the logical block from the NVM and send it to the host system [0026] a memory unit of NVM 110 may receive data and a message from controller 108 that instructs the memory unit to store the data. Similarly, the memory unit may receive a message from controller 108 that instructs the memory unit to retrieve data.) (i.e., LBA is LPN)
mapping, by the controller, the LPN to a physical page number (PPN) in a storage medium of the storage device based on a logical-to-physical (L2P) look-up table (LUT) comprising most significant bits (MSBs) of a PPN entry; (Benisty [0002] The mapping from LBA to the PBA is stored in a table referred to herein as a logical to physical (L2P) table. When the host system reads a particular LBA, the SSD looks up the PBA in the L2P table in order to retrieve the logical block from the NVM and send it to the host system. [0007] a memory device; and a controller coupled to the memory device, wherein the controller is configured to: determine most significant bits (MSBs) for a physical address of the memory device) (i.e., PBA is PPN)
generating, by the controller, least significant bits (LSBs) of the PPN entry from the LPN based on a hash function; (Benisty [0007] least significant bits (LSBs) for a physical address of the memory device)
and determining, by the controller, the PPN for the command based on the MSBs, the LSBs, and a meta area in the storage medium. (Benisty [0007] the controller is configured to: determine most significant bits (MSBs) and least significant bits (LSBs) for a physical address of the memory device, store the MSBs in a L2P table; and store the LSBs in a table distinct from the L2P table [0008] and configure a metadata table to store remaining bits of the physical addresses with metadata, wherein the metadata table is distinct from the L2P table, and wherein the remaining data corresponds to LSBs of the physical addresses.) (i.e., metadata table is a meta area)
Benisty does not teach generating, by the controller, least significant bits (LSBs) of the PPN entry from the LPN based on a hash function
However, Ballapuram teaches generating, by the controller, [a portion] of the PPN entry from the LPN based on a hash function (Ballapuram [0005] a controller configured to: compute a hash value by applying a hash function to the logical address, the hash value providing a first portion of a first physical address)
Benisty and Ballapuram are analogous art because they are from the same field of memory control. Before the effective filing date of the invention, it would have been obvious to a person of ordinary skill in the art, having the teaching of Benisty and Ballapuram to modify the Benisty‘s LSB that is in a metadata table separate from MSB in L2P table with Ballapuram’s teaching of applying a hash function to the logical address to generate a portion of physical address so that LSB is generated from applying a hash function to logical address and stored metadata in the metadata table. The motivation for doing so would be that (Ballapuram [0004]) shorter physical-address entries in the L2P table beneficially enable nearly optimal and aligned accesses to the DRAM and a more-optimal use of the DRAM capacity.
Regarding Claim 13, Benisty teaches
A storage device comprising: a controller; and a non-transitory computer readable storage medium storing instructions that, when executed, cause the controller to: (Benisty [0006] a data storage device comprises: a memory device; and a controller coupled to the memory device, wherein the controller is configured to)
receive a command with a corresponding logical page number (LPN); (Benisty [0002] The data is provided by a host system which addresses each Logical Block with a logical block address (LBA). When the host system reads a particular LBA, the SSD looks up the PBA in the L2P table in order to retrieve the logical block from the NVM and send it to the host system [0026] a memory unit of NVM 110 may receive data and a message from controller 108 that instructs the memory unit to store the data. Similarly, the memory unit may receive a message from controller 108 that instructs the memory unit to retrieve data.) (i.e., LBA is LPN)
map the LPN to a physical page number (PPN) in the storage medium based on a logical-to-physical (L2P) look-up table (LUT) comprising most significant bits (MSBs) of a PPN entry; (Benisty [0002] The mapping from LBA to the PBA is stored in a table referred to herein as a logical to physical (L2P) table. When the host system reads a particular LBA, the SSD looks up the PBA in the L2P table in order to retrieve the logical block from the NVM and send it to the host system. [0007] a memory device; and a controller coupled to the memory device, wherein the controller is configured to: determine most significant bits (MSBs) for a physical address of the memory device) (i.e., PBA is PPN)
generate least significant bits (LSBs) of the PPN entry from the LPN based on a hash function; (Benisty [0007] least significant bits (LSBs) for a physical address of the memory device)
and determine the PPN for the command based on the MSBs, the LSBs, and a meta area in the storage medium. (Benisty [0007] the controller is configured to: determine most significant bits (MSBs) and least significant bits (LSBs) for a physical address of the memory device, store the MSBs in a L2P table; and store the LSBs in a table distinct from the L2P table [0008] and configure a metadata table to store remaining bits of the physical addresses with metadata, wherein the metadata table is distinct from the L2P table, and wherein the remaining data corresponds to LSBs of the physical addresses.) (i.e., metadata table is a meta area)
Benisty does not teach
and a non-transitory computer readable storage medium storing instructions that, when executed, cause the controller to: generate least significant bits (LSBs) of the PPN entry from the LPN based on a hash function;
However, Ballapuram teaches
and a non-transitory computer readable storage medium storing instructions that, when executed, cause the controller to: (Ballapuram [0014] the functions associated with the controller can be performed by hardware (for example, analog or digital circuits), a combination of hardware and software (for example, program code or firmware stored in a non-transitory computer-readable medium that is executed by a processor or control circuitry))
generate [a portion] of the PPN entry from the LPN based on a hash function; (Ballapuram [0005] a controller configured to: compute a hash value by applying a hash function to the logical address, the hash value providing a first portion of a first physical address)
Benisty and Ballapuram are analogous art because they are from the same field of memory control. Before the effective filing date of the invention, it would have been obvious to a person of ordinary skill in the art, having the teaching of Benisty and Ballapuram to modify the Benisty‘s LSB that is in a metadata table separate from MSB in L2P table with Ballapuram’s teaching of applying a hash function to the logical address to generate a portion of physical address so that LSB is generated from applying a hash function to logical address and stored metadata in the metadata table. The motivation for doing so would be that (Ballapuram [0004]) shorter physical-address entries in the L2P table beneficially enable nearly optimal and aligned accesses to the DRAM and a more-optimal use of the DRAM capacity.
Claim(s) 2, 14 is/are rejected under 35 U.S.C. 103 as being unpatentable over Benisty (US 20240095165), in view of Ballapuram (US 20230333976), further in view of Bo (US 20240403209).
Regarding Claim 2, Benisty and Ballapuram teach
Benisty teaches wherein the command is a read command and determining the PPN comprises: obtaining data entries from the storage medium based on the MSBs of the L2P LUT; (Benisty [0002] When the host system reads a particular LBA, the SSD looks up the PBA in the L2P table in order to retrieve the logical block from the NVM and send it to the host system. [0021] The most significant bits (MSB) of the L2P are stored in the DRAM)
performing a conflict check on the data entries based on a centralized mapping table in the meta area of the storage medium; (Benisty [0050] a data storage device comprises: memory means; and a controller coupled to the memory means, wherein the controller is configured to: configure a metadata table to store remaining bits of the physical addresses with metadata, wherein the metadata table is distinct from the L2P table, and wherein the remaining data corresponds to least significant bits (LSBs) of the physical addresses.) (i.e., metadata table on the storage device is a centralized mapping table)
and outputting a data entry from the data entries that passes the conflict check [data storage based on address mapping] (Benisty [0002] When the host system reads a particular LBA, the SSD looks up the PBA in the L2P table in order to retrieve the logical block from the NVM and send it to the host system.)
Benisty-Ballapuram teaches apply hash function to logical address (Ballapuram [0005] compute a hash value by applying a hash function to the logical address, the hash value providing a first portion of a first physical address), but Benisty-Ballapuram does not teach hash collision and address conflict caused by hash collision.
Benisty-Ballapuram does not teach performing a conflict check on the data entries based on a centralized mapping table in the meta area of the storage medium; and outputting a data entry from the data entries that passes the conflict check.
However, Bo teaches performing a conflict check on the data entries based on [if hash value already exists] (Bo [0072] after the first hash value is obtained, a collision state corresponding to the first hash value is determined. if the first hash value is not included in the target hash bucket, the first hash value does not conflict)
the data entries that passes the conflict check. (Bo [0072] after the first hash value is obtained, a collision state corresponding to the first hash value is determined. if the first hash value is not included in the target hash bucket, the first hash value does not conflict)
Benisty, Ballapuram and Bo are analogous art because they are from the same field of memory control. Before the effective filing date of the invention, it would have been obvious to a person of ordinary skill in the art, having the teaching of Benisty, Ballapuram and Bo to modify the Benisty-Ballapuram‘s generating LSB using hash function with Bo’s hash value conflict check. The motivation for doing so would be (Bo [0069-0070]) detecting a collision state of the first hash value. if the collision state is a first state…a mapping relationship is established between the first hash value and the target logical address.
Regarding Claim 14, Benisty and Ballapuram teach
Benisty teaches wherein the command is a read command and, in determining the PPN,
the instructions further cause the controller to: obtain data entries from the storage medium based on the MSBs of the L2P LUT; (Benisty [0002] When the host system reads a particular LBA, the SSD looks up the PBA in the L2P table in order to retrieve the logical block from the NVM and send it to the host system. [0021] The most significant bits (MSB) of the L2P are stored in the DRAM)
perform a conflict check on the data entries based on a centralized mapping table in the meta area of the storage medium; (Benisty [0050] a data storage device comprises: memory means; and a controller coupled to the memory means, wherein the controller is configured to: configure a metadata table to store remaining bits of the physical addresses with metadata, wherein the metadata table is distinct from the L2P table, and wherein the remaining data corresponds to least significant bits (LSBs) of the physical addresses.) (i.e., metadata table on the storage device is a centralized mapping table)
and output a data entry from the data entries that passes the conflict check [data storage based on address mapping] (Benisty [0002] When the host system reads a particular LBA, the SSD looks up the PBA in the L2P table in order to retrieve the logical block from the NVM and send it to the host system.)
Benisty-Ballapuram teaches apply hash function to logical address (Ballapuram [0005] compute a hash value by applying a hash function to the logical address, the hash value providing a first portion of a first physical address), but Benisty-Ballapuram does not teach hash collision and address conflict caused by hash collision.
Benisty-Ballapuram does not teach perform a conflict check on the data entries based on a centralized mapping table in the meta area of the storage medium; and output a data entry from the data entries that passes the conflict check.
However, Bo teaches perform a conflict check on the data entries based on [if hash value already exists] (Bo [0072] after the first hash value is obtained, a collision state corresponding to the first hash value is determined. if the first hash value is not included in the target hash bucket, the first hash value does not conflict)
the data entries that passes the conflict check. (Bo [0072] after the first hash value is obtained, a collision state corresponding to the first hash value is determined. if the first hash value is not included in the target hash bucket, the first hash value does not conflict)
Benisty, Ballapuram and Bo are analogous art because they are from the same field of memory control. Before the effective filing date of the invention, it would have been obvious to a person of ordinary skill in the art, having the teaching of Benisty, Ballapuram and Bo to modify the Benisty-Ballapuram‘s generating LSB using hash function with Bo’s hash value conflict check. The motivation for doing so would be (Bo [0069-0070]) detecting a collision state of the first hash value. if the collision state is a first state…a mapping relationship is established between the first hash value and the target logical address.
Relevant Prior Art
The prior art made of record and not relied upon is considered pertinent to applicant’s disclosure.
Conklin (US 20210073141) teaches reducing forward mapping table size using hashing.
Conclusion
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/WEI MA/Examiner, Art Unit 2135
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