DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 103
The text of those sections of Title 35, U.S. Code not included in this action can be found in a prior Office action.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-4, 6, 11-14, 16 are rejected under 35 U.S.C. 103 as being unpatentable over Lee et al (US 20250244888, Lee) in view of Li et al (US 10078453, Li).
As to claim 1, Lee discloses a method for managing memory in a computing system, comprising:
generating a virtual node (par. 140, “a RAID set”) by combining two or more physical nodes (“storage devices 130”) coupled to a compute express link (CXL) switch (fig. 1 CXL switch 120).
Lee does not disclose the step of identifying a physical address of data stored in the memory based on an offset between address ranges of the two or more physical nodes. In the same field of art (peripheral configuration), Li discloses a method for managing read/write operations in a hybrid memory device system (abstract). In one embodiment, Li further discloses the step of identifying a physical address of data stored in a memory based on an offset between address ranges of the two or more physical nodes (fig. 4, 7 s706). Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of Lee and Li, by identifying a physical address of data stored in the memory based on an offset between address ranges of the two or more physical nodes. The motivation is to improve the capacity of the system (col 1 ln 15-30).
As to claim 2, Lee/Li discloses the method of claim 1, wherein the two or more physical nodes expose a distinct address range (Li, col 6 ln 10-25. Note memory devices 106, 108 are shared between applications 110) that corresponds to a shared memory region in a CXL memory expander (Lee, fig. 13, CXL switch 120).
As to claim 3, Lee/Li discloses the method of claim 1, further comprising maintaining a memory allocation table that associates one or more pages in the shared memory region with the virtual node (Lee, fig. 12; Li, fig. 4).
As to claim 4, Lee/Li discloses the method of claim 1, wherein the offset is determined based on a difference in base addresses assigned to the two or more physical nodes (Li, col 6 ln 10-25 “a first and last addresses in the range”).
As to claim 6, Lee/Li discloses the method of claim 1, further comprising retrieving a memory page using the physical address (Lee, par 144-145).
As to claims 11-14, 16, all the same elements of claims 1-4, 6 are listed, but in an apparatus form. Therefore, the supporting rationale of the rejection to claims 1-4, 6 applies equally to claims 11-14, 16.
Claims 5, 7-9, 15, 17-19 are rejected under 35 U.S.C. 103 as being unpatentable over Lee in view of Li and further in view of Muntz (US 20250123985).
As to claim 5, Lee/Li discloses the method of claim 1, but does not disclose the limitations in claim 5. In the same field of art (peripheral configuration), Muntz discloses an autonomous and integrated translator for local server bus operations (abstract). In one embodiment, Muntz further discloses two or more physical nodes are coupled to the CXL switch (fig. 1 switch 102) through two or more CXL host adapters, respectively (host fabric adapters 114, par. 30). Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of Lee/Li and Muntz, by comprising the two or more physical nodes coupled to the CXL switch through two or more CXL host adapters, respectively. The motivation is to improve cost-efficiency of the system (par. 3).
As to claim 7, Lee/Li discloses the method of claim 1, but does not disclose the limitations in claim 7. In the same field of art (peripheral configuration), Chen discloses an electronic device migrates the data of the first process in a volatile memory to a non-volatile memory in the running process of the system (par. 7). In one embodiment, Chen discloses the step of updating a page middle directory (PMD) to point to a page table entry (PTE) (fig. 6, 7, par. 132-134) when a process is migrated between central processing units (CPU) nodes (fig. 5b). Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of Lee/Li and Chen, by further comprising updating a page middle directory (PMD) to point to a page table entry (PTE) when a process is migrated between central processing units (CPU) nodes. The motivation is to improve the performance of the system (par. 4).
As to claim 8, Lee/Li discloses the method of claim 1, but does not disclose the limitations in claim 8. In the same field of art (peripheral configuration), Chen discloses an electronic device migrates the data of the first process in a volatile memory to a non-volatile memory in the running process of the system (par. 7). In one embodiment, Chen discloses the step of updating a page middle directory (PMD) to point to a page table entry (PTE) (fig. 6, 7, par. 132-134) when a process is migrated between central processing units (CPU) nodes (fig. 5b). Since Lee/Li discloses a base address corresponding to a local CXL host adapter (Li, col 6 ln 10-25 “a first and last addresses in the range”), it therefore would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of Lee/Li and Chen, by further comprising updating a page middle directly (PMD) entry to point to a page table entry (PTE) associated with a base address corresponding to a local CXL host adapter when a process is migrated between central processing unit (CPUs) nodes. The motivation is to improve the performance of the system (par. 4).
As to claim 9, Lee/Li discloses the method of claim 1, but does not disclose the limitations in claim 9. In the same field of art (peripheral configuration), Chen discloses an electronic device migrates the data of the first process in a volatile memory to a non-volatile memory in the running process of the system (par. 7). In one embodiment, Chen discloses the step of selecting a page table entry (PTE) to manage access to a shared memory region (fig. 6-7). Since Lee/Li discloses the base address corresponding to a local CXL host adapter (Li, col 6 ln 10-25 “a first and last addresses in the range”), it therefore would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of Lee/Li and Chen, by selecting a page table entry (PTE) associated with a base address corresponding to a local CXL host adapter to manage access to a shared memory region.
The motivation is to improve the performance of the system (par. 4).
As to claims 15, 17-19, all the same elements of claims 5, 7-9 are listed, but in an apparatus form. Therefore, the supporting rationale of the rejection to claims 5, 7-9 applies equally to claims 15, 17-19.
Claims 10, 20 is rejected under 35 U.S.C. 103 as being unpatentable over Lee in view of Li and further in view of Voltz (US 20200278858).
As to claim 10, Lee/Li discloses the method of claim 1, but does not disclose the limitations in claim 10. In the same field of art (peripheral configuration), Voltz discloses a technique includes communicating with a plurality of input/output (I/O) modules to cause a firmware image to be transferred to the I/O modules (abstract). In one embodiment, Voltz further discloses data stored in a memory is accessed with a reduced latency compared to accessing the memory without the virtual node (par. 20). Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of Lee/Li and Voltz, by accessing the data stored in the memory with a reduced latency compared to accessing the memory without the virtual node. The motivation is to improve the functionality of the system (par. 1).
As to claim 20, all the same elements of claim 10 are listed, but in an apparatus form. Therefore, the supporting rationale of the rejection to claim 10 applies equally to claim 20.
Conclusion
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/D.P/ Examiner, Art Unit 2184
/HENRY TSAI/ Supervisory Patent Examiner, Art Unit 2184
