Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Examiner Notes
Drawing references were left in the claims. However, the drawing references are not being given any patentable weight.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim(s) 1, is/are rejected under 35 U.S.C. 103 as being unpatentable over Del Croce et al., US20230308089 (hereinafter referred to as Del Croce), in view of Sievers et al., US20220224323 (hereinafter referred to as Sievers).
In regards to claim 1, Del Croce teaches a circuit (2nd OC protection stage 13b & power transistor T_L; [Fig. 5]) comprising: a power transistor (power transistor T_L; [Fig. 5]) having a first and a second load electrode (drain and source, respectively, of T_L; [Fig. 5]); a line (OUT line; [Fig. 5]) connected to the first or the second load electrode (implicit, the line is connected to the second load electrode; [Fig. 5]) and configured to carry a load current (current i_L; [Fig. 5]) when the power transistor is on (inherent because the transistor is in a closed position when on), the load current causing a magnetic field around the line (inherent property of current flowing); a protection circuit (2nd OC protection stage 13b; [Fig. 5]) including a comparator (amplifier AMP2; [Fig. 5]), a latch (RS-flip-flop RS_2; [Fig. 5]), and a first electronic switch (transistor T_2; [Fig. 5]), wherein the comparator is configured to signal, at its output, that the current sense signal (current sense signal; [0038]) exceeds (reaches or exceeds; [0038]) a first threshold value (second offset voltage V_OS2; [0038]), wherein the latch is configured to be set (is set; [0038]) based on an output signal of the comparator, and wherein the first electronic switch is coupled to a control electrode (gate of T_L; [Fig. 5]) of the power transistor (implicit; [Fig. 5]) and configured to discharge (discharged via… the transistor T_2; [0038]) the control electrode when the latch is set to switch the power transistor off (output a High Level (Q=1); [0038]).
Del Croce does not teach a magnetic field sensor arranged adjacent to the line to sense the magnetic field and configured to provide a current sense signal which represents the load current.
Sievers teaches a magnetic field sensor (magnetic field sensor; [0038]) arranged adjacent to the line (line carrying the current; [0038]) to sense the magnetic field (magnetic field; [0038]) and configured to provide a current sense signal (inherent sense signal of the magnetic field sensor) which represents the load current (current; [0038]).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified Del Croce in order to incorporate a magnetic field sensor arranged adjacent to the line to sense the magnetic field and configured to provide a current sense signal which represents the load current as taught by Sievers. The motivation for doing so would be an engineering design choice for measuring the current as taught by Sievers in [0038].
In regards to claim 6, Del Croce teaches the circuit of claim 1, further comprising: a reset circuit (other external circuitry; [0039]) configured to reset the latch (may be reset; [0039]) based on a logic level of an input signal (reset signal; [0039]) applied at the first input terminal.
In regards to claim 8, Del Croce teaches wherein the latch has a dominant set input (is set; [0038]).
Claim(s) 2-5 & 10 is/are rejected under 35 U.S.C. 103 as being unpatentable over Del Croce et al., US20230308089 (hereinafter referred to as Del Croce), in view of Sievers et al., US20220224323 (hereinafter referred to as Sievers), and in further view of Grasso et al., US20230275577 (hereinafter referred to as Grasso).
In regards to claim 2, Del Croce & Sievers do not teach the circuit of claim 1, further comprising, a supply circuit that is connected to a first input terminal and configured to provide an internal supply voltage between an internal supply node and an internal ground node.
Grasso teaches the circuit of claim 1, further comprising, a supply circuit (power management unit 219; [Fig. 2A]) that is connected to a first input terminal (device gate terminal 21; [Fig. 2A]) and configured to provide an internal supply voltage (appropriate voltage or currents; [0047]) between an internal supply node (terminal 213; [Fig. 2A]) and an internal ground node (return; [Fig. 2A]).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified Del Croce & Sievers in order to incorporate the circuit of claim 1, further comprising, a supply circuit that is connected to a first input terminal and configured to provide an internal supply voltage between an internal supply node and an internal ground node as taught by Grasso. The motivation for doing so would be to supply voltage to the comparator and for a reference voltage.
In regards to claim 3, Del Croce & Sievers do not teach wherein the protection circuit further includes: a second electronic switch connected between a first input terminal and the control electrode of the power transistor and configured to disconnect the first input terminal and the control electrode when the latch is set.
Grasso teaches wherein the protection circuit further includes: a second electronic switch (gate control path 28 or depletion transistor Q1; [Fig. 2A] & [Fig. 5A]) connected between a first input terminal and the control electrode of the power transistor (implicit; [Fig. 2A]) and configured to disconnect (to be at least partially switched off; [0065]) the first input terminal and the control electrode when the latch is set (control signal short; [0065]).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified Del Croce & Sievers in order to incorporate wherein the protection circuit further includes: a second electronic switch connected between a first input terminal and the control electrode of the power transistor and configured to disconnect the first input terminal and the control electrode when the latch is set as taught by Grasso. The motivation for doing so would be to isolate and protect the input gate signal from a short circuit event.
In regards to claim 4, Del Croce & Sievers do not teach the circuit of claim 3, further comprising, a supply circuit that is connected to the first input terminal and configured to provide an internal supply voltage between an internal supply node and an internal ground node.
Grasso teaches the circuit of claim 3, further comprising, a supply circuit (power management unit 219; [Fig. 2A]) that is connected to the first input terminal (device gate terminal 21; [Fig. 2A]) and configured to provide an internal supply voltage (appropriate voltage or currents; [0047]) between an internal supply node (terminal 213; [Fig. 2A]) and an internal ground node (return; [Fig. 2A]).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified Del Croce & Sievers in order to incorporate the circuit of claim 3, further comprising, a supply circuit that is connected to the first input terminal and configured to provide an internal supply voltage between an internal supply node and an internal ground node as taught by Grasso. The motivation for doing so would be to supply voltage to the comparator and for a reference voltage.
In regards to claim 5, Del Croce & Sievers do not teach wherein the internal ground node is connected to the second load electrode of the power transistor, and/or wherein the supply circuit includes a buffer capacitor connected between the internal supply node and the internal ground node.
Grasso teaches wherein the internal ground node is connected to the second load electrode of the power transistor (implicit of the connection between terminals 211 and 216; [Fig. 2A]), and/or wherein the supply circuit includes a buffer capacitor connected between the internal supply node and the internal ground node.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified Del Croce & Sievers in order to incorporate wherein the internal ground node is connected to the second load electrode of the power transistor, and/or wherein the supply circuit includes a buffer capacitor connected between the internal supply node and the internal ground node as taught by Grasso. The motivation for doing so would be to supply voltage to the comparator and for a reference voltage.
In regards to claim 10, Del Croce & Sievers do not teach wherein the circuit is included in a chip package which has only three separate terminals and/or no dedicated supply terminals.
Grasso teaches wherein the circuit is included in a chip package (transistor device 20, same package; [0034-0035] & [Fig. 2A]) which has only three separate terminals (device terminals 21, 22, 23; [0034] & [Fig. 2A]) and/or no dedicated supply terminals.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified Del Croce & Sievers in order to incorporate wherein the circuit is included in a chip package which has only three separate terminals and/or no dedicated supply terminals as taught by Grasso. The motivation for doing so would be to make the device look “like a normal transistor” ([0034], Grasso).
Claim(s) 9 is/are rejected under 35 U.S.C. 103 as being unpatentable over Del Croce et al., US20230308089 (hereinafter referred to as Del Croce), in view of Sievers et al., US20220224323 (hereinafter referred to as Sievers), and in further view of Kumazawa et al., US20240313763 (hereinafter referred to as Kumazawa).
In regards to claim 9, Del Croce & Sievers do not teach wherein a filter circuit is coupled between the output of the comparator and a set input of the latch.
Kumazawa teaches wherein a filter circuit (filter circuit 25; [Fig. 2]) is coupled between the output of the comparator and a set input of the latch (implicit; [0057] & [Fig. 2]).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified Del Croce & Sievers in order to incorporate wherein a filter circuit is coupled between the output of the comparator and a set input of the latch as taught by Kumazawa. The motivation for doing so would be “to delay its rising for a determined time” ([0076], Kumazawa).
Allowable Subject Matter
Claims 7 and 11-15 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Claim 7 is indicated containing allowable subject matter because prior art fails to teach or suggest, either alone or in combination all of the limitations of claim 1 & 7, especially “wherein the reset circuit is an passive low-pass filter coupled between the first input terminal and a reset input of the latch.”
Claim 11 is indicated containing allowable subject matter because prior art fails to teach or suggest, either alone or in combination all of the limitations of claim 1 & 11, especially “a supply circuit that includes a further transistor whose control electrode is connected to the first input terminal and whose load current path is coupled between an internal supply node and the first load electrode of the power transistor.”
Claims 12-13 would be allowed based on dependence of claim 11.
Claim 14 is indicated containing allowable subject matter because prior art fails to teach or suggest, either alone or in combination all of the limitations of claim 1 & 14, especially “wherein the power transistor has a control electrode coupled to a second input terminal.”
Claim 15 is indicated containing allowable subject matter because prior art fails to teach or suggest, either alone or in combination all of the limitations of claim 1 & 15, especially “wherein the power transistor is a split gate transistor which has a first and a second control electrode, the first control electrode being coupled to a first input terminal and the second control electrode being coupled to a second input terminal.”
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. US20170214313A1 and US20190140630A1 are relevant prior arts for claim 1.
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SAMANTHA LYNETTE FAUBERT
Examiner
Art Unit 2836
/CRYSTAL L HAMMOND/ Supervisory Primary Examiner, Art Unit 2838
Prosecution Insights