DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 1-33 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 1 is directed to a memory controller that programs a mode register for a memory to set a read-only mode for a read clock. Claim 1 also recites additional limitations that appear to be directed to a memory – I.E., starting a read clock signal in response to a command. Because the claim is 1) directed to a data processor comprising a memory controller, 2) does not explicitly recite a memory as being part of the invention, and 3) does not recite any steps that would trigger the recited operation in a memory (I.E., issuing a command to the memory to start the read clock signal), it is unclear how the functions executed by the memory further limit the functions of the memory controller. This includes the subsequent step of performing a read cycle using the read clock which is started by the memory in response to a command. The Examiner recommends amending claim 1 to more explicitly indicate that the memory and its functions are part of the claimed invention (e.g., “a data processing comprising a memory controller and a memory... wherein the memory is configured to...”).
Similar reasoning may be applied to claim 18, particularly in regard to the read clock signal being started in response to a command that has not been issued.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1, 15, 17, 18, and 33 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Takahashi, U.S. Patent No. 10,431,293. Takahashi was cited in the Information Disclosure Statement filed on 30 April 2026, and also by the Examiner during prosecution of parent Application No. 17/850,299 (issued as U.S. Patent No. 12,315,551).
Regarding claim 1, Takahashi discloses a data processor configured to control a memory controller to:
program at least one mode register of a memory [col. 10, lines 56-58: “...Read Control Logic 66 receives variable burst length (BL) information from a Mode Register 110 of the memory device 10...”] to set a read clock mode to one of a plurality of settings [col. 3, lines 32-35: “Based on the timing of successive read commands, the memory device may operate in either a ‘single read’ (or ‘non-burst read’) mode or a ‘consecutive burst read’ (or ‘burst read’) mode.”], wherein the plurality of settings includes a read-only mode [col. 8, lines, 20-25 and Fig. 3: non-burst mode comprising only read commands] in which the memory starts a read clock signal in response to a command [Fig. 3: DQS toggles in response to commands RD1 and RD2]; and
subsequently perform a read cycle by receiving data during the read cycle using the read clock signal [col. 3, lines 3-5: “The data strobe signals (e.g., DQS) may include a programmable pre-amble portion, a data read out period, and a post-amble portion.”].
Regarding claim 15, Takahashi discloses that the settings include an always running mode [Fig. 3-5: DQS of non-burst mode shown in Fig. 3 goes to Hi-Z between read commands, whereas the DQS of burst mode shown in Fig. 4 and 5 remain active between read commands].
Regarding claim 17, Takahashi discloses that the data processor further comprises a physical interface circuit coupled to the memory controller and configured to be coupled to the memory [col. 4, lines 48-53: “The CA signals and the external clock signals may be supplied to CA pads or terminals 12 and clock (e.g., CLK, CLKF and CKE) pads or terminals 14 of the electronic device, for example, via a CA bus and a clock bus, or any suitable communicative coupling from a controller or host processor.”].
Claims 18 and 33 are rejected on the same basis as claims 1, 15, and 17.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 16 and 32 are rejected under 35 U.S.C. 103 as being unpatentable over Takahashi in view of Pirich et al., U.S. Patent Application Publication No. 2005/0245314.
Regarding claim 16, Takahashi discloses the data processor of claim 1, but does not disclose a GPU coupled to the memory controller.
Pirich discloses a GPU coupled to a memory controller [para. 0017: “A memory controller 110 is connected to the GPU 108 to facilitates processor access to various types of memory 112, such as, but not limited to, a RAM (Random Access Memory).“].
It would have been obvious to one of ordinary skill in the art, before the effective filing date, to combine the teachings of Takahashi and Pirich by including a GPU, as taught by Pirich, coupled to the memory controller of Takahashi. Takahashi teaches that the data processing system may be, among other things, a game console [col. 4, lines 13-15: “Alternatively, the host device may be another type of electronic device, such as a copier, a scanner, a printer, a game console...”]. Pirich discloses a game console with a GPU coupled to a memory controller, and further teaches that the GPU is part of a video processing pipeline for the game console that provides high speed and high resolution graphics processing and display [para. 0017]. It would therefore have been obvious to one of ordinary skill in the art to apply the teachings of Pirich to Takahashi based on Takahashi’s teaching of a game console and Pirich’s teaching that a GPU provides high speed graphics and display processing for a game console.
Claim 32 is rejected on the same basis as claim 16.
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13.
The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/patent/patents-forms. The actual filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIA /25, or PTO/AIA /26) should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to www.uspto.gov/patents/apply/applying-online/eterminal-disclaimer.
Claims 1, 6-8, 10, 11, 13, 15, 18, 23-25, 27, 28, and 30 are provisionally rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1, 3-6, 8, 10-13, 16, 18, and 19 of copending Application No. 19/300,318 (reference application). Although the claims at issue are not identical, they are not patentably distinct from each other because the application claims are anticipated by, or obvious in view of, the reference claims.
The application claims represent broadened versions of the reference claims. For example, while reference claim 1 recites additional steps not found in application claim 1, it also recites steps of 1) programming a mode register to set a read clock mode in a read-only mode, and 2) receiving data during a read cycle using the read clock signal. Similar reasoning may be applied to the other independent claims. With respect to the dependent claims, the application claims represent obvious variants of the reference claims because they merely recite the same limitations in different groupings. For example, reference claim 5 recites steps found in application claims 8 and 10. Similar reasoning may be applied to the other dependent claims.
This is a provisional nonstatutory double patenting rejection because the patentably indistinct claims have not in fact been patented.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Miyano, U.S. Patent Application Publication No. 2020/0135257, discloses a data processor configured to control a memory controller to:
set a read clock mode to one of a plurality of settings, wherein the plurality of settings includes a read-only mode [para. 0042: “As a reminder, the burst read mode may refer to a memory access operation responsive to a plurality of read commands being asserted consecutively...”] in which the memory starts a read clock signal in response to a command [para. 0028: “For example, the delay locked loop clock signal (DLLCLKO) may be permitted to transmit in response to receiving the delayed read command signal (RCMD_After_QED) but not in response to receiving the delayed write command signal (WCMD_After_QED).”]; and
subsequently perform a read cycle by receiving data during the read cycle using the read clock signal [para. 0026: “...the control system 10 receives the read command and when an output buffer in the DQ system 16 receives read data responsive to the read command based on a clock signal (e.g., the delay locked loop clock signal, DLLCLK).”].
Kim, U.S. Patent Application Publication No. 2022/0051715, discloses a system that generates a read clock enablement signal based on a mode register when a read operation is performed [para. 0103].
Schnell et al., U.S. Patent Application Publication No. 2007/0291572, discloses a system that drives a clock tree only during a read operation [claim 7].
Kim, U.S. Patent No. 5,940,030, discloses a system that enables a clock input buffer only during a read operation [col. 3, lines 48-59].
Fujioka et al., U.S. Patent Application Publication No. 2004/0184325, discloses a system that uses a mode register to set a burst mode [abstract].
The following references share an inventor with the present application, are part of the same application family, and are relevant to the claimed invention:
Nygren et al., U.S. Patent No. 11,854,602,
Nygren et al., U.S. Patent No. 12,243,578,
Nygren et al., U.S. Patent No. 12,315,551,
Nygren et al., U.S. Patent No. 12,394,467.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to JI H BAE whose telephone number is (571)272-7181. The examiner can normally be reached Tuesday to Friday and every other Monday, 9 am to 6 pm.
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/JI H BAE/Primary Examiner, Art Unit 2176 U.S. Patent and Trademark Office
Phone: 571-272-7181
Fax: 571-273-7181
ji.bae@uspto.gov
