DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Restriction to one of the following inventions is required under 35 U.S.C. 121:
I. Claims 1-20 and 21-25, drawn to 1. … initiate a timer based at least in part on receiving the first command; receive a second command associated with a second access operation; and suppress performing the second access operation based at least in part on a value of timer satisfying a threshold value, classified in G11C 7/22 - Read-write [R-W] timing or clocking circuits Read-write [R-W] control signal generators or management.
II. Claim 11-20, drawn to 11. …increment a value of counter of the memory system, wherein the value of the counter is associated with performing access operations at the memory system; receive a first command associated with a first access operation based at least in part on incrementing the value of the counter; perform the first access operation based at least in part on the value of the counter satisfying a first threshold value; and adjust the value of the counter based at least in part on performing the first access operation, classified in G06F 3/0613 – in relation to throughput.
The inventions are independent or distinct, each from the other because:
Inventions I and II are related as subcombinations disclosed as usable together in a single combination. The subcombinations are distinct if they do not overlap in scope and are not obvious variants, and if it is shown that at least one subcombination is separately usable. In the instant case, subcombination I has separate utility such as initiate a timer based at least in part on receiving the first command; receive a second command associated with a second access operation; and suppress performing the second access operation based at least in part on a value of timer satisfying a threshold value classified in G11C 7/22 - Read-write [R-W] timing or clocking circuits Read-write [R-W] control signal generators or management.
Subcombination II has separate utility such as increment a value of counter of the memory system, wherein the value of the counter is associated with performing access operations at the memory system; receive a first command associated with a first access operation based at least in part on incrementing the value of the counter; perform the first access operation based at least in part on the value of the counter satisfying a first threshold value; and adjust the value of the counter based at least in part on performing the first access operation, classified in G06F 3/0613 – in relation to throughput.
See MPEP § 806.05(d).
The examiner has required restriction between subcombinations usable together. Where applicant elects a subcombination and claims thereto are subsequently found allowable, any claim(s) depending from or otherwise requiring all the limitations of the allowable subcombination will be examined for patentability in accordance with 37 CFR 1.104. See MPEP § 821.04(a). Applicant is advised that if any claim presented in a divisional application is anticipated by, or includes all the limitations of, a claim that is allowable in the present application, such claim may be subject to provisional statutory and/or nonstatutory double patenting rejections over the claims of the instant application.
Restriction for examination purposes as indicated is proper because all the inventions listed in this action are independent or distinct for the reasons given above and there would be a serious search and/or examination burden if restriction were not required because one or more of the following reasons apply:
Group I is directed to using a timer to determine whether or not to perform a subsequently received command based on the timer and Group II is directed to using counter that is associated with performing access operations and determining whether or not to perform any operation based on the value of the counter.
Applicant is advised that the reply to this requirement to be complete must include (i) an election of an invention to be examined even though the requirement may be traversed (37 CFR 1.143) and (ii) identification of the claims encompassing the elected invention.
The election of an invention may be made with or without traverse. To reserve a right to petition, the election must be made with traverse. If the reply does not distinctly and specifically point out supposed errors in the restriction requirement, the election shall be treated as an election without traverse. Traversal must be presented at the time of election in order to be considered timely. Failure to timely traverse the requirement will result in the loss of right to petition under 37 CFR 1.144. If claims are added after the election, applicant must indicate which of these claims are readable upon the elected invention.
Should applicant traverse on the ground that the inventions are not patentably distinct, applicant should submit evidence or identify such evidence now of record showing the inventions to be obvious variants or clearly admit on the record that this is the case. In either instance, if the examiner finds one of the inventions unpatentable over the prior art, the evidence or admission may be used in a rejection under 35 U.S.C. 103 or pre-AIA 35 U.S.C. 103(a) of the other invention.
During a telephone conversation with Brian Sullivan, Reg. No. 73, 392 on 7/15/2026 a provisional election was made without traverse to prosecute the invention of Group I, claims 1-10 and 21-25. Affirmation of this election must be made by applicant in replying to this Office action. Claims 11-20 are withdrawn from further consideration by the examiner, 37 CFR 1.142(b), as being drawn to a non-elected invention.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 4 and 24 rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention. Claim 4 and 24 recites the limitation "a fifth command". There is insufficient antecedent basis for this limitation in the claim as claim 4 and 24 are dependent upon independent claims 1 and 21 which only have a first and second command. If they were dependent upon claims 3 and 23 respectively then there would be no issue as those claims do mention a fourth command.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1, 2, 5-10, 21, 22, and 25 are rejected under 35 U.S.C. 103 as being unpatentable over Boles (US PGPub ) in view of L'Ecuyer et al. (US PGPub , hereafter referred to as L'Ecuyer).
Regarding claim 1, Boles teaches a memory system, comprising: one or more memory devices, and processing circuitry coupled with the one or more memory devices (Fig. 1, shows the memory system with a processor connected to local and other memories), and configured to cause the memory system to: receive a first command associated with a first access operation, initiate a timer based at least in part on receiving the first command (Paragraphs [0066] and [0069], states a request can be received from the host to initiate a memory transaction and a timer can also be initialized in association with the transaction and thus the command), receive a second command associated with a second access operation (Paragraphs [0066] and [0069], the process is done for all memory requests meaning that multiple can be received throughout the operation of the memory). Boles does not explicitly teach suppressing performing the second access operation based at least in part on a value of timer satisfying a threshold value.
L'Ecuyer teaches suppressing performing the second access operation based at least in part on a value of timer satisfying a threshold value (Paragraph [0062], states that if a timer is still counting (satisfying a threshold value) the can delay a second command to ensure a particular data rate is met). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the teachings of Boles to implement a delay of operation based on the timer as taught in L'Ecuyer so to increase the use of the link rate of the devices while preventing frame loss (L’Ecuyer, Paragraph [0062]).
Regarding claim 2, Boles and L'Ecuyer teach all the limitations to claim 1. L'Ecuyer further teaches wherein the processing circuitry is further configured to cause the memory system to: receive a third command comprising an indication of an initial value of the timer, and set the initial value of the timer based at least in part on receiving the third command (Paragraph [0018], states the timer can be based on the size of the data frame (size of the received command)). The combination of and reason for combining are the same as those given in claim 1.
Regarding claim 5, Boles and L'Ecuyer teach all the limitations to claim 1. L'Ecuyer further teaches wherein the processing circuitry is further configured to cause the memory system to: perform the second access operation based at least in part on the value of the timer failing to satisfy the threshold value (Paragraph [0057], if the timer has expired (reached zero and fails to satisfy the threshold value) then the next command can be sent). The combination of and reason for combining are the same as those given in claim 1.
Regarding claim 6, Boles and L'Ecuyer teach all the limitations to claim 1. L'Ecuyer further teaches wherein the processing circuitry is further configured to cause the memory system to: identify one or more parameters associated with the first command, and select an initial value for the timer based at least in part on the one or more parameters, wherein the timer comprises the initial value when initiated (Paragraph [0018], as stated in the rejection to claim 5, the size of the data frame (parameter associated with first command) can be used to determine the starting value of the timer). The combination of and reason for combining are the same as those given in claim 1.
Regarding claim 7, Boles and L'Ecuyer teach all the limitations to claim 1. L'Ecuyer further teaches wherein the one or more parameters comprise a size of data associated with the first access operation, a type of the first access operation, a quantity of planes of the memory system associated with the first access operation, or a combination thereof (Paragraph [0018], as stated in the rejection to claim 6). The combination of and reason for combining are the same as those given in claim 1.
Regarding claim 8, Boles and L'Ecuyer teach all the limitations to claim 1. L'Ecuyer further teaches wherein the processing circuitry is further configured to cause the memory system to: determine, by the memory system, a target rate for processing commands, and select an initial value for the timer based at least in part on the target rate, wherein the timer comprises the initial value when initiated (Paragraph [0018], an agreed upon rate between devices can be used to determine the value of the timer). The combination of and reason for combining are the same as those given in claim 1.
Regarding claim 9, Boles and L'Ecuyer teach all the limitations to claim 1. Boles further teaches wherein the processing circuitry is further configured to cause the memory system to: perform the first access operation based at least in part on receiving the first command, wherein initiating the timer is based at least in part on performing the first access operation (Paragraphs [0066] and [0069], as stated in the rejection to claim 1, the operation is performed because a command was received and the timer is initiated with the operation). The combination of and reason for combining are the same as those given in claim 1.
Regarding claim 10, Boles and L'Ecuyer teach all the limitations to claim 1. L'Ecuyer further teaches wherein the value of the timer failing to satisfy the threshold value corresponds to the value of the timer expiring (Paragraph [0057], as stated in the rejection to claim 5, the command can be delayed until the timer expires). The combination of and reason for combining are the same as those given in claim 1.
Regarding claims 21, 22, and 25, claims 21, 22, and 25 are the computer readable medium claims associated with claims 1, 2, and 5. Since Boles and L'Ecuyer teach all the limitations to claims 1, 2, and 5, they also teach all the limitations to claims 21, 22, and 25; therefore the rejections to claims 1, 2, and 5 also apply to claims 21, 22, and 25.
Claims 3 and 23 are rejected under 35 U.S.C. 103 as being unpatentable over Boles and L'Ecuyer as applied to claims 2 and 22 above, and further in view of Pan et al. (US PGPub 2020/0221298, hereafter referred to as Pan).
Regarding claim 3, Boles and L'Ecuyer teach all the limitations to claim 2. wherein the processing circuitry is further configured to cause the memory system to: receive a fourth command comprising an updated initial value of the timer, and update the initial value of the timer based at least in part on receiving the fourth command.
Pan teaches wherein the processing circuitry is further configured to cause the memory system to: receive a fourth command comprising an updated initial value of the timer, and update the initial value of the timer based at least in part on receiving the fourth command (Paragraph [0128], states a command can be sent that can provide a new value of the timer). Since both Boles/L’Ecuyer and Pan teach the use of timers it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the prior art references according to known methods by modifying the teachings of Boles and L’Ecuyer to also use a command to update the timer value as taught in Pan to obtain the predictable result of receive a fourth command comprising an updated initial value of the timer, and update the initial value of the timer based at least in part on receiving the fourth command (as all this does is specify how the timer can be updated).
Regarding claim 23, claim 23 is the computer readable medium claim associated with claim 3. Since Boles, L'Ecuyer, and Pan teach all the limitations to claim 3, they also teach all the limitations to claim 23; therefore the rejection to claim 3 also applies to claim 23.
Claims 4 and 24 are rejected under 35 U.S.C. 103 as being unpatentable over Boles and L'Ecuyer as applied to claims 1 and 21 above, and further in view of Foster (US PGPub 2015/0134864).
Regarding claim 4, Boles and L'Ecuyer teach all the limitations to claim 1. Boles and L'Ecuyer do not teach wherein the processing circuitry is further configured to cause the memory system to: receive a fifth command comprising a request for an initial value of the timer, and transmit an indication of an initial value of the timer based at least in part on receiving the fifth command.
Foster teaches wherein the processing circuitry is further configured to cause the memory system to: receive a fifth command comprising a request for a value of the timer, and transmit an indication of a value of the timer based at least in part on receiving the fifth command (Paragraph [0058], states a request for a local timer value can be sent and in response the value of the timer may be transmitted). Since both Boles/L’Ecuyer and Foster teach the use of timers it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the prior art references according to known methods by modifying the teachings of Boles and L’Ecuyer to also implement a request for the timer’s value as taught in Foster to obtain the predictable result of receive a fifth command comprising a request for a value of the timer, and transmit an indication of a value of the timer based at least in part on receiving the fifth command.
Regarding claim 24, claim 24 is the computer readable medium claim associated with claim 4. Since Boles, L'Ecuyer, and Foster teach all the limitations to claim 4, they also teach all the limitations to claim 24; therefore the rejection to claim 4 also applies to claim 24.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to NICHOLAS A PAPERNO whose telephone number is (571)272-8337. The examiner can normally be reached Mon-Fri 9:30-5 EST.
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/NICHOLAS A. PAPERNO/Examiner, Art Unit 2132
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