DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Amendment2. In an amendment dated, March 30, 2026, claims 1, 10 and 20 are amended. Currently claims 1-20 are pending.
Terminal Disclaimer
The terminal disclaimer filed on March 14, 2026 disclaiming the terminal portion of any patent granted on this application which would extend beyond the expiration date of U.S. Patent No. 12,317,597 has been reviewed and is accepted. The terminal disclaimer has been recorded.
Response to Arguments
Applicant's arguments filed March 14, 2026 have been fully considered but they are not persuasive.
On page 10-11 of the remarks, applicant argues prior art of record fails to disclose claim limitation of independent claims 1 and 20 wherein “….the second signal line, the third signal line and the fourth signal line overlap a same pixel circuit of the first display sub-region in a thickness direction of the display panel, and the third signal line and the same pixel circuit overlapping the third signal line are insulated from each other .” the office respectfully disagrees. Prior art of record discloses the connection of pixel circuit and signal lines and (Fig 6, 10) discloses signal lines overlapping pixel circuit in a thickness direction as well as third signal line disposed on an insulating layer that would insulate it from pixel circuit. Therefore it is obvious to an ordinary skilled person in the art at the time of the filing that prior art of record discloses the claimed limitation of independent claims wherein the position of signal lines disposed overlapping pixel circuit in a thickness direction of the display panel and having insulation between pixel circuit and connecting signal line (third signal line).
Claim Rejections - 35 USC § 103
5. In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
6. The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1-3, 5-9, and 12-20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Ding L CN 113160743 (for English translation see Feng et al US 2023/0343794).
As in claim 1, Feng et al discloses a display panel (Fig 1), comprising:
a first display region, a second display region and a first function region, wherein the first display region is adjacent to the first function region in a first direction, the second display region is adjacent to the first function region in a second direction, and the first direction intersects the second direction; (Fig 4, 5) discloses first display region (i.e. left and right of Hole region), a second display region (i.e. above hole region) and a first function region (hole) wherein the first display region is adjacent to the first function region in a first direction, and the second display region is adjacent to the first function region in a second direction, wherein the first direction intersects the second direction
wherein the second display region comprises a first signal line extending in the second direction, the first signal line is configured to supply a first type of signal to a pixel circuit of the second display region, and the first signal line comprises a first segment and a second segment that are separated by the first function region; (Fig 4, 5) discloses second display region (i.e. above hole region) having first signal line (12) extending in the second direction (Y-direction) and configured to supply a first type of signal to a pixel circuit and the first signal line comprises a first segment (121) and a second segment (122) that are separated by the first function region (hole)
wherein the first display region comprises a first display sub-region; (Fig 4-5 left side of Hole region)
wherein the first display sub-region comprises a second signal line and a third signal line that extend in the second direction, the second signal line is configured to supply the first type of signal to a pixel circuit of the first display sub-region, and the third signal line is electrically connected to the first segment and the second segment; (Fig 4, 5) discloses first sub-region (i.e. left side of Hole region) having second and a third signal line (40 and 22) that extend in the second direction (y-direction) that are configured to supply the first type of signal to a pixel circuit of the first display sub-region, and the third signal line (22) is electrically connected to the first segment and the second segment (121 & 122);
wherein the display panel further comprises a fourth signal line extending in the second direction and configured to transmit a second type of signal; (Fig 5) discloses fourth signal line (421) extending in the second direction configured to transmit a second type of signal
and wherein the second signal line, the third signal line and the fourth signal line overlap a same pixel circuit of the first display sub-region in a thickness direction of the display panel, and the third signal line and the same pixel circuit overlapping the third signal line are insulated from each other . (Par 0024) discloses signal lines electrically connected to the pixel circuits. [0028] In order to provide signals for pixel driver circuits which are electrically connected to a same second category signal line 12, the first connection signal lines 20 are provided to connect the separated first section 121 and second section 122. And (Fig 6 and Par 0047) discloses signal lines overlap a same pixel circuit of the first display sub-region in a thickness direction of the display panel and the third signal line used to connect two signal lines (i.e. first segment and second segment) disposed on insulation layer. Thus it is obvious to an ordinary skill person in the art that the second signal line, the third signal line and the fourth signal line overlap a same pixel circuit of the first display sub-region in a thickness direction of the display panel, and the third signal line used to connect first segment and second segment is disposed on insulation layer to insulate it from pixel circuit in order to avoid short circuit.
As in claim 2, Feng et al discloses the display panel (Fig 1) according to claim 1, comprising at least one of: the fourth signal line is a first power signal Line, the second type of signal is a first power signal, or the first type of signal is a data signal. (Fig 5 and Par 0042) discloses signal line 40 (i.e. 41 & 42) may be a power signal line.
As in claim 3, Feng et al discloses the display panel (Fig 1) according to claim 1, wherein in a same pixel circuit of the first display sub-region, the second signal line and the third signal line are located on a same side of the fourth signal line. (Fig 5, 9 and Par 0024) discloses signal lines electrically connected to the pixel circuits. But fails to explicitly disclose the arrangement of the third signal line is located on one side of the second signal line facing away from the fourth signal line. However changing the locations of signal lines (i.e. rearrangement of parts) third signal line, second signal line and fourth signal line) with respect to each other in a pixel circuit would yield the same predictable result. It is obvious to an ordinary skill person in the art at the time of the filing to have side signal lines arranged it a particular configuration in respect to each other would not change the performance of said signal lines as well as each pixel circuit. Therefore, rearranging signal lines (i.e. with respect to each other as claimed above would have been obvious design choice to an ordinary skill person in the art at the time of the filing to yields same predictable outcome.
In re Japikse, 86 USPQ 70 (CCPA 1950) In the brief of the Solicitor for the patent office it is pointed out that the claim reads on Cannon except as to the final limitation reading “means disposed in alignment with said opening for contact by said depending means to start the pressing operation of said hydraulic press.” As to that limitation it was held that there would be no invention in shifting the starting switch disclosed by Cannon to a different position since the operation of the device would not thereby be modified.
In KSR, the Supreme Court particularly emphasized "the need for caution in granting a patent based on the combination of elements found in the prior art,"Id. at 415, 82 USPQ2d at 1395, and discussed circumstances in which a patent might be determined to be obvious. Importantly, the Supreme Court reaffirmed principles based on its precedent that "[t]he combination of familiar elements according to known methods is likely to be obvious when it does no more than yield predictable results."Id. at 415-16, 82 USPQ2d at 1395. The Supreme Court stated that there are "[t]hree cases decided after Graham [that] illustrate this doctrine." Id. at 416, 82 USPQ2d at 1395. (1) "In United States v. Adams, . . . [t]he Court recognized that when a patent claims a structure already known in the prior art that is altered by the mere substitution of one element for another known in the field, the combination must do more than yield a predictable result." Id. (2) "In Anderson’s-Black Rock, Inc. v. Pavement Salvage Co., . . . [t]he two [pre-existing elements] in combination did no more than they would in separate, sequential operation." Id. at 416-17, 82 USPQ2d at 1395. (3) "[I]n Sakraida v. AG Pro, Inc., the Court derived . . . the conclusion that when a patent simply arranges old elements with each performing the same function it had been known to perform and yields no more than one would expect from such an arrangement, the combination is obvious." Id. at 417, 82 USPQ2d at 1395-96 (Internal quotations omitted.). The principles underlining these cases are instructive when the question is whether a patent application claiming the combination of elements of prior art would have been obvious.
However, it has been held that a mere rearrangement of element without modification of the operation of the device involves only routine skill in the art. In re Japiske, 86 USPQ 70 (CCPA 1950). The rearrangement in this case does not modify the operation of the device because having signal lines disposed as claimed or as disclosed in prior art of record would not prevent display signal(s) being transmitted as well as hinder the operation of pixel circuit. As discloses in prior art of record having said signal lines arranged as shown in prior art would yield an increase a screen-to-body ratio of a display area and improve display effects similar to current application.
As in claim 5, Feng et al discloses the display panel (Fig 1) according to claim 1, wherein the second signal line and the third signal line are located in a same film. (Fig 6) discloses second signal line and the third signal line are located in a same film/layer.
As in claim 6, Feng et al discloses the display panel (Fig 1) according to claim1, wherein in the first direction, a distance between the second signal line and the third signal line is d1, and d1 2.5µm. (Fig 5, 9, Par 0024, 0026) discloses second signal line and the third signal line having a given distance between each other (i.e. d1). But fails to explicitly disclose the distance between signal lines is greater than or equal to 2.5µm. However it would have been an obvious design choice to have said distance to be greater than or equal to 2.5µm to yield same predictable result. However, it is obvious and well known that adjusting the distance between two signal lines (i.e. the second signal line and the third signal line) to be within a given range would help in improving display uniformity of the light emitting area to the total display area or percentage of the effective display area in a display panel, optimized luminance can be obtained. Thus, it would have been obvious to a skilled person in the art at the time of the filing to optimize the distance range to be greater than or equal to 2.5µm, since it has been held that where the general conditions of a claim are disclosed in the prior art, it is not inventive to discover the optimum or workable ranges by routine experimentation." In re Aller, 220 F.2d 454, 456, 105 USPQ 233, 235 (CCPA 1955)
As in claim 7, Feng et al discloses the display panel (Fig 1) according to claim1, further comprising a first connection line extending in the first direction, wherein the first connection line is configured to connect the first signal line to the third signal line. (Fig 4, 5, 8, 9 Par 0029-0033) discloses first connection line (21) extending in the first direction (Y-direction) and is configured to connect the first signal line (121) to the third signal line (22).
As in claim 8, Feng et al discloses the display panel (Fig 1) according to claim 7, comprising at least one of: the first connection line and the third signal line are located in different films, or the first connection line and the reference voltage signal line are located in a same film. (Fig 5-6) discloses connection signal lines (i.e. 20) are located in different films from signal line (i.e. 10)
As in claim 9, Feng et al discloses the display panel (Fig 1) according to claim 7, further comprising a reference voltage signal line extending in the first direction, wherein the reference voltage signal line is configured to supply a reference voltage signal to the pixel circuit [(Par 0041, 0052, 0054) discloses signal line may be a reference voltage signal line configured to supply a reference voltage signal]; and the first connection line and the reference voltage signal line are insulated from each other, and in the thickness direction of the display panel, the first connection line and the reference voltage signal line at least partially overlap. (Fig 5, 9) discloses connection line and the reference voltage signal line are at least partially overlap.
As in claim 12, Feng et al discloses the display panel (Fig 1) according to claim 1, wherein the first display region further comprises a second display sub-region [(Fig 4, 5) discloses a second display sub-region (i.e. right side hole region)]; wherein the second display sub-region comprises a fifth signal line extending in the second direction and configured to supply the first type of signal to a pixel circuit of the second display sub-region; wherein the display panel further comprises a virtual signal line extending in the second direction; wherein the virtual signal line comprises a first virtual signal line located in the second display sub-region, and in a same pixel circuit of the second display sub-region, the fifth signal line and the first virtual signal line are located on a same side of the fourth signal line; and wherein the virtual signal line further comprises a second virtual signal line located in the first display sub-region, the second virtual signal line and the third signal line are arranged in the second direction and are insulated from each other. (Fig 4-5) discloses the second display sub-region comprises signal line extending in the second direction (i.e. y-direction) and configured to supply the signal to a pixel circuit (Par 0024,0026) of the second display sub-region wherein the display panel further comprises a (virtual) signal line extending in the second direction (y-direction); comprises a first signal line located in the second display sub-region. As to the position/location of signal lines in respect to other signal lines; it would have been an obvious design choice to an ordinary skill person in the art to have said signal lines positioned/located in a particular arrangement to yield same predictable result.
As in claim 13, Feng et al discloses the display panel (Fig 1) according to claim 12, wherein the virtual signal line further comprises a third virtual signal line located in the second display region, and in a same pixel circuit of the second display region, the first signal line and the third virtual signal line are located on a same side of the fourth signal line. (Fig 4-5) discloses the second display sub-region comprises signal line extending in the second direction (i.e. y-direction) and configured to supply the signal to a pixel circuit (Par 0024,0026) of the second display sub-region wherein the display panel further comprises a (virtual) signal line extending in the second direction (y-direction); comprises a first signal line located in the second display sub-region. As to the position/location of signal lines in respect to other signal lines; it would have been an obvious design choice to an ordinary skill person in the art to have said signal lines positioned/located in a particular arrangement to yield same predictable result.
As in claim 14, Feng et al discloses the display panel (Fig 1) according to claim 12, wherein a third type of signal is applied to the virtual signal line, and the third type of signal is a fixed voltage signal. (Par 0041) discloses signal lines may be a reference voltage signal line (i.e. fixed voltage signal)
As in claim 15, Feng et al discloses the display panel (Fig 1) according to claim 12, wherein in the same pixel circuit of the first display sub-region, in the first direction, a distance between the second signal line and the third signal line is d1; and in the same pixel circuit of the second display sub-region, in the first direction, a distance between the fifth signal line and the first virtual signal line is d3; wherein dl> d3. (Fig 5, 9, Par 0024, 0026) discloses first display sub-region and second display sub-region having signal lines and pixel circuits (not shown) connected to plurality of signal lines; wherein said signal lines having varying distance between each other (i.e. d1 and d2). But fails to explicitly disclose the distance between signal lines d1 of first display sub-region is greater or equal to the distance between the two signal lines d3 in a second display sub-region. However it would have been an obvious design choice to have said distance to be a particular ratio to yield same predictable result.
As in claim 16, Feng et al discloses the display panel (Fig 1) according to claim 12, wherein a line width of the third signal line is W1, and a line width of the virtual signal line is W2, wherein W1< W2. (Fig 5 and 6) discloses signal lines having different width. Therefore it would have been obvious to an ordinary skill person in the art at the time of the filing to have the line width with different size wherein line width of the third signal line would be less than line width of the virtual signal line as an alternat design choice to yield same predictable result.
As in claim 17, Feng et al discloses the display panel (Fig 1) according to claim 12, further comprising a second connection line extending in the first direction, wherein the second connection line is configured to connect the first virtual signal line to the second virtual signal line, and/or configured to connect the second virtual signal line to the third virtual signal line. (Fig 4-5, 9) discloses second connection line extending in the first direction configured to connect signal lines.
As in claim 18, Feng et al discloses the display panel (Fig 1) according to claim 17, wherein the first virtual signal line, the second virtual signal line and the third virtual signal line are located in a same film; and the second connection line and the virtual signal line are located in different films. (Fig 5- 6) discloses location of signal lines
As in claim 19, Feng et al discloses the display panel (Fig 1) according to claim 12, further comprising a first connection line extending in the first direction, wherein the first connection line is configured to connect the first signal line of the second display region to the third signal line of the first display sub-region; wherein the display panel further comprises a virtual connection line extending in the first direction, the virtual connection line and the first connection line are arranged in the first direction and are insulated from each other. (Fig 3-5 and 9) discloses connection line extending in the first direction configured to connect signal line(s) of the display region(s) wherein the display panel further comprises a virtual connection line extending in the first direction and are insulated from first connection line.
As in claim 20, Feng et al discloses a display panel (Fig 1), comprising a display panel, wherein the display panel comprises:
a first display region, a second display region and a first function region, wherein the first display region is adjacent to the first function region in a first direction, the second display region is adjacent to the first function region in a second direction, and the first direction intersects the second direction; (Fig 4, 5) discloses first display region (i.e. left and right of Hole region), a second display region (i.e. above hole region) and a first function region (hole) wherein the first display region is adjacent to the first function region in a first direction, and the second display region is adjacent to the first function region in a second direction, wherein the first direction intersects the second direction
wherein the second display region comprises a first signal line extending in the second direction, the first signal line is configured to supply a first type of signal to a pixel circuit of the second display region, and the first signal line comprises a first segment and a second segment that are separated by the first function region; (Fig 4, 5) discloses second display region (i.e. above hole region) having first signal line (12) extending in the second direction (Y-direction) and configured to supply a first type of signal to a pixel circuit and the first signal line comprises a first segment (121) and a second segment (122) that are separated by the first function region (hole)
wherein the first display region comprises a first display sub-region; (Fig 4-5 left side of Hole region)
wherein the first display sub-region comprises a second signal line and a third signal line that extend in the second direction, the second signal line is configured to supply the first type of signal to a pixel circuit of the first display sub-region, and the third signal line is electrically connected to the first segment and the second segment; (Fig 4, 5) discloses first sub-region (i.e. left side of Hole region) having second and a third signal line (40 and 22) that extend in the second direction (y-direction) that are configured to supply the first type of signal to a pixel circuit of the first display sub-region, and the third signal line (22) is electrically connected to the first segment and the second segment (121 & 122);
wherein the display panel further comprises a fourth signal line extending in the second direction and configured to transmit a second type of signal; (Fig 5) discloses fourth signal line (421) extending in the second direction configured to transmit a second type of signal
and wherein the second signal line, the third signal line and the fourth signal line overlap a same pixel circuit of the first display sub-region in a thickness direction of the display panel, and the third signal line and the same pixel circuit overlapping the third signal line are insulated from each other. (Par 0024) discloses signal lines electrically connected to the pixel circuits. [0028] In order to provide signals for pixel driver circuits which are electrically connected to a same second category signal line 12, the first connection signal lines 20 are provided to connect the separated first section 121 and second section 122. And (Fig 6 and Par 0047) discloses signal lines overlap a same pixel circuit of the first display sub-region in a thickness direction of the display panel and the third signal line used to connect two signal lines (i.e. first segment and second segment) disposed on insulation layer. Thus it is obvious to an ordinary skill person in the art that the second signal line, the third signal line and the fourth signal line overlap a same pixel circuit of the first display sub-region in a thickness direction of the display panel, and the third signal line used to connect first segment and second segment is disposed on insulation layer to insulate it from pixel circuit in order to avoid short circuit.
Claim(s) 4 and 11 is/are rejected under 35 U.S.C. 103 as being unpatentable over Ding L CN 113160743 (for English translation see Feng et al US 2023/0343794) in view of Chin X CN 113223409 (for English translation see Feng et al US 2023/0343785).
As in claim 4, Feng et al discloses the display panel (Fig 1) according to claim 1, further comprising (Par 0024, 0026) discloses display panel having pixel circuits in a display area.
and in a same pixel circuit group of the first display sub-region, in the first direction, the second signal line is located between two third signal lines, or the third signal line is located between two second signal lines. (Fig 5, 9) discloses a plurality of third signal line is located between two signal lines
But fails to disclose the pixel circuit group comprises a first pixel circuit and a second pixel circuit disposed adjacent to each other in the first direction and arranged in a mirror-image; However Feng et al (785) Fig 2 disclose pixel circuit group, wherein the pixel circuit group comprises a first pixel circuit and a second pixel circuit disposed adjacent to each other in the first direction (Y-direction). Therefore it would have been obvious to an ordinary skill person in the art at the time of the filing to modify Feng et al display panel with the teaching of Feng et al display panel having pixel circuit group disposed adjacent to each other in the first direction in order to provide improved pixel control reduce coast.
As in claim 11, Feng et al discloses the display panel (Fig 1) according to claim 7, further comprising a first power signal line, wherein the first power signal line is configured to transmit a first power signal; (Par 0041) discloses signal line 40 may be a power signal line (Vdd line) the pixel circuit (Par 0024, 0026, 0055) discloses pixel circuit; and (Par 0028) discloses pixel driver circuits which are electrically connected to a same second category signal line 12, the first connection signal lines 20 are provided to connect the separated first section 121 and second section 122. (Fig 5 and Par 0042) discloses signal line that is connected to pixel circuit (i.e. power signal line) includes a first sub-signal line and a second sub-signal line which are electrically connected to each other through a via having a given distance between the connection line and the first via that is greater than 0 (see fig 4-5). But fails to disclose the pixel circuit further comprises a data signal write transistor, a drive transistor, and a compensation transistor; wherein the drive transistor is connected in series between the first power signal line and a light-emitting element; wherein a first electrode of the drive transistor is electrically connected to a first electrode of the data signal write transistor, a second electrode of the drive transistor is electrically connected to a first electrode of the compensation transistor, and a second electrode of the compensation transistor is electrically connected to a gate of the drive transistor; wherein in the pixel circuit of the first display sub-region, a second electrode of the data signal write transistor is electrically connected to the second signal line through a first via; and wherein in the second direction, a distance between the first connection line and the first via is d2, wherein d2 > 0. However Kim et al (Fig 12-13 and Par 0068, 0070-0082) discloses pixel circuit that is disposed in a display region comprising a data signal write transistor (Fig 13, T2), a drive transistor(Fig 13; T1), and a compensation transistor (Fig 13; T3), wherein the drive transistor (T1) is connected in series between the first power signal line (ELVDD) and a light-emitting element (OLED); a first electrode of the drive transistor (T1) is electrically connected to a first electrode of the data signal write transistor (T2), a second electrode of the drive transistor (T1) is electrically connected to a first electrode of the compensation transistor (T3), and a second electrode of the compensation transistor (T3) is electrically connected to a gate of the drive transistor (T1); and in the pixel circuit (Fig 13) of the first display sub-region (Fig 12), a second electrode of the data signal write transistor is electrically connected to the second signal line through a first via; Thus given the separation of signal lines disposed above and below the hole wherein connection line is used to connect first sub-signal line and a second sub-signal line in order to provide signal to the pixel circuit in Feng et al and Pixel circuit shown in Kim et al it would have been obvious to an ordinary skill person in the art at the time of the filing to particular electrode of pixel circuit connect to the signal line through a via in order to provide data signal to pixel circuit. Therefore it would have been obvious to an ordinary skill person in the art at the time of the filing to modify Feng et al display panel with the teaching of Kim et al display panel having well-known display pixel circuit and its connection to yield same predictable result.
Allowable Subject Matter
Claim 10 allowed. Prior art of record singularly or in combination thereon fails to disclose all the connection of pixel circuit transistor to each other as well as the locations of signal lines in the thickness direction of the display panel as claimed.
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to BENYAM KETEMA whose telephone number is (571)270-7224. The examiner can normally be reached 9AM-5PM (M-F).
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/BENYAM KETEMA/Primary Examiner, Art Unit 2626
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