Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 101
35 U.S.C. 101 reads as follows:
Whoever invents or discovers any new and useful process, machine, manufacture, or composition of matter, or any new and useful improvement thereof, may obtain a patent therefor, subject to the conditions and requirements of this title.
Claims 1-8 are rejected under 35 U.S.C. 101 because the claimed invention is directed to non-statutory subject matter. The claimed "one or more memories" can be interpreted to include both transitory and non-transitory embodiments. For example, paragraph [0023] states, “local memory 120 may include ROM or other memory that may store operating code”. The stated “other memory” can be reasonably interpreted to potentially include transitory embodiments. Transitory embodiments are not directed to statutory subject matter. See In re Nuijten, 500 F.3d 1346, 1356-57 (Fed. Cir. 2007).
A claim drawn to such a “memory/memories” that covers both transitory and non-transitory embodiments may be amended to narrow the claim to cover only statutory embodiments to avoid a rejection under 35 U.S.C. § 101 by adding the limitation "non-transitory" to the claim.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-24 are rejected under 35 U.S.C. 103 as being unpatentable over US 11,663,074 B1 to Huang, Yu-Ming et al (herein referred to as Yu-Ming) in view of US 12,548,629 B2 to Huang, Zhen et al (herein referred to as Zhen).
Referring to claim 1, Yu-Ming discloses a memory system, comprising: one or more memories storing processor-executable code; and one or more processors coupled with the one or more memories and individually or collectively operable to execute the code to cause the memory system (“memory system including a memory and a memory controller coupled to the memory” Col. 1, Lines 21-23) to: retrieve, from mapping information stored by the memory system, an entry mapped to one or more parameters associated with a set of memory cells of the memory system (“input parameters and optimal read voltages, which can be recorded in a lookup table” Col. 6, lines 57-58); apply a read voltage to the set of memory cells, wherein a magnitude of the read voltage is based at least in part on the entry (“obtain a first reading output of target memory data stored in the memory using a first read voltage” Col. 1, line 24-25); determine a bit error count associated with the set of memory cells based at least in part on applying the read voltage, the bit error count indicating a quantity of errors in data stored in the set of memory cells (“optimal read voltages corresponding to a minimum failed bit count of a reading output” Col.2, line 48-50); and Yu-Ming does not explicitly teach “determine whether to refresh the set of memory cells based at least in part on the bit error count and a threshold bit error count. However, Zhen, in an analogous art, teaches the determine whether to refresh the set of memory cells based at least in part on the bit error count and a threshold bit error count ("generate a refresh command according to a failed bit count (abbreviated to fbc) or a bit error rate of data read from the memory device" Col. 10, line 26-28). Thus, Yu-Ming and Zhen each disclose running error correction on a memory system. A person of ordinary skill in the art before the effective filing date of the claimed invention would have recognized that the generating refresh command disclosed by Zhen could have been applied to error correction method of Yu-Ming because both Yu-Ming and Zhen have failed bit count as one of the parameters. Furthermore, a person of ordinary skill in the art would have been able to carry out the application. Finally, the application achieves the predictable result of allowing the determination of whether to refresh the set of memory cells based on the bit error cunt and a threshold bit error count.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to apply the refresh command of Zhen for the error correction method of Yu-Ming to yield the predictable result of providing a determination whether to refresh the set of memory cells based at least in part on the bit error count and a threshold bit error count.
Referring to claim 2, Yu-Ming in view of Zhen discloses wherein, to determine whether to refresh the set of memory cells, the one or more processors are individually or collectively operable to execute the code to cause the memory system to: compare the bit error count to the threshold bit error count; and refresh the set of memory cells based at least in part on the bit error count being greater than the threshold bit error count (Zhen, "generate a refresh command according to a failed bit count (abbreviated to fbc) or a bit error rate of data read from the memory device" Col. 10, lines 26-28).
Referring to claim 3, Yu-Ming in view of Zhen discloses wherein, to refresh the set of memory cells, the one or more processors are individually or collectively operable to execute the code to cause the memory system to: read the data from the set of memory cells; and write the data to a second set of memory cells of the memory system that are different from the set of memory cells (Yu-Ming, “device controller 112 is configured to send data and a write command to instruct the memory 116 to store the data to a specified address” Col. 9, line 54-56 & Zhen, “The array control circuit may perform a data read operation, a data write operation” Col. 11, lines 6-7).
Referring to claim 4, Yu-Ming in view of Zhen discloses wherein, to determine whether to refresh the set of memory cells, the one or more processors are individually or collectively operable to execute the code to cause the memory system to (Zhen, “The control circuit compares the error bit count obtained in the starting step S10 with the new error bit count obtained in the steps S21 to S22” Col. 16, line 37-39): compare the bit error count to the threshold bit error count (Zhen, "generate a refresh command according to a failed bit count (abbreviated to fbc) or a bit error rate of data read from the memory device" Col. 10, line 26-28); and determine to refrain from refreshing the set of memory cells based at least in part on the bit error count being less than the threshold bit error count (Yu-Ming, “parameters include at least one of a failed bit count in the second reading output” Col. 2, line 39-40).
Referring to claim 5, Yu-Ming in view of Zhen discloses wherein the one or more processors are individually or collectively further operable to execute the code to cause the memory system to: apply, as part of a coarse calibration operation to determine the one or more parameters, a default read voltage to the set of memory cells (Yu-Ming, “the memory-side read circuit is configured to determine the second read voltage using a valley-tracking read scheme based on a valley-tracking range determined by the memory controller” Col. 4, line 34-37); and determine, based at least in part on the coarse calibration operation, a second bit error count associated with the set of memory cells, wherein the one or more parameters are based at least in part on the second bit error count, and wherein retrieving the entry is based at least in part on the one or more parameters and a fine calibration operation (Yu-Ming, “the read voltage and associated information such as the second set of parameters, can be used to calibrate” Col.10, line 67 – col.11 line 1).
Referring to claim 6, Yu-Ming in view of Zhen discloses wherein: each memory cell of the set of memory cells is programmed to a voltage level of a set of voltage levels that represent the data, and a second magnitude of the default read voltage is based at least in part on a highest voltage level of the set of voltage levels (Yu-Ming, “The verified read voltages are in a static order according to corresponding priority levels” Col. 6, line 34-35).
Referring to claim 7, Yu-Ming in view of Zhen discloses wherein the one or more processors are individually or collectively further operable to execute the code to cause the memory system to: adjust, as part of a fine calibration operation and based at least in part on the entry, a second magnitude of a default read voltage to obtain the magnitude of the read voltage, wherein applying the read voltage to the set of memory cells is based at least in part on the fine calibration operation (Yu-Ming, “Data is first read with a first priority verified voltage; if a reading output of the data fails to pass an ECC test, a second priority verified voltage is then used.” Col. 6, lines 26-39).
Referring to claim 8, Yu-Ming in view of Zhen discloses wherein the one or more parameters comprise a temperature associated with the memory system, a second bit error count associated with the memory system, or both (Yu-Ming, “first set of parameters includes at least one of address information, a number of P/E cycles, a reading temperature” Col. 2, line 35-37 & “parameters include at least one of a failed bit count in the second reading output” Col. 2, line 39-40).
Referring to method claims 9-16 and non-transitory CRM claims 17-24, the claims recite similar limitations as found in memory system claims 1-8, therefore, are similarly rejected as unpatentable over Yu-Ming in view of Zhen.
Conclusion
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Justin R. Knapp
Primary Examiner
Art Unit 2112
/JUSTIN R KNAPP/Primary Examiner, Art Unit 2112
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