DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
1.In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
2. Claims 1-2, 4-11, 13-21, 23-25 are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Gopalakrishnan et al. (Pub. No. US 20140029331)
As per claims 1, 10, 20, Gopalakrishnan discloses an apparatus for operating a memory system (fig.1, memory system 100), comprising:
drive a data strobe signal (paragraph 21, line 4, a strobe signal DQS) according to a first rate during a first duration of a data transfer operation and according to a second rate during a second duration of the data transfer operation (paragraph 21, data rates employ a strobe signal DQS with a different preamble time durations of a command clock time interval for each operation); and
transfer, via a data channel (paragraph 32, lines 2-3, transmits data stream along a given data path with an accompanying strobe signal generated in a strobe timing domain), data of a data burst (paragraph 24, line 6, an incoming burst of write data) to a memory device (fig.1, memory 104) of the memory system during the data transfer operation and based at least in part on driving the data strobe signal (paragraph 24, line 6, strobe enable DQS_EN signals initiated to alert and enable DRAM receiver circuitry to receive an incoming burst of write data) according to the first rate (paragraph 21, lines 2-3, selection between the modes generally depends on the memory device data rate) during the first duration of the data transfer operation and according to the second rate during the second duration of the data transfer operation (paragraph 33, the timing associated with the creation of parallel data transfer depends on the memory device mode of operation).
As per claims 2, 11, 21, Gopalakrishnan discloses wherein, to transfer the data of the data burst, the processing circuitry is configured to cause the apparatus to: transfer the data of the data burst (paragraph 24, line 6, an incoming burst of write data) from a memory controller (fig.1, a memory controller 102) of the memory system to the memory device of the memory system; or receive the data of the data burst at the memory device from a host system (paragraph 24, line 6, strobe enable DQS_EN signals initiated to alert and enable DRAM receiver circuitry to receive an incoming burst of write data).
As per claims 4, 13, 23, Gopalakrishnan discloses wherein the processing circuitry is further configured to cause the apparatus to: drive the data strobe signal according to a third rate during a third duration of the data transfer operation that is after the first duration and before the second duration, wherein the third rate is greater than the first rate and less than the second rate (paragraph 21, lines 4-6, employ a strobe signal DQS with a different preamble time duration (e.g., that is approximately 0.35t.sub.CK (where t.sub.CK represents the duration of a command clock time interval)).
As per claim 14, Gopalakrishnan discloses wherein driving the data strobe signal according to the first rate during the first duration and according to the second rate applicable during the second duration is based at least in part on a read strobe signal that is driven according to the first rate during a third duration of the data transfer operation and driven according to the second rate during a fourth duration of the data transfer operation(paragraph 21, lines 4-6, employ a strobe signal DQS with a different preamble time duration (e.g., that is approximately 0.35t.sub.CK (where t.sub.CK represents the duration of a command clock time interval)).
As per claims 5, 15, 24, Gopalakrishnan discloses wherein transferring the data of the data burst is in accordance with the first rate during the first duration and the second rate during the second duration of the data transfer operation (paragraph 24, line 6, strobe enable DQS_EN signals initiated to alert and enable DRAM receiver circuitry to receive an incoming burst of write data).
As per claims 6, 16, 25, Gopalakrishnan discloses wherein: transferring the data of the data burst is in accordance with the second rate during the first duration and the second duration of the data transfer operation(paragraph 21, lines 4-6, data rates up to 1.6 Gb/s often employ a strobe signal DQS with a preamble time duration that is approximately 0.35t.sub.CK (where t.sub.CK represents the duration of a command clock time interval)), and a starting time for transferring the data is based at least in part on an offset value from a start of the first duration (paragraph 24, lines 4-5, an initial reference point TO, respective "start of packet" SOP and strobe enable DQS_EN signals).
As per claims 7, 17, Gopalakrishnan discloses wherein the first rate is less than the second rate (paragraph 21, lines 2-10, The selection between the modes generally depends on the memory device data rate and In the second mode of operation, the data rate is significantly higher, and the timing margins to correctly sample and process received write data correspondingly tighter as further cites at paragraph 27, lines 3-5)
As per claims 8, 18, Gopalakrishnan discloses wherein the first duration comprises one or more warm-up cycles of a warm-up period for the data transfer operation (paragraph 24, lines 3-5, programmed first write latency WL1 value of four clock cycles and a further half clock delay, referenced from an initial reference point TO, respective "start of packet" SOP and strobe enable DQS_EN signals).
As per claims 9, 19, Gopalakrishnan discloses wherein the data strobe signal comprises a single ended signal or a pair of differential signals (paragraph 36, lines 10-13, Signals and signaling paths shown or described as being single-ended may also be differential, and vice-versa).
Claim Rejections - 35 USC § 103
3. In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
4. Claims 3, 12, 22 are rejected under 35 U.S.C. 103 as being unpatentable over Gopalakrishnan et al. (Pub. No. US 20140029331) in view of Tatapudi et al. (Pub. No. US 20220011934)
As per claims 3, 12, 22, Gopalakrishnan discloses wherein the processing circuitry is further configured to cause the apparatus to: perform a write operation to write the data of the data burst to one or more memory of the memory device, wherein transferring the data of the data burst to one or more memory of the memory device is based at least in part on transferring the data of the data burst to the memory device of the memory system (paragraph 24, line 6, strobe enable DQS_EN signals initiated to alert and enable DRAM receiver circuitry to receive an incoming burst of write data).
Gopalakrishnan discloses all the limitations as the above but does not explicitly disclose perform a write operation to write the data to one or more memory cells of the memory device. However, Tatapudi discloses this (paragraph 38, lines 5-11, The memory die 200 may include one or more memory cells 205 that may each be programmable to store different logic states (e.g., programmed to one of a set of two or more possible states).
It would have been obvious to one with ordinary skill in the art before the effective filling date of the claimed invention was made to consider the teachings of Tatapudi with the teaching of Gopalakrishnan so as to hold data and instructions for programs and files that actively using by processor so as to yield the predicatable result so as to control efficiently, thus enhance the system performance.
5. The prior art made of record and not relied upon is considered pertinent to applicant’s disclosure.
Amarilio et al. [Pub. No. US20090251976] discloses the data strobe masking gating signal modifier is configured to be operative to center the expected data receipt duration indicating signal about the midpoint of the duration of the data transmission using the following functionality
Conclusion
6. Any inquiry concerning this communication or earlier communications from the examiner should be directed to KIM T HUYNH whose telephone number is (571)272-3635 or via e-mail addressed to [kim.huynh3@uspto.gov]. The examiner can normally be reached on M-F 7.00AM- 4:00PM. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Tsai Henry can be reached at (571)272-4176 or via e-mail addressed to [Henry.Tsai@USPTO.GOV].
The fax phone numbers for the organization where this application or proceeding is assigned are (571)273-8300 for regular communications and After Final communications. Any inquiry of a general nature or relating to the status of this application or proceeding should be directed to the receptionist whose telephone number is (571)272-2100.
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/K. T. H./
Examiner, Art Unit 2184
/HENRY TSAI/Supervisory Patent Examiner, Art Unit 2184
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