DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Drawings
The drawings are objected to under 37 CFR 1.83(a). The drawings must show every feature of the invention specified in the claims. Therefore, the seventh through twelfth patches overlapping configurations/orientations of first through sixth patches as claimed must be shown or the feature(s) canceled from the claim(s). No new matter should be entered.
Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. The figure or figure number of an amended drawing should not be labeled as “amended.” If a drawing figure is to be canceled, the appropriate figure must be removed from the replacement sheet, and where necessary, the remaining figures must be renumbered and appropriate changes made to the brief description of the several views of the drawings for consistency. Additional replacement sheets may be necessary to show the renumbering of the remaining figures. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13.
The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/patent/patents-forms. The actual filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIA /25, or PTO/AIA /26) should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to www.uspto.gov/patents/apply/applying-online/eterminal-disclaimer.
Claims 1-20 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1-19 of U.S. Patent No. 12, 315, 995. Although the claims at issue are not identical, they are not patentably distinct from each other because they contain substantially similar subject matter (see chart below).
Claims 2-12, 14-15 and 17-20 are also rejected as being dependent on claim 1 and may also correspond to claims 2-14 and 17-19 of the ‘995 patent.
Instant Application
US Patent No. 12,315,995
1. Apparatus comprising: a substrate; and an antenna on the substrate that includes a first patch, wherein the first patch has a first corner, a second corner, and a diagonal axis passing through the first and second corners, a conductive via in the substrate and coupled to the first patch along the diagonal axis, a second patch overlapping the first patch, a third patch separated from a first edge of the second patch by a first gap, a fourth patch separated from a second edge of the second patch by a second gap, a fifth patch separated from a third edge of the second patch by a third gap, and a sixth patch separated from a fourth edge of the second patch by a fourth gap.
1. An electronic device comprising: a housing having a dielectric wall; a display mounted to the housing opposite the dielectric wall; a substrate having a surface facing the dielectric wall; and an antenna configured to radiate through the dielectric wall, wherein the antenna includes a directly fed [first] patch embedded in [on] the substrate, wherein the directly fed [first] patch is rectangular and has a first corner, a second corner, and a diagonal axis passing through the first and second corners; a conductive via in the substrate and coupled to the directly fed patch along the diagonal axis; a first parasitic [second] patch on the surface of the substrate and overlapping the directly fed [first] patch, a second parasitic [third] patch on the surface of the substrate and separated from a first edge of the first parasitic [second] patch by a first gap, a third [fourth] parasitic patch on the surface of the substrate and separated from a second edge of the first parasitic [second] patch by a second gap, a fourth parasitic [fifth] patch on the surface of the substrate and separated from a third edge of the first parasitic [second] patch by a third gap, and a fifth parasitic [sixth] patch on the surface of the substrate and separated from a fourth edge of the first parasitic [second] patch by a fourth gap.
13. Apparatus comprising: a substrate; and a phased antenna array that includes a first antenna and a second antenna on the substrate, wherein the first antenna includes a first patch fed by a first conductive via in the substrate, a second patch overlapping the first patch, a third patch separated from a first edge of the second patch by a first gap, a fourth patch separated from a second edge of the second patch by a second gap, a fifth patch separated from a third edge of the second patch by a third gap, and a sixth patch separated from a fourth edge of the second patch by a fourth gap, the second antenna including a seventh patch fed by a second conductive via in the substrate, a center of the first patch and a center of the seventh patch being aligned along a linear axis, the seventh patch being square, the first, second, third, and fourth edges of the first patch being non- parallel and non-perpendicular with respect to the linear axis, and four edges of the seventh patch being non-parallel and non-perpendicular with respect to the linear axis.
15. An electronic device comprising: a housing having a dielectric wall; a display mounted to the housing opposite the dielectric wall; a substrate having a surface facing the dielectric wall; and a phased antenna array configured to radiate through the dielectric wall, wherein the phased antenna array includes a first antenna and a second antenna, and the first antenna includes a first directly fed patch embedded in the substrate, a first parasitic [second] patch on the surface of the substrate and overlapping the first directly fed patch, a second parasitic [third] patch on the surface of the substrate and separated from a first edge of the first parasitic [second] patch by a first gap, a third parasitic [fourth] patch on the surface of the substrate and separated from a second edge of the first [second] parasitic patch by a second gap, a fourth [fifth] parasitic patch on the surface of the substrate and separated from a third edge of the first parasitic [second] patch by a third gap, and a fifth parasitic [sixth] patch on the surface of the substrate and separated from a fourth edge of the first parasitic [second] patch by a fourth gap, wherein the second antenna includes a second [seventh] directly fed patch embedded in the substrate, a center of the first directly fed patch and a center of the second [seventh] directly fed patch are aligned along a linear axis, the second [seventh] directly fed patch is [being] square, the first, second, third, and fourth edges of the first directly fed patch are non-parallel and non-perpendicular with respect to the linear axis, and four edges of the second [seventh] directly fed patch are non-parallel and non-perpendicular with respect to the linear axis, the second antenna including a sixth parasitic patch on the surface of the substrate and overlapping the second directly fed patch, a seventh parasitic patch on the surface of the substrate and separated from a fifth edge of the sixth parasitic patch by a fifth gap, an eighth parasitic patch on the surface of the substrate and separated from a sixth edge of the sixth parasitic patch by a sixth gap, a ninth parasitic patch on the surface of the substrate and separated from a seventh edge of the sixth parasitic patch by a seventh gap, and a tenth parasitic patch on the surface of the substrate and separated from an eighth edge of the sixth parasitic patch by an eighth gap, wherein the sixth parasitic patch is square, the seventh, eighth, ninth, and tenth parasitic patches are polygonal and non-square, the linear axis overlaps first and second corners of the first parasitic patch, the linear axis overlaps third and fourth corners of the sixth parasitic patch, and the linear axis does not overlap the second, third, fourth, fifth, seventh, eighth, ninth, and tenth parasitic patches.
18. An antenna module comprising: a substrate; and an antenna on the substrate, wherein the antenna includes a rectangular metal patch having a diagonal axis, an antenna feed terminal coupled to the rectangular metal patch along the diagonal axis, a first patch overlapping the rectangular metal patch, a second patch separated from a first edge of the first patch by a first gap, a third patch separated from a second edge of the first parasitic patch by a second gap, a fourth patch separated from a third edge of the first parasitic patch by a third gap, and a fifth patch separated from a fourth edge of the first parasitic patch by a fourth gap.
16. An electronic device comprising: a housing that includes a dielectric wall; a display mounted to the housing opposite the dielectric wall; a substrate, wherein a surface of the substrate faces the dielectric wall; and an antenna [module] configured to convey radio-frequency signals through the dielectric wall, wherein the antenna includes a rectangular metal patch embedded in the substrate and having a diagonal axis, an antenna feed terminal coupled to the rectangular metal patch along the diagonal axis; a first [parasitic] patch on the surface of the substrate and overlapping the rectangular metal patch, a second [parasitic] patch on the surface of the substrate and separated from a first edge of the first [parasitic] patch by a first gap, a third [parasitic] patch on the surface of the substrate and separated from a second edge of the first [parasitic] patch by a second gap, a fourth [parasitic] patch on the surface of the substrate and separated from a third edge of the first [parasitic] patch by a third gap, and a fifth [parasitic] patch on the surface of the substrate and separated from a fourth edge of the first [parasitic] patch by a fourth gap.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Jason M Crawford whose telephone number is (571)272-6004. The examiner can normally be reached Mon-Thurs 6:30am-3:00pm, Fri 6:30am-12:30pm.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Alexander Taningco can be reached at 571-272-8048. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/JASON M CRAWFORD/Primary Examiner, Art Unit 2845
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