DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 05/09/2025, 05/09/2025 are in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statements are being considered by the examiner.
Non-Statutory Type Double Patenting
The non-statutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper time wise extension of the "right to exclude" granted by a patent and to prevent possible harassment by multiple assignees. A non-statutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Langi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Omum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on non-statutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP §§ 706.02(1)(1) - 706.02(1)(3) for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/patenVpatents-forms. The filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIN25, or PTO/AIN26) should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to www.uspto.gov/patents/process/file/efs/guidance/eTD-info-l.isp
"A later patent claim is not patentably distinct from an earlier patent claim if the later claim is obvious over, or anticipated by the earlier claim. ln re Longi- 759 F.2d at 896, 225 USPQ at 651 (affirming a holding of obviousness-type double patenting because the claims at issue were obvious over claims in four prior art patents); In re Berg, 140 F.3d at 1437, 46 USPQ2d at 1233 (Fed. Cir. 1998) (affirming a holding of obviousness-type double patenting where a patent application claim to a genus is anticipated by a patent claim to a species within that genus). " ELI LILLY AND COMPANY v BARR LABORATORIES, INC., United States Court of Appeals for the Federal Circuit, ON PETITION FOR REHEARING EN BANC (DECIDED: May 30, 2001).
Claims 1-20 are rejected on the ground of non-statutory double patenting as being unpatentable over claims 1-20 of reference patent 12314181. Although the claims at issue are not identical, they are not patentably distinct from each other because the claims of the instant applications are matching in contents (while language is different) to reference claim 1-20 of reference patent 12314181.
Regarding claim 8, claim 1 of reference patent 12314181 as shown in the table below (also included in the attached OA.APPENDIX titled doublepatentingmap.pdf) contains the mapping of the claims in the instant application and the claims of reference patent 12314181. It seems that all the claim elements of the instant claim 8 are matching in contents (while language is different) to reference claim 1 of reference patent 12314181. There is no new patentably distinct claim element in the instant claim. Instant claim 8 is in fact a subset of reference claim 1.
Regarding claim 9, claim 2 of reference patent 12314181 as shown in the table below (also included in the attached OA.APPENDIX titled doublepatentingmap.pdf) contains the mapping of the claims in the instant application and the claims of reference patent 12314181. It seems that all the claim elements of the instant claim 9 are matching in contents (while language is different) to reference claim 2 of reference patent 12314181. There is no new patentably distinct claim element in the instant claim.
Regarding claim 10-13, combination of claims 3-7 of reference patent 12314181 as shown in the table below (also included in the attached OA.APPENDIX titled doublepatentingmap.pdf) contains the mapping of the claims in the instant application and the claims of reference patent 12314181. It seems that all the claim elements of the instant claims 10-13 are matching in contents (while language is different) to the combination of reference claims 3-7 of reference patent 12314181. There is no new patentably distinct claim element in the instant claim.
The instant claims 10-13 in combination teaches - writing memory access command to the storage access queue in the first memory, retrieving the command from the queue and executes it.
The reference claims 3-7 in combination teaches - transmitting/writing memory access command (to access storage/second memory/non-volatile memory using second protocol) to first memory and retrieving first data from non-volatile storage (second memory) executing the stored/transmitted command that uses second protocol. Translating logical address to a physical address is implied in executing memory access command.
Regarding claim 14, combination of claims 8-10 of reference patent 12314181 as shown in the table below (also included in the attached OA.APPENDIX titled doublepatentingmap.pdf) contains the mapping of the claims in the instant application and the claims of reference patent 12314181. It seems that all the claim elements of the instant claim 14 are matching in contents (while language is different) to combination of reference claims 8-10 of reference patent 12314181. There is no new patentably distinct claim element in the instant claim.
Instant claim 14 teaches the same as instant claims 10-13 but does it for a write command. Reference claims 8-10 do the same for a write command.
Regarding claim 1, this is a device claim corresponding to method claim 8 and suffers the same double patenting issue as in claim 8 and is rejected for the same reason as shared in claim 8.
Regarding claim 2, this is a device claim corresponding to method claim 9 and suffers the same double patenting issue as in claim 9 and is rejected for the same reason as shared in claim 9.
Regarding claim 3, this is a device claim corresponding to method claim 10 and suffers the same double patenting issue as in claim 10 and is rejected for the same reason as shared in claim 10.
Regarding claim 4, this is a device claim corresponding to method claim 11 and suffers the same double patenting issue as in claim 11 and is rejected for the same reason as shared in claim 11.
Regarding claim 5, this is a device claim corresponding to method claim 12 and suffers the same double patenting issue as in claim 12 and is rejected for the same reason as shared in claim 12.
Regarding claim 6, this is a device claim corresponding to method claim 14 and suffers the same double patenting issue as in claim 14 and is rejected for the same reason as shared in claim 14.
Regarding claim 7, this is a device claim corresponding to method claim 13 and suffers the same double patenting issue as in claim 13 and is rejected for the same reason as shared in claim 13.
Regarding claim 15, this is a computer storage medium (CSM) claim corresponding to method claim 8 and suffers the same double patenting issue as in claim 8 and is rejected for the same reason as shared in claim 8.
Regarding claim 16, this is a computer storage medium (CSM) claim corresponding to method claim 9 and suffers the same double patenting issue as in claim 9 and is rejected for the same reason as shared in claim 9.
Regarding claim 17, this is a computer storage medium (CSM) claim corresponding to method claim 10 and suffers the same double patenting issue as in claim 10 and is rejected for the same reason as shared in claim 10.
Regarding claim 18, this is a computer storage medium (CSM) claim corresponding to method claim 11 and suffers the same double patenting issue as in claim 11 and is rejected for the same reason as shared in claim 11.
Regarding claim 19, this is a computer storage medium (CSM) claim corresponding to method claim 12 and suffers the same double patenting issue as in claim 12 and is rejected for the same reason as shared in claim 12.
Regarding claim 20, this is a computer storage medium (CSM) claim corresponding to method claim 14 and suffers the same double patenting issue as in claim 14 and is rejected for the same reason as shared in claim 14.
Instant claims: 19/195,623
Ref patent: 12314181, app:18/432,518
claim 8
claim 1
A method, comprising:
A method, comprising:
communicating, by a device via an interface of the device, with a host system, the device having:
establishing a connection between a host system and a memory sub-system;
a first memory accessible via the interface to the host system using a first protocol of cache-coherent memory access; and
attaching a portion of a random access memory of the memory sub-system as a memory device accessible to the host system over the connection using a first protocol of cache-coherent memory access;
a second memory accessible to the host system using a second protocol of storage access;
providing, by the memory sub-system using a non-volatile memory of the memory sub-system, storage services accessible over the connection using a second protocol of storage access;
storing, by the device in response to the host system using the first protocol, a command in the first memory, the command configured to access the second memory using the second protocol;
configuring one or more storage access queues in the memory device implemented using the portion of the random access memory of the memory sub-system;
executing, by the device, the command of the second protocol and stored in the first memory.
receiving, in the one or more storage access queues, a storage access message from the host system using the first protocol of cache-coherent memory access; and
performing, by the memory sub-system, a storage access operation in the non-volatile memory of the sub-system using the storage access message in the one or more storage access queues.
claim 9
claim 2
The method of claim 8, wherein the first protocol is in accordance with a standard of compute express link (CXL).
The method of claim 1, wherein the connection is in accordance with a standard of computer express link (CXL).
claim 10
claim 3
The method of claim 8, wherein a storage access queue is configured in the first memory to accept the host system storing the command via the first protocol into the storage access queue.
The method of claim 2, wherein the storage access message is transmittable from the host system to the memory sub-system over the connection using the second protocol of storage access.
claim 11
claim 4
The method of claim 10, further comprising:
The method of claim 3, wherein the storage access message includes a read command; and
retrieving, by the device, the command from the storage access queue for execution.
the storage access operation includes execution of the read command to retrieve first data from the non-volatile memory of the memory sub-system.
claim 12
claim 5
The method of claim 11, wherein the execution of the command in the device includes reading data from the second memory from a location identified via a logical block address.
The method of claim 4, further comprising: providing, by the memory sub-system, the first data in the memory device for retrieval using the first protocol of cache-coherent memory access.
claim 13
claim 6
The method of claim 12, further comprising: translating, by the device, the logical block address into a physical address in the second memory.
The method of claim 5, wherein the first data is provided in the one or more storage access queues.
claim 7
The method of claim 4, further comprising: providing, by the memory sub-system, the first data to the host system over the connection using the second protocol of storage access.
claim 14
claim 8
The method of claim 11, wherein the executing of the command in the device includes writing data to the second memory at a location identified via a logical block address.
The method of claim 3, wherein the storage access message includes a write command; and
the method further comprises: receiving, by the memory sub-system from the host system over the connection using the first protocol of cache-coherent memory access, second data, wherein the storage access operation includes execution of the write command to write the second data into the non-volatile memory of the memory sub-system.
claim 9
The method of claim 8, wherein the second data is received from the host system over the connection using the first protocol of cache-coherent memory access in the one or more storage access queues.
claim 10
The method of claim 3, wherein the storage access message includes a write command; and
the method further comprises:
receiving, by the memory sub-system from the host system over the connection using the second protocol of storage access, second data, wherein the storage access operation includes execution of the write command to write the second data into the non-volatile memory of the memory sub-system.
Potential Allowable Subject Matter
Claims 1-20 are currently not rejected in view of prior art on the grounds of 35 U.S.C 102/103, and could become allowable subject matter if the double patenting rejection is overcome.
Claim 8 recites "A method, comprising:
communicating, by a device via an interface of the device, with a host system, the device having:
a first memory accessible via the interface to the host system using a first protocol of cache-coherent memory access; and
a second memory accessible to the host system using a second protocol of storage access;
storing, by the device in response to the host system using the first protocol, a command in the first memory, the command configured to access the second memory using the second protocol;
executing, by the device, the command of the second protocol and stored in the first memory.”
Prior art like KIM (US 20240118839 A1)[Kim] [011O] Fig. 4: teaches a memory device 110 of the external memory system 100 including a host accessible area 410. However, Kim does not teach that the memory accessible via the interface to the host system using a first protocol of cache-coherent memory access and does not teach accessing a second memory using a second protocol of storage access and storing a command in the first memory.
Prior Art like Kagan (US 20150261434 A1) [0019] teaches having queue storing storage access commands. Instant claim teaches storing command in the first memory. Having queue indicates a means to store command and is similar to the teachings in the instant claim element. However, Kagan teaches a network of servers connected through server network interface controller (NIC) and upon receiving a storage access command in accordance with the protocol, initiates a remote direct memory access (RDMA) operation performed by the host and server NICs so as to execute on the storage server, via the network, a storage transaction specified by the command.
Prior Art like Lin (US 20030033474 A1) [0018] teaches storage access request being completed indicating execution of storage access operation. Any system that uses storage access command or access request ultimately executes the command and accesses memory. There is nothing innovative in this claim element.
Prior Art like SHAO (US 20170004101 A1)[Shao] [0074]: teaches implementing cache-coherent memory access. However, Shao is focused on data copying method that includes reading, by a DMA controller, target data from storage space corresponding to a source physical address of the target data by using an ACP and storing, by the DMA controller, the target data into storage space corresponding to a destination physical address of the target data by using the ACP.
More prior arts are shared in pe2e_search_notes attached as OA.APPENDIX.
While the prior arts Kim/Kagan/Lin/Shao teaches different claim elements, the contexts of the teachings are different. It does not seem obvious combining these teachings by a person ordinarily skilled in the art to develop the teaching in the instant claim. Examiner considers combining all the teachings as not merely a work of a carpenter but involves some level innovative idea.
No known prior art taken alone or in combination teaches a device having a first memory accessible via the interface to the host system using a first protocol of cache-coherent memory access; and a second memory accessible to the host system using a second protocol of storage access where second memory is accessed by placing/storing a command in the first memory and executing the command.
Independent claim 1 is a device claim, corresponding to method claim 8 and presents a combination of limitations similar to those presented in the method claim 8 and is allowable for the same reason.
Independent claim 15 is a computer storage medium claim corresponding to the method claim 8 and presents a combination of limitations similar to those presented in the method claim 8 and is allowable for the same reason.
Claims 9-14 are dependent on claim 8 and is allowable for the same reason due at least to this dependence.
Claims 2-7 are dependent on claim 1 and is allowable for the same reason due at least to this dependence.
Claims 16-20 are dependent on claim 15 and is allowable for the same reason due at least to this dependence.
Any comments considered necessary by applicant must be submitted no later than the payment of the issue fee and, to avoid processing delays, should preferably accompany the issue fee. Such submissions should be clearly labeled "Comments on Statement of Reasons for Allowance."
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure and is included in pe2e_search_notes and is attached as OA.APPENDIX.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to MOHAMMAD S HASAN whose telephone number is (571)270-1737. The examiner can normally be reached on Mon-Fri 8-5.
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/M.S.H/Examiner, Art Unit 2138
/SHAWN X GU/
Primary Examiner, AU2138
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