DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Priority
Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55.
Inventorship
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-3 and 20 are rejected under 35 U.S.C. 103 as being unpatentable over U.S. Pub. No. 2022/0013618 by Park et al. (“Park”) in view of Chinese Pub. No. CN 113838399 A by Deng et al. (“Deng”).
As to claim 1, Park discloses a display panel (Park, display device, Figure 1), comprising a display area (Park, display area DA, Figure 1) and a hole-digging area (Park, hole HL and hole edge area HEA, Figure 1) surrounded by the display area;
wherein the display panel comprises a plurality of first scanning signal lines (Park, scan lines SL, Figures 2 and 5), the plurality of first scanning signal lines comprise a plurality of first type scanning signal lines (Park, scan lines SL, Figures 2 and 5), each of the plurality of first type scanning signal lines comprises a first part (Park, left horizontal side of first scan line SL1, Figure 5), a second part (Park, right horizontal side of first scan line SL1, Figure 5), and a third part (Park, curved part of first scan line SL1, Figure 5), the first part and the second part are respectively located on opposite two sides of the hole-digging area and extend along a first direction (Park, left and right horizontal sides of first scan line SL1 on opposite sides of the hole edge area HEA, Figure 5), the third part is connected between the first part and the second part (Park, the curved part of first scan line SL1 is between the left and right horizontal sides, Figure 5), and an extension line of the first part passes through the hole-digging area (Park, first scan line SL1 within the hole edge area HEA, Figure 5);
Park does not expressly teach
wherein a unit length impedance of the third part is greater than a unit length impedance of the first part and a unit length impedance of the second part.
Deng teaches a display panel wherein a unit length impedance of the third part is greater than a unit length impedance of the first part and a unit length impedance of the second part (Deng, The resistance per unit length of the second sub-data line 122 of the central wiring area AA21 is r1 (which is equivalent to a straight part of Park), and the resistance per unit length of the second sub-data line 122 of the edge wiring area AA22 is r2 (which is equivalent to the curve part of Park), where r1 < r2. Figure 2, ¶ [0028]. It is noted that resistance R= V/I and impedance Z also = V/I. Therefore, the unit length impedance of AA22 is greater than a unit length impedance AA21).
The combination of Park and Deng teaches the first and second parts having a lower impedance per unit length than the third part.
At the time before the effective filing date of the claimed invention, it would have been obvious to one of ordinary skill in the art to modify Park’s scan lines to include Deng’s wiring lines around the hole because such a modification is the result of combining prior art elements according to known methods to yield predictable results. More specifically, Park’s scan lines as modified by Deng’s wiring lines around the hole is known to yield a predictable result of teaches a known resistance for the lines provides improved reliability for the driving signals as the current and voltage levels are more accurately determined. Thus, a person of ordinary skill would have appreciated including in Park’s scan lines the ability to do Deng’s wiring lines around the hole since the claimed invention is merely a combination of old elements, and in the combination each element merely would have performed the same function as it did separately, and one of ordinary skill in the art would have recognized that the results of the combination were predictable.
Thus, Park, as modified by Deng, teaches curved part of the scan lines have different resistances per unit length than the straight parts.
As to claim 2, Park, as modified by Deng, teaches the display panel wherein a line width of the third part is less than a line width of the first part and a line width of the second part (Deng, the line width w2 of the second sub-data line 1222 of the edge wiring area AA22 can be gradually narrowed along the second direction Y and from the center C of the high-transmittance area to the edge, Figure 2, ¶ [0052]). In addition, the motivation is the same as in the rejection of claim 1.
As to claim 3, Park, as modified by Deng, teaches the display panel wherein the plurality of first scanning signal lines farther comprise a plurality of second type scanning signal lines extending along the first direction, and the line width of the third part is less than a line width of each of the plurality of second type scanning signal lines (Deng, the line width w2 of the second sub-data line 1222 of the edge wiring area AA22 can be gradually narrowed along the second direction Y and from the center C of the high-transmittance area to the edge, Figure 2, ¶ [0052]). In addition, the motivation is the same as in the rejection of claim 1.
As to claim 20, Park discloses a display device, comprising a display panel (Park, display device, Figure 1), wherein the display panel comprises a display area (Park, display area DA, Figure 1) and a hole-digging area (Park, hole HL and hole edge area HEA, Figure 1) surrounded by the display area;
wherein the display panel comprises a plurality of first scanning signal lines (Park, scan lines SL, Figures 2 and 5), the plurality of first scanning signal lines comprise a plurality of first type scanning signal lines (Park, scan lines SL, Figures 2 and 5), each of the plurality of first type scanning signal lines comprises a first part (Park, left horizontal side of first scan line SL1, Figure 5), a second part (Park, right horizontal side of first scan line SL1, Figure 5), and a third part (Park, curved part of first scan line SL1, Figure 5), the first part and the second part are respectively located on opposite two sides of the hole-digging area and extend along a first direction (Park, left and right horizontal sides of first scan line SL1 on opposite sides of the hole edge area HEA, Figure 5), the third part is connected between the first part and the second part (Park, the curved part of first scan line SL1 is between the left and right horizontal sides, Figure 5), and an extension line of the first part passes through the hole-digging area (Park, first scan line SL1 within the hole edge area HEA, Figure 5);
Park does not expressly teach
wherein a unit length impedance of the third part is greater than a unit length impedance of the first part and a unit length impedance of the second part.
Deng teaches a display panel wherein a unit length impedance of the third part is greater than a unit length impedance of the first part and a unit length impedance of the second part (Deng, The resistance per unit length of the second sub-data line 122 of the central wiring area AA21 is r1 (which is equivalent to a straight part of Park), and the resistance per unit length of the second sub-data line 122 of the edge wiring area AA22 is r2 (which is equivalent to the curve part of Park), where r1 < r2. Figure 2, ¶ [0028]. It is noted that resistance R= V/I and impedance Z= V/I. Therefore, the unit length impedance of AA22 is greater than a unit length impedance AA21).
The combination of Park and Deng teaches the first and second parts having a lower resistance per unit length than the third part.
At the time before the effective filing date of the claimed invention, it would have been obvious to one of ordinary skill in the art to modify Park’s scan lines to include Deng’s wiring lines around the hole because such a modification is the result of combining prior art elements according to known methods to yield predictable results. More specifically, Park’s scan lines as modified by Deng’s wiring lines around the hole is known to yield a predictable result of teaches a known resistance for the lines provides improved reliability for the driving signals as the current and voltage levels are more accurately determined. Thus, a person of ordinary skill would have appreciated including in Park’s scan lines the ability to do Deng’s wiring lines around the hole since the claimed invention is merely a combination of old elements, and in the combination each element merely would have performed the same function as it did separately, and one of ordinary skill in the art would have recognized that the results of the combination were predictable.
Thus, Park, as modified by Deng, teaches curved part of the scan lines have different resistances per unit length than the straight parts.
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13.
The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/patent/patents-forms. The actual filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIA /25, or PTO/AIA /26) should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to www.uspto.gov/patents/apply/applying-online/eterminal-disclaimer.
Claims 1, 4 and 20 are rejected on the ground of nonstatutory double patenting as being unpatentable over claim 1 of U.S. Patent No. 12,293,701 in view of Chinese Pub. No. CN 113838399 A by Deng et al. (“Deng”).
Instant application Claims 1 and 4
Parent Patent No. 12,293,701 Claim 1
(Claim 1) A display panel, comprising a display area and a hole-digging area surrounded by the display area;
A display panel, comprising a display area and a hole-digging area surrounded by the display area, wherein the display panel comprises a plurality of light- emitting devices arranged in an array and a pixel driving circuit driving the plurality of light- emitting devices, and the pixel driving circuit comprises:
a driving transistor;
a switching transistor, connected to the driving transistor at a first node;
a compensation transistor, connected to a first scanning signal line, wherein the compensation transistor, the driving transistor, and the plurality of light-emitting devices are connected at a second node; and
a first initialization transistor, connected to a second scanning signal line, wherein the first initialization transistor, the driving transistor, and the compensation transistor are connected at a third node;
(Claim 1) wherein the display panel comprises a plurality of first scanning signal lines, the plurality of first scanning signal lines comprise a plurality of first type scanning signal lines, each of the plurality of first type scanning signal lines comprises a first part, a second part, and a third part, the first part and the second part are respectively located on opposite two sides of the hole-digging area and extend along a first direction, the third part is connected between the first part and the second part, and an extension line of the first part passes through the hole-digging area; and
wherein part of the first scanning signal line comprises a first part located at a left side of the hole-digging area, a second part located at a right side of the hole-digging area, and a third part connected to the first part and the second part, and an extension line of the first part passes through the hole-digging area; and/or, part of the second scanning signal line comprises a fourth part located at the left side of the hole-digging area, a fifth part located at the right side of the hole- digging area, and a sixth part connected to the fourth part and the fifth part, and an extension line of the fourth part passes through the hole-digging area; and
(Claim 4) 4. The display panel according to claim 1, further comprising:
the display panel further comprising:
(Claim 4) a substrate;
a substrate;
(Claim 4) a first active layer disposed on a side of the substrate;
a first active layer, disposed on a side of the substrate;
(Claim 4) a first metal layer disposed on a side of the first active layer away from the substrate;
a first metal layer, disposed on a side of the first active layer away from the substrate;
(Claim 4) a second metal layer disposed on a side of the first metal layer away from the first active layer;
a second metal layer, disposed on a side of the first metal layer away from the first active layer;
(Claim 4) a second active layer disposed on a side of the second metal layer away from the first metal layer; and
a second active layer, disposed on a side of the second metal layer away from the first metal layer; and
(Claim 4) a third metal layer disposed on a side of the second active layer away from the second metal layer;
a third metal layer, disposed on a side of the second active layer away from the second metal layer;
(Claim 4) wherein the third part is disposed in at least one of the first metal layer, the second metal layer, and the third metal layer.
wherein the third part is disposed in at least one of the first metal layer, the second metal layer, and the third metal layer, and the sixth part is disposed in at least one of the first metal layer, the second metal layer, and the third metal layer.
The parent patent does not expressly teach (Claim 1) wherein a unit length impedance of the third part is greater than a unit length impedance of the first part and a unit length impedance of the second part.
However, Deng teaches a display panel (Claim 1) wherein a unit length impedance of the third part is greater than a unit length impedance of the first part and a unit length impedance of the second part (Deng, The resistance per unit length of the second sub-data line 122 of the central wiring area AA21 is r1 (which is equivalent to a straight part of Park), and the resistance per unit length of the second sub-data line 122 of the edge wiring area AA22 is r2 (which is equivalent to the curve part of Park), where r1 < r2. Figure 2, ¶ [0028]. It is noted that R= V/I and Z= V/I. Therefore, the unit length impedance of AA22 is greater than a unit length impedance AA21).
At the time before the effective filing date of the claimed invention, it would have been obvious to one of ordinary skill in the art to modify Parent Patent No. 12,293,701 to include Deng’s wiring lines around the hole because such a modification is the result of combining prior art elements according to known methods to yield predictable results. More specifically, Deng’s wiring lines around the hole is known to yield a predictable result of teaches a known resistance for the lines provides improved reliability for the driving signals as the current and voltage levels are more accurately determined. Thus, a person of ordinary skill would have appreciated including in Parent Patent No. 12,293,701 scan lines the ability to do Deng’s wiring lines around the hole since the claimed invention is merely a combination of old elements, and in the combination each element merely would have performed the same function as it did separately, and one of ordinary skill in the art would have recognized that the results of the combination were predictable.
Thus, these claims are rejected based on the obviousness type non-statutory double patenting.
In addition, claim 20, of the instant application, is similarly rejected in this way as it includes nearly identical limitations as claim 1, of the instant application.
Allowable Subject Matter
Claims 4-19 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims and overcome the obvious type double patenting rejection.
As to dependent claims 5-19, these claims are objected to for the same reasons as objected dependent claim 4 as they depend upon objected dependent claim 4.
Reasons for Allowance
As to claim 4, Park, as modified by Deng, teaches the display panel further comprising:
a substrate (Park, substrate 100, Figure 4);
a first active layer (Park, first semiconductor pattern A1, Figure 4) disposed on a side of the substrate;
a first metal layer (Park, first gate electrode G1, Figure 4) disposed on a side of the first active layer away from the substrate;
a second metal layer (Park, second capacitor electrode Cst2, Figure 4) disposed on a side of the first metal layer away from the first active layer;
a second active layer (Park, first electrode 160, Figure 4) disposed on a side of the second metal layer away from the first metal layer; and
a third metal layer (Park, second electrode 190, Figure 4) disposed on a side of the second active layer away from the second metal layer;
Park additionally teaches the scan lines layered as shown in figure 6. However, figure 6 of Park does not teach the multiple active and metal layers which includes parts of the scan lines as recited in the claims.
Park does not expressly teach
wherein the third part is disposed in at least one of the first metal layer, the second metal layer, and the third metal layer.
In addition, no other prior art was found which teaches, alone or in combination, the cited limitations.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to BRENT D CASTIAUX whose telephone number is (571)272-5143. The examiner can normally be reached Mon-Fri 7:30 AM- 4:00 PM.
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/BRENT D CASTIAUX/Primary Examiner, Art Unit 2623