Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the claims at issue are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); and In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on a nonstatutory double patenting ground provided the reference application or patent either is shown to be commonly owned with this application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The USPTO internet Web site contains terminal disclaimer forms which may be used. Please visit http://www.uspto.gov/forms/. The filing date of the application will determine what form should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to http://www.uspto.gov/patents/process/file/efs/guidance/eTD-info-I.jsp.
The patent claims include all of the limitations of the instant application claims, respectively. The patent claims also include additional limitations. Hence, the instant application claims are generic to the species of invention covered by the respective patent claims. As such, the instant application claims are anticipated by the patent claims and are therefore not patentably distinct therefrom. (See Eli Lilly and Co. v. Barr Laboratories Inc., 58 USPQ2D 1869, "a later genus claim limitation is anticipated by, and therefore not patentably distinct from, an earlier species claim", In re Goodman, 29 USPQ2d 2010, "Thus, the generic invention is 'anticipated' by the species of the patented invention" and the instant “application claims are generic to species of invention covered by the patent claim, and since without terminal disclaimer, extant species claims preclude issuance of generic application claims”).
Claims 1-20 are rejected on the ground of nonstatutory obviousness-type double patenting as being unpatentable over claims 1-20 of U.S. Patent No. 12327527.
The present application claims the same subject matter of gate driver unit and display panel, which is same as the US patent 12327527.
For example:
19/195,695
12/327,527
1. A gate driver unit comprising a plurality of gate driver circuits, at least one of the gate driver circuits each comprising: a first node control module electrically connected to a first node of the gate driver circuit at a present stage and a second node of the gate driver circuit at the present stage, and configured to transmit a first power supply signal to the first node according to a potential of the second node and a corresponding first clock signal, or transmit a second power supply signal to the first node according to the potential of the second node; an output control module electrically connected to the first node of the gate driver circuit and a third node of the gate driver circuit at the present stage, and configured to electrically connect the first node and the third node, or to disconnect an electrical connection between the first node and the third node; and a second output module electrically connected to the second node, the third node, and a second output terminal of the gate driver circuit at the present stage, and configured to output a corresponding second clock signal or the first power supply signal to the second output terminal according to the potential of the second node and a potential of the third node; and
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wherein at least one of the first node control module and the output control module is electrically connected to the second node of the gate driver circuit at a preceding stage.
1. A gate driver unit comprising a plurality of gate driver circuits, at least one of the gate driver circuits each comprising: a first node control module electrically connected to a first node of the gate driver circuit at a present stage and a second node of the gate driver circuit at the present stage, and configured to transmit a first power supply signal to the first node according to a potential of the second node and a corresponding first clock signal, or transmit a second power supply signal to the first node according to the potential of the second node; a first output module electrically connected to the first node of the gate driver circuit at the present stage and a first output terminal of the gate driver circuit at the present stage, and configured to output the second power supply signal or a third power supply signal to the first output terminal according to a potential of the first node; an output control module electrically connected to the first node of the gate driver circuit and a third node of the gate driver circuit at the present stage, and configured to electrically connect the first node and the third node, or to disconnect an electrical connection between the first node and the third node; and a second output module electrically connected to the second node, the third node, and a second output terminal of the gate driver circuit at the present stage, and configured to output a corresponding second clock signal or the first power supply signal to the second output terminal according to the potential of the second node and a potential of the third node; and wherein at least one of the first node control module and the output control module is electrically connected to the second node of the gate driver circuit at a preceding stage.
2. The gate driver unit according to claim 1, wherein the first node control module of an n-th-stage gate driver circuit of the plurality of gate driver circuits is electrically connected to the second node of an (n-1)-th-stage gate driver circuit of the plurality of gate driver circuits, and the first node control module of the n-th-stage gate driver circuit is configured to transmit the first power supply signal or a fourth power supply signal to the first node according to a potential of the second node of the (n-1)-th-stage gate driver circuit and the corresponding first clock signal.
2. The gate driver unit according to claim 1, wherein the first node control module of an n-th-stage gate driver circuit of the plurality of gate driver circuits is electrically connected to the second node of an (n-1)-th-stage gate driver circuit of the plurality of gate driver circuits, and the first node control module of the n-th-stage gate driver circuit is configured to transmit the first power supply signal or a fourth power supply signal to the first node according to a potential of the second node of the (n-1)-th-stage gate driver circuit and the corresponding first clock signal.
3. The gate driver unit according to claim 2, wherein the first node control module comprises: a first transistor, an input terminal of the first transistor being configured to receive the first power supply signal; a second transistor, a first control terminal and a second control terminal of the second transistor being electrically connected to a control terminal of the first transistor, an input terminal of the second transistor being configured to receive the fourth power supply signal, and an output terminal of the second transistor being electrically connected to the output terminal of the first transistor; and a third transistor, a control terminal of the third transistor being configured to receive the corresponding first clock signal, an input terminal of the third transistor being electrically connected to the output terminal of the first transistor, and an output terminal of the third transistor being electrically connected to the first node; and wherein the control terminal of the first transistor of the n-th-stage gate driver circuit is electrically connected to the second node of the (n-1)-th-stage gate driver circuit.
3. The gate driver unit according to claim 2, wherein the first node control module comprises: a first transistor, an input terminal of the first transistor being configured to receive the first power supply signal; a second transistor, a first control terminal and a second control terminal of the second transistor being electrically connected to a control terminal of the first transistor, an input terminal of the second transistor being configured to receive the fourth power supply signal, and an output terminal of the second transistor being electrically connected to the output terminal of the first transistor; and a third transistor, a control terminal of the third transistor being configured to receive the corresponding first clock signal, an input terminal of the third transistor being electrically connected to the output terminal of the first transistor, and an output terminal of the third transistor being electrically connected to the first node; and wherein the control terminal of the first transistor of the n-th-stage gate driver circuit is electrically connected to the second node of the (n-1)-th-stage gate driver circuit.
4. The gate driver unit according to claim 1, wherein the output control module comprises: a fourth transistor, an input terminal of the fourth transistor being electrically connected to the first node; a fifth transistor, an input terminal of the fifth transistor being electrically connected to an output terminal of the fourth transistor, and an output terminal of the fifth transistor being electrically connected to the third node of the gate driver circuit at the present stage; and a first capacitor, a first terminal of the first capacitor being electrically connected to a control terminal of the fourth transistor, and a second terminal of the first capacitor being electrically connected to the output terminal of the fourth transistor; and wherein at least one of the control terminal of the fourth transistor and a control terminal of the fifth transistor is electrically connected to the second node of the gate driver circuit at the preceding stage.
4. The gate driver unit according to claim 1, wherein the output control module comprises: a fourth transistor, an input terminal of the fourth transistor being electrically connected to the first node; a fifth transistor, an input terminal of the fifth transistor being electrically connected to an output terminal of the fourth transistor, and an output terminal of the fifth transistor being electrically connected to the third node of the gate driver circuit at the present stage; and a first capacitor, a first terminal of the first capacitor being electrically connected to a control terminal of the fourth transistor, and a second terminal of the first capacitor being electrically connected to the output terminal of the fourth transistor; and wherein at least one of the control terminal of the fourth transistor and a control terminal of the fifth transistor is electrically connected to the second node of the gate driver circuit at the preceding stage.
5. The gate driver unit according to claim 4, wherein a control terminal of the fourth transistor of the n-th-stage gate driver circuit is electrically connected to the second node of an (n-10)-th-stage gate driver circuit of the plurality of gate driver circuits.
5. The gate driver unit according to claim 4, wherein a control terminal of the fourth transistor of the n-th-stage gate driver circuit is electrically connected to the second node of an (n-10)-th-stage gate driver circuit of the plurality of gate driver circuits.
6. The gate driver unit according to claim 4, wherein a control terminal of the fifth transistor of the n-th-stage gate driver circuit is electrically connected to the second 2 node of an (n-2)-th-stage gate driver circuit of the plurality of gate driver circuits.
6. The gate driver unit according to claim 4, wherein a control terminal of the fifth transistor of the n-th-stage gate driver circuit is electrically connected to the second node of an (n-2)-th-stage gate driver circuit of the plurality of gate driver circuits.
7. The gate driver unit according to claim 1, wherein the at least one of the gate driver circuits each further comprises: a first output module electrically connected to the first node of the gate driver circuit at the present stage and a first output terminal of the gate driver circuit at the present stage, and configured to output the second power supply signal or a third power supply signal to the first output terminal according to a potential of the first node; wherein the first output module comprises: a first output transistor, a control terminal of the first output transistor being electrically connected to the first node of the gate driver circuit at the present stage, an input terminal of the first output transistor being configured to receive the second power supply signal; and a second output transistor, a control terminal of the second output transistor being electrically connected to the first node of the gate driver circuit at the present stage, an input terminal of the second output transistor being configured to receive the third power supply signal, and an output terminal of the second output transistor and an output terminal of the first output transistor being electrically connected to the first output terminal of the gate driver circuit at the present stage; wherein a channel width of the first output transistor is different from a channel width of the second output transistor.
7. The gate driver unit according to claim 1, wherein the first output module comprises: a first output transistor, a control terminal of the first output transistor being electrically connected to the first node of the gate driver circuit at the present stage, an input terminal of the first output transistor being configured to receive the second power supply signal; and a second output transistor, a control terminal of the second output transistor being electrically connected to the first node of the gate driver circuit at the present stage, an input terminal of the second output transistor being configured to receive the third power supply signal, and an output terminal of the second output transistor and an output terminal of the first output transistor being electrically connected to the first output terminal of the gate driver circuit at the present stage.
8. The gate driver unit according to claim 7, wherein the input terminal of the first output transistor of the gate driver circuit at a stage of an odd number is electrically connected to a first sub-power supply line for transmitting the second power supply signal, and the input terminal of the second output transistor of the gate driver circuit at the stage of the odd number is electrically connected to a second sub-power supply line for transmitting the third power supply signal; the input terminal of the first output transistor of the gate driver circuit of a stage of an even number is electrically connected to a third sub-power supply line for transmitting the second power supply signal, and the input terminal of the second output transistor of the gate driver circuit of the stage of the even number is electrically connected to a fourth sub-power supply line for transmitting the third power supply signal.
8. The gate driver unit according to claim 7, wherein the input terminal of the first output transistor of the gate driver circuit at a stage of an odd number is electrically connected to a first sub-power supply line for transmitting the second power supply signal, and the input terminal of the second output transistor of the gate driver circuit at the stage of the odd number is electrically connected to a second sub-power supply line for transmitting the third power supply signal; the input terminal of the first output transistor of the gate driver circuit of a stage of an even number is electrically connected to a third sub-power supply line for transmitting the second power supply signal, and the input terminal of the second output transistor of the gate driver circuit of the stage of the even number is electrically connected to a fourth sub-power supply line for transmitting the third power supply signal.
9. The gate driver unit according to claim 7, wherein the input terminal of the first output transistor of a (1+3m)-th-stage gate driver circuit is electrically connected to a first sub-power supply line for transmitting the second power supply signal, and the input terminal of the second output transistor of the (1+3m)-th-stage gate driver circuit is electrically connected to a second sub-power supply line for transmitting the third power supply signal; wherein m>0;the input terminal of the first output transistor of a (2+3m)-th-stage gate driver circuit is electrically connected to a third sub-power supply line for transmitting the second power supply signal, and the input terminal of the second output transistor of the (2+3m)-th-stage gate driver circuit is electrically connected to a fourth sub-power supply line for transmitting the third power supply signal; and the input terminal of the first output transistor of a (3+3m)-th-stage gate driver circuit is electrically connected to a fifth sub-power supply line for transmitting the second power supply signal, and the input terminal of the second output transistor of the (3+3m)-th-stage gate driver circuit is electrically connected to a sixth sub-power supply line for transmitting the third power supply signal.
9. The gate driver unit according to claim 7, wherein the input terminal of the first output transistor of a (1+3m)-th-stage gate driver circuit is electrically connected to a first sub-power supply line for transmitting the second power supply signal, and the input terminal of the second output transistor of the (1+3m)-th-stage gate driver circuit is electrically connected to a second sub-power supply line for transmitting the third power supply signal; wherein m≥0; the input terminal of the first output transistor of a (2+3m)-th-stage gate driver circuit is electrically connected to a third sub-power supply line for transmitting the second power supply signal, and the input terminal of the second output transistor of the (2+3m)-th-stage gate driver circuit is electrically connected to a fourth sub-power supply line for transmitting the third power supply signal; and the input terminal of the first output transistor of a (3+3m)-th-stage gate driver circuit is electrically connected to a fifth sub-power supply line for transmitting the second power supply signal, and the input terminal of the second output transistor of the (3+3m)-th-stage gate driver circuit is electrically connected to a sixth sub-power supply line for transmitting the third power supply signal.
10. The gate driver unit according to claim 8, wherein the first sub-power supply line and the third sub-power supply line are electrically connected to a first power supply bus; and wherein a square resistance of the first power supply bus is smaller than a square resistance of the first sub-power supply line, and the square resistance of the first power supply bus is smaller than a square resistance of the third sub-power supply line.
10. The gate driver unit according to claim 8, wherein the first sub-power supply line and the third sub-power supply line are electrically connected to a first power supply bus; and wherein a square resistance of the first power supply bus is smaller than a square resistance of the first sub-power supply line, and the square resistance of the first power supply bus is smaller than a square resistance of the third sub-power supply line.
11. The gate driver unit according to claim 8, wherein the second sub-power supply line and the fourth sub-power supply line are electrically connected to a second power supply bus; and wherein a square resistance of the second power supply bus is smaller than a square resistance of the second sub-power supply line, and the square resistance of the second power supply bus is smaller than a square resistance of the fourth sub-power supply line.
11. The gate driver unit according to claim 8, wherein the second sub-power supply line and the fourth sub-power supply line are electrically connected to a second power supply bus; and wherein a square resistance of the second power supply bus is smaller than a square resistance of the second sub-power supply line, and the square resistance of the second power supply bus is smaller than a square resistance of the fourth sub-power supply line.
12. The gate driver unit of claim 7, wherein the channel width of the first output transistor is less than 288 microns and the channel width of the second output transistor 4 has is less than 186 microns.
12. The gate driver unit of claim 7, wherein a channel width of the first output transistor is less than 288 microns and a channel width of the second output transistor has is less than 186 microns.
13. The gate driver unit of claim 3, wherein a channel width of the first transistor is greater than 4.95 microns.
13. The gate driver unit of claim 3, wherein a channel width of the first transistor is greater than 4.95 microns.
14. The gate driver unit according to claim 1, wherein the first node control module comprises a sixth transistor, a seventh transistor, and an eighth transistor; a first control terminal and a second control terminal of the sixth transistor are configured to receive the corresponding first clock signal, and an input terminal of the sixth transistor is electrically connected to the first node; a control terminal of the seventh transistor is electrically connected to the second node of the gate driver circuit at the present stage, an input terminal of the seventh transistor is configured to receive the first power supply signal, and an output terminal of the seventh transistor is electrically connected to an output tenninal of the sixth transistor; a control terminal of the eighth transistor is electrically connected to the second node of the gate driver circuit at the present stage, an input terminal of the eighth transistor is configured to receive the second power supply signal, and an output terminal of the eighth transistor is electrically connected to the first node of the gate driver circuit at the present stage;the second output module comprises a third output transistor, a fourth output transistor and a second capacitor, a control terminal of the third output transistor is electrically connected to the third node of the gate driver circuit at the present stage, and an input terminal of the third output transistor is configured to receive the corresponding second clock signal; a control terminal of the fourth output transistor is electrically connected to the second node of the gate driver circuit at the present stage, an input terminal of the fourth output transistor is configured to receive the first power supply signal, and an output terminal of the third output transistor and an output terminal of the fourth output transistor are electrically connected to the second output terminal of the gate driver circuit at the present stage; a first terminal of the second capacitor is electrically connected to the control tenninal of the third output transistor, and a second terminal of the second capacitor is electrically connected to the output terminal of the third output transistor; andthe at least one of the gate driver circuits each further comprises a second node control module, the second node control module comprises a ninth transistor and a tenth 5 transistor, a control terminal of the ninth transistor is electrically connected to the first node of the gate driver circuit at the present stage, an input terminal of the ninth transistor is configured to receive the first power supply signal, and an output terminal of the ninth transistoris electrically connected to the second node of the gate driver circuit at the present stage; a control terminal of the tenth transistor is electrically connected to the first node of the gate driver circuit at the present stage, an input terminal of the tenth transistor is configured to receive a fourth power supply signal,and an output terminal of the tenth transistor is electrically connected to the second node of the gate driver circuit at the present stage.
14. The gate driver unit according to claim 1, wherein the first node control module comprises a sixth transistor, a seventh transistor, and an eighth transistor; a first control terminal and a second control terminal of the sixth transistor are configured to receive the corresponding first clock signal, and an input terminal of the sixth transistor is electrically connected to the first node; a control terminal of the seventh transistor is electrically connected to the second node of the gate driver circuit at the present stage, an input terminal of the seventh transistor is configured to receive the first power supply signal, and an output terminal of the seventh transistor is electrically connected to an output terminal of the sixth transistor; a control terminal of the eighth transistor is electrically connected to the second node of the gate driver circuit at the present stage, an input terminal of the eighth transistor is configured to receive the second power supply signal, and an output terminal of the eighth transistor is electrically connected to the first node of the gate driver circuit at the present stage; the second output module comprises a third output transistor, a fourth output transistor and a second capacitor, a control terminal of the third output transistor is electrically connected to the third node of the gate driver circuit at the present stage, and an input terminal of the third output transistor is configured to receive the corresponding second clock signal; a control terminal of the fourth output transistor is electrically connected to the second node of the gate driver circuit at the present stage, an input terminal of the fourth output transistor is configured to receive the first power supply signal, and an output terminal of the third output transistor and an output terminal of the fourth output transistor are electrically connected to the second output terminal of the gate driver circuit at the present stage; a first terminal of the second capacitor is electrically connected to the control terminal of the third output transistor, and a second terminal of the second capacitor is electrically connected to the output terminal of the third output transistor; and the at least one of the gate driver circuits each further comprises a second node control module, the second node control module comprises a ninth transistor and a tenth transistor, a control terminal of the ninth transistor is electrically connected to the first node of the gate driver circuit at the present stage, an input terminal of the ninth transistor is configured to receive the first power supply signal, and an output terminal of the ninth transistor is electrically connected to the second node of the gate driver circuit at the present stage; a control terminal of the tenth transistor is electrically connected to the first node of the gate driver circuit at the present stage, an input terminal of the tenth transistor is configured to receive a fourth power supply signal, and an output terminal of the tenth transistor is electrically connected to the second node of the gate driver circuit at the present stage.
15. A display panel, comprising: a gate driver unit comprising a plurality of gate driver circuits, at least one of the gate driver circuits each comprising a first node control module, an output control module, and a second output module; wherein the first node control module is electrically connected to a first node of the gate driver circuit at a present stage and a second node of the gate driver circuit at the present stage, and the first node control module isconfigured to transmit a first power supply signal to the first node according to a potential of the second node and a corresponding first clocksignal,or transmit a second power supply signal to the first node according to the potential of the second node; the output control module is electrically connected to the first node of the gate driver circuit at the present stage and to a third node of the gate driver circuit at the present stage, and the output control module is configured to electrically connect the first node and the third node or to disconnect an electrical connection between the first node and the third node; the second output module is electrically connected to the second node, the third node, and a second output terminal of the gate driver circuit at the present stage, the second output module is configured to output a corresponding second clock signal or the first power supply signal to the second output terminal according to the potential of the second node and a potential of the third node, and wherein at least one of the first node control module and the output controlmodule is electrically connected to the second node of the gate driver circuit at a preceding stage; and a plurality of sub-pixels, at least one of the sub-pixels each comprising a light emitting device and a pixel driver circuit for driving the light emitting device to emit light, the pixel driver circuit comprising a driving transistor, a compensation transistor6 and a data transistor, an input terminal and an output terminal of the compensation transistor being electrically connected between a control terminal and an output terminal of the driving transistor, an input terminal of the data transistor being configured to receive a corresponding data signal, and an output terminal of the data transistor being electrically connected to the input terminal of the driving transistor; and wherein the first output terminals of the plurality of gate driver circuits are electrically connected to the control terminals of the compensation transistors of the plurality of sub-pixels, and the second output terminals of the plurality of gate driver circuits are electrically connected to the control terminals of the data transistors of the plurality of sub-pixels.
15. A display panel, comprising: a gate driver unit comprising a plurality of gate driver circuits, at least one of the gate driver circuits each comprising a first node control module, a first output module, an output control module, and a second output module; wherein the first node control module is electrically connected to a first node of the gate driver circuit at a present stage and a second node of the gate driver circuit at the present stage, and the first node control module is configured to transmit a first power supply signal to the first node according to a potential of the second node and a corresponding first clock signal, or transmit a second power supply signal to the first node according to the potential of the second node; the first output module is electrically connected to the first node of the gate driver circuit at the present stage and a first output terminal of the gate driver circuit at the present stage, and the first output module is configured to output the second power supply signal or a third power supply signal to the first output terminal according to a potential of the first node; the output control module is electrically connected to the first node of the gate driver circuit at the present stage and to a third node of the gate driver circuit at the present stage, and the output control module is configured to electrically connect the first node and the third node or to disconnect an electrical connection between the first node and the third node; the second output module is electrically connected to the second node, the third node, and a second output terminal of the gate driver circuit at the present stage, the second output module is configured to output a corresponding second clock signal or the first power supply signal to the second output terminal according to the potential of the second node and a potential of the third node, and wherein at least one of the first node control module and the output control module is electrically connected to the second node of the gate driver circuit at a preceding stage; and a plurality of sub-pixels, at least one of the sub-pixels each comprising a light emitting device and a pixel driver circuit for driving the light emitting device to emit light, the pixel driver circuit comprising a driving transistor, a compensation transistor and a data transistor, an input terminal and an output terminal of the compensation transistor being electrically connected between a control terminal and an output terminal of the driving transistor, an input terminal of the data transistor being configured to receive a corresponding data signal, and an output terminal of the data transistor being electrically connected to the input terminal of the driving transistor; and wherein the first output terminals of the plurality of gate driver circuits are electrically connected to the control terminals of the compensation transistors of the plurality of sub-pixels, and the second output terminals of the plurality of gate driver circuits are electrically connected to the control terminals of the data transistors of the plurality of sub-pixels.
16. The display panel according to claim 15, wherein the display panel comprises a display area and a non-display area located at a periphery of the display area, the non- display area comprises a fan-out area; the display panel comprises a first power connection line, a second power connection line, a first pin, and a second pin located in the fan-out area; the first power connection line is electrically connected to the first pin, and is electrically connected to the plurality of gate driver circuits through a sub-power supply line for transmitting the second power signal, and the second power connection line is electrically connected to the second pin, and is electrically connected to the plurality of gate driver circuits through a sub-power supply line for transmitting the third power signal; and wherein the plurality of sub-pixels are located in the display area, the gate driver unit is located in the non-display area, a square resistance of the first power supply connection line is less than a square resistance of the sub-power supply line for transmitting each first power supply signal, and a square resistance of the second power supply connection line is less than a square resistance of the sub-power supply line for transmitting each second power supply signal.
16. The display panel according to claim 15, wherein the display panel comprises a display area and a non-display area located at a periphery of the display area, the non-display area comprises a fan-out area; the display panel comprises a first power connection line, a second power connection line, a first pin, and a second pin located in the fan-out area; the first power connection line is electrically connected to the first pin, and is electrically connected to the plurality of gate driver circuits through a sub-power supply line for transmitting the second power signal, and the second power connection line is electrically connected to the second pin, and is electrically connected to the plurality of gate driver circuits through a sub-power supply line for transmitting the third power signal; and wherein the plurality of sub-pixels are located in the display area, the gate driver unit is located in the non-display area, a square resistance of the first power supply connection line is less than a square resistance of the sub-power supply line for transmitting each first power supply signal, and a square resistance of the second power supply connection line is less than a square resistance of the sub-power supply line for transmitting each second power supply signal.
17. The display panel according to claim 15, wherein the first node control module of an n-th-stage gate driver circuit is electrically connected to the second node of an (n- A)-th-stage gate driver circuit, and the first node control module of the n-th-stage gate driver circuit is configured to transmit the first power supply signal or a fourth power supply signal to the first node according to the potential of the second node of the (n- A)-th-stage gate driver circuit and the corresponding first clock signal;A>l.
17. The display panel according to claim 15, wherein the first node control module of an n-th-stage gate driver circuit is electrically connected to the second node of an (n-A)-th-stage gate driver circuit, and the first node control module of the n-th-stage gate driver circuit is configured to transmit the first power supply signal or a fourth power supply signal to the first node according to the potential of the second node of the (n-A)-th-stage gate driver circuit and the corresponding first clock signal; A≥1.
18. The display panel of claim 17, wherein the first node control module comprises: a first transistor, an input terminal of which being configured to receive the first power supply signal; a second transistor, a first control terminal and a second control terminal of which being electrically connected to a control terminal of the first transistor, an input terminal of which being configured to receive the fourth power supply signal, and an output terminal of which being electrically connected to the output terminal of the first transistor; and a third transistor, a control terminal of which being configured to receive the corresponding first clock signal, an input terminal of which being electrically connected to the output terminal of the first transistor, and an output terminal of which being electrically connected to the first node; and wherein the control terminal of the first transistor of the n-th-stage gate driver circuit is electrically connected to the second node of the (n-A)-th-stage gate driver circuit.
18. The display panel of claim 17, wherein the first node control module comprises: a first transistor, an input terminal of which being configured to receive the first power supply signal; a second transistor, a first control terminal and a second control terminal of which being electrically connected to a control terminal of the first transistor, an input terminal of which being configured to receive the fourth power supply signal, and an output terminal of which being electrically connected to the output terminal of the first transistor; and a third transistor, a control terminal of which being configured to receive the corresponding first clock signal, an input terminal of which being electrically connected to the output terminal of the first transistor, and an output terminal of which being electrically connected to the first node; and wherein the control terminal of the first transistor of the n-th-stage gate driver circuit is electrically connected to the second node of the (n-A)-th-stage gate driver circuit.
19. The display panel according to claim 15, wherein the output control module comprises: a fourth transistor, an input terminal of the fourth transistor being electrically connected to the first node; a fifth transistor, an input terminal of the fifth transistor being electrically connected to an output terminal of the fourth transistor, and an output terminal of the fifth transistor being electrically connected to the third node of the gate driver circuit at the present stage; and a first capacitor, a first terminal of the first capacitor being electrically connected to a control terminal of the fourth transistor, and a second terminal of the first capacitor being electrically connected to the output terminal of the fourth transistor; and wherein a control terminal of the fifth transistor of the n-th-stage gate driver circuit is electrically connected to the second node of an (n-C)-th-stage gate driver circuit of the plurality of gate driver circuits; C>1;wherein the control terminal of the fourth transistor of the n-th-stage gate driver circuit is electrically connected to the second node of an (n-B)-th-stage gate driver 8 circuit of the plurality of gate driver circuits; C<B.
19. The display panel according to claim 15, wherein the output control module comprises: a fourth transistor, an input terminal of the fourth transistor being electrically connected to the first node; a fifth transistor, an input terminal of the fifth transistor being electrically connected to an output terminal of the fourth transistor, and an output terminal of the fifth transistor being electrically connected to the third node of the gate driver circuit at the present stage; and a first capacitor, a first terminal of the first capacitor being electrically connected to a control terminal of the fourth transistor, and a second terminal of the first capacitor being electrically connected to the output terminal of the fourth transistor; and wherein a control terminal of the fifth transistor of the n-th-stage gate driver circuit is electrically connected to the second node of an (n-C)-th-stage gate driver circuit of the plurality of gate driver circuits; C≥1.
20. The display panel according to claim 15, wherein the at least one of the gate driver circuits each further comprises: a first output module electrically connected to the first node of the gate driver circuit at the present stage and a first output terminal of the gate driver circuit at the present stage, and configured to output the second power supply signal or a third power supply signal to the first output terminal according to a potential of the first node; wherein the at least one of the gate driver circuits each further comprises: a first output module electrically connected to the first node of the gate driver circuit at the present stage and a first output terminal of the gate driver circuit at the present stage, and configured to output the second power supply signal or a third power supply signal to the first output terminal according to a potential of the first node; wherein the first output module comprises: a first output transistor, a control terminal of the first output transistor being electrically connected to the first node of the gate driver circuit at the present stage, an input terminal of the first output transistor being configured to receive the second power supply signal; and a second output transistor, a control terminal of the second output transistor being electrically connected to the first node of the gate driver circuit at the present stage, an input terminal of the second output transistor being configured to receive the third power supply signal, and an output terminal of the second output transistor and an output terminal of the first output transistor being electrically connected to the first output terminal of the gate driver circuit at the present stage; wherein a channel width of the first output transistor is different from a channel width of the second output transistor.
1. A gate driver unit comprising a plurality of gate driver circuits, at least one of the gate driver circuits each comprising: a first node control module electrically connected to a first node of the gate driver circuit at a present stage and a second node of the gate driver circuit at the present stage, and configured to transmit a first power supply signal to the first node according to a potential of the second node and a corresponding first clock signal, or transmit a second power supply signal to the first node according to the potential of the second node; a first output module electrically connected to the first node of the gate driver circuit at the present stage and a first output terminal of the gate driver circuit at the present stage, and configured to output the second power supply signal or a third power supply signal to the first output terminal according to a potential of the first node; an output control module electrically connected to the first node of the gate driver circuit and a third node of the gate driver circuit at the present stage, and configured to electrically connect the first node and the third node, or to disconnect an electrical connection between the first node and the third node; and a second output module electrically connected to the second node, the third node, and a second output terminal of the gate driver circuit at the present stage, and configured to output a corresponding second clock signal or the first power supply signal to the second output terminal according to the potential of the second node and a potential of the third node; and wherein at least one of the first node control module and the output control module is electrically connected to the second node of the gate driver circuit at a preceding stage.
12. The gate driver unit of claim 7, wherein a channel width of the first output transistor is less than 288 microns and a channel width of the second output transistor has is less than 186 microns.
Claims 1-20 are allowable over the prior art of record. The rejection(s) under the obvious double patenting rejection, set forth in this Office action, would need to be overcome.
Conclusion
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INSA . SADIO
Primary Examiner
Art Unit 2628
/INSA SADIO/Primary Examiner, Art Unit 2628