DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1, 7, 13 is/are rejected under 35 U.S.C. 103 as being unpatentable over MAGNAVACCA (US 20230376230 A1), in view of Son (US 20250244884 A1) and IE (KR 20230036038 A)
Regarding Claim 1, MAGNAVACCA teaches:
A data storage device comprising: a memory device including a plurality of memory blocks; (MAGNAVACCA, abstract, A memory device may include a plurality of non-volatile memory devices and a controller. The controller may be configured to generate first parity data for a portion of a data block stored in a plurality of memory blocks of the plurality of non-volatile memory devices)
and a controller configured to control the memory device, (MAGNAVACCA, abstract, A memory device may include a plurality of non-volatile memory devices and a controller.)
wherein the controller divides a block group including the memory blocks into a set number of sub-groups, (MAGNAVACCA,[0043] As shown in FIG. 3, the redundant array 280 includes the non-volatile memory devices 210a-210n. Each of the non-volatile memory devices 210a-210n includes a plurality of data planes....[0044] A data plane may be grouped into logic units that are assigned to respective logical unit numbers (LUNs). For some types of non-volatile memory devices (e.g., NAND devices), each plane may include of a set of memory blocks 310 (e.g., physical non-volatile memory blocks). )
the sub-groups including first and second sub-groups, (MAGNAVACCA, Fig. 3, Plane 1, Plane 2… Plane z)
each of the sub-groups including a plurality of pages, (MAGNAVACCA, [0044], Each memory block 310 may include a set of pages.)
MAGNAVACCA doesn’t explicitly teach:
and wherein the controller generates first recovery data programed on a page basis to correspond to data programmed in the first sub- group on the page basis,
However, MAGNAVACCA does teach:
(MAGNAVACCA, Fig. 7, 720, abstract, The controller may be configured to generate first parity data for a portion of a data block stored in a plurality of memory blocks of the plurality of non-volatile memory devices. )
And Son does teach:
(Son, [0148] As a first example, when the recovery data is mirrored data, the unit data may be an amount of data that can be programmed into one physical page of the second sub-block in a second level cell mode. ) Examiner’s note: this shows the recovery data is generated on the page basis.
Therefore, it would have been obvious before the effective filing date of the claimed invention to one of ordinary skill in the art to which said subject matter pertains to combine MAGNAVACCA with page basis recovery data generation as taught by Son, because when the first level cell mode is an SLC mode and the second level cell mode is a TLC mode, and a parity operation is performed on six data chunks to generate one parity data chunk, the data may be an amount of data that can be programmed in eighteen (18) physical pages of the first sub-block. (Son, [0148])
MAGNAVACCA in view of Son further teaches:
generates second recovery data programed on a sub-group basis for the first sub-group when programming of the first sub-group is complete, (MAGNAVACCA, Fig. 7, 750, Generate respective cumulative parity data for a plurality of groups of page lines of the data block)
MAGNAVACCA in view of Son does not explicitly teach:
and invalidates the second recovery data for the first sub-group when programming of the second sub-group is complete, the second sub-group being programmed after the programming of the first sub-group is complete.
However, IE teaches:
and invalidates the second recovery data for the first sub-group when programming of the second sub-group is complete, the second sub-group being programmed after the programming of the first sub-group is complete. (IE, Fig. 8B section in spec, Referring to FIG. 8B , in a subsequent situation ( S22 ), the controller 120 stores data after all first sub areas SB1 included in the first number of memory blocks MB1 to MBx are stored. , the second type of data D2 may be stored in the second sub areas SB2 of the memory blocks MB1 to MBx. When all the second sub areas SB2 of the memory blocks MB1 to MBx store data, the parity data PD stored in the parity memory block PMB does not need to be maintained any longer and can be erased.)
Therefore, it would have been obvious before the effective filing date of the claimed invention to one of ordinary skill in the art to which said subject matter pertains to combine MAGNAVACCA in view of Son with erase parity after data is stored in second sub area as taught by IE, because the parity data PD stored in the parity memory block PMB does not need to be maintained any longer (IE, Fig. 8B section in spec)
Regarding claim 7,
The data storage device of claim 7 performs the same method steps as the methods of claim 1, and claim 7 is therefore rejected using the same rationale set forth above in the rejection of claim 1
Regarding claim 13,
The method of claim 13 performs the same method steps as the methods of claim 1, and claim 13 is therefore rejected using the same rationale set forth above in the rejection of claim 1
Allowable Subject Matter
Claims 2-6, 8-12, 14-18 objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
SINGIDI (CN 113168358 A): Various applications may include devices and/or methods for providing parity protection to data spread over a plurality of memory devices of a memory system. The parity check is stored in a buffer, wherein the parity is generated from a portion of the data written to the page, the page has a different portion of the page in a portion of each plane of one or more planes of the plurality of memory devices. For each page, the parity check is stored in the buffer. In response to determining that a transmission criterion is satisfied, the parity data in the buffer is transmitted from the buffer to a temporary block. After programming the data into the block to close the block, the verification of the block is performed with respect to the data error. In response to passing through the verification, the temporary block can be released for the next data writing operation. The invention claims an additional device, system and method.
Tang (US 10169142 B2): A method is performed by a solid state device (SSD) controller to generate a parity. The method includes receiving input data to be stored to pages of a storage device, wherein each page is capable of being allocated with multiple codewords; configuring codewords of the pages into multiple groups, wherein each group has an integer number of codewords, at least one of the pages is allocated with a non-integer number of codewords, and wherein the integer number is larger than the non-integer number; obtaining parities for the multiple groups, and storing the parities to reserved spaces of the storage device. With the calculation of a parity decoupled from physical pages, the selection of a rate of code used is unconstrained by an integer number of codewords per page.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to XINYUAN YU whose telephone number is (571)272-7140. The examiner can normally be reached Monday-Friday 8:30-5:30.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Bryce Bonzo can be reached at 571-272-3655. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/XINYUAN YU/Examiner, Art Unit 2113 /BRYCE P BONZO/Supervisory Patent Examiner, Art Unit 2113
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