The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
Current Status of Claims
This action is a response to communication of May 27, 2026. By amendment of May 27, 2026 the Applicant amended claims 1, 14-15, and 17. Therefore, claims 1 to 20 remain active in the application.
Response to Amendment
Applicant’s arguments with respect to claim(s) 1-20 have been considered but are moot because the new ground of rejection does not rely on at least some of the references applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Drawings
The drawings are objected to under 37 CFR 1.83(a). The drawings must show every feature of the invention specified in the claims. Therefore, the “the PCB comprises a plurality of layers including: a first layer that includes a first signal line forming at least a portion of the second path, a second layer disposed below the first layer, and a third layer disposed above the first layer, and wherein at least a portion of the second layer and at least a portion of the third layer are grounded so as to electrically shield the second path” (emphasis added by examiner) must be shown or the feature(s) canceled from the claim(s). No new matter should be entered.
Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. The figure or figure number of an amended drawing should not be labeled as “amended.” If a drawing figure is to be canceled, the appropriate figure must be removed from the replacement sheet, and where necessary, the remaining figures must be renumbered and appropriate changes made to the brief description of the several views of the drawings for consistency. Additional replacement sheets may be necessary to show the renumbering of the remaining figures. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 1-20 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as failing to set forth the subject matter which the inventor or a joint inventor, or for applications subject to pre-AIA 35 U.S.C. 112, the applicant regards as the invention. Specifically, limitation to claim 1 introduced by amendment of May 27, 2026, “the PCB comprises a plurality of layers including: a first layer that includes a first signal line forming at least a portion of the second path, a second layer disposed below the first layer, and a third layer disposed above the first layer, and wherein at least a portion of the second layer and at least a portion of the third layer are grounded so as to electrically shield the second path” is not clearly illustrated and not supported by the original disclosure. In the Remarks the Applicant did not provide the reference to the original disclosure supporting the limitations introduced by amendment May 27, 2026. Accordingly, the correction of claim language is respectfully requested.
Allowable Subject Matter
Claims 2-11 and 16-20 were previously objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. No prior art of the record shows the limitation “a regulator including a terminal connected to an input node of the another circuit; and a fifth pad connected to another terminal of the regulator, wherein the PMIC further includes another power supply circuit and a sixth pad connected to the another power supply circuit wherein the PMIC is further configured to provide a third DC signal to the regulator via a third path between the fifth pad and the sixth pad, using the another power supply circuit, wherein the third DC signal is converted to a fourth DC signal via the regulator, and wherein the fourth DC signal is provided from the regulator to the another circuit.”
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1, 12, 13, 14, 15 is/are rejected under 35 U.S.C. 103 to the best examiner’s understanding as being unpatentable over Jang et al. (US Patent Publication Application 2022/0068180 A1) in view of Kikuchi (US Patent 5,506,37).
In regard of claim 1, Jang et al. disclose an electronic device comprising: at least one processor comprising processing circuitry; a display including a display panel and display driver circuitry (See Figure 1 of Jang et al. illustrating a display (100) including processor (150) and display driver circuit (130a, 130m) as discussed in paragraphs [0028-0030] of Jang et al.), the display driver circuitry including: at least one circuit configured to process an image obtained from the at least one processor for displaying via the display panel (See Figure 1 of Jang et al. illustrating the display driver circuitry (130a-130m) including image process circuit from (150) as discussed in paragraph [0030] of Jang et al.), a first pad connected to an of the at least one circuit, and a second pad connected to the input node, wherein the display further includes a capacitor connected to the input node via the first pad (See Figures 5 and 7 of Jang et al. illustrating a first pad connecting a first voltage generating module (510) to input to the display driver (130) and capacitor (Co) as discussed in paragraphs [0078-0080]); and power management integrated circuitry (PMIC, 120c ) including a third pad, a fourth pad, and a power supply circuit respectively connected to the third pad and the fourth pad, wherein the PMIC is configured to: provide a first direct current (DC) signal to the at least one circuit via a first path between the first pad and the third pad, using the power supply circuit; identify a voltage value of the first DC signal at the input node via a second path between the second pad and the fourth pad, using the power supply circuit (See paragraph [0061] of Jang et al. discussing integration of the power management circuit comprising circuits illustrated in Figures 5 to 8 of Jang et al. providing a first DC signal (Vo1) to the circuit (530) as discussed in paragraphs [0065-0066]); and provide a second DC signal obtained based on the voltage value to the at least one circuit via the first path, using the power supply circuit (See Figures 5 to 8 of Jang et al. illustrating second DC signal (Vo2) obtained based on the voltage value of circuit (530) as discussed in paragraphs [0066-0069] of Jang et al.).
However, the reference to Jang et al. does not specifically disclose the electronic device, wherein the PCB comprises a plurality of layers including: a first layer that includes a first signal line forming at least a portion of the second path, a second layer disposed below the first layer, and a third layer disposed above the first layer, and wherein at least a portion of the second layer and at least a portion of the third layer are grounded so as to electrically shield the second path.
In the same field of endeavor, Kikuchi discloses in Figure 2 the printed circuit board with a first layer (13) that includes a first signal line (19) forming at least a portion of the second path and second layer (15) disposed below the first layer (13) and third layer (14) disposed above the first layer (13) and grounded (17) to electrically shield the second path (18) as discussed in paragraphs starting in column 5, lines 14-67 and in column 6, lines 48-51 of Kikuchi.
Therefore, it would be obvious for a person skilled in the art before the effective filing date of the claimed invention to use multi-layered PCB of Kikuchi with the device of Jang et al. in order to reduce electromagnetic wave noise produced by signal lines and second path by sandwiching the signal lines with solid-patch grounds for shielding.
In regard of claim 12, Jang et al. and Kikuchi further disclose the electronic device of claim 1, wherein the display driver circuitry further includes another circuit configured to at least temporarily store the image provided from the at least one processor and a fifth pad connected to an input node of the another circuit, and wherein the PMIC is further configured to provide the second DC signal to the another circuit via a third path between the third pad and the fifth pad, using the power supply circuit (See Figures 1 and 5 of Jang et al. illustrating the power management device (120a) and the display driver circuitry (130) configured to store the image (RGB) provided from processor (150) and provide the second DC signal (Vo2) using the power supply circuit (120)) .
In regard of claim 13, Jang et al. and Kikuchi further disclose the electronic device of claim 12, wherein the display further includes another capacitor connected to the input node of another circuit via the fifth pad (See Figure 2 of Jang et al. illustrating the part of the display including another capacitor (SE) connected to the input node (SL) as discussed in paragraphs [0032-0033] of Jan et al.).
In regard of claim 14, Jang et al. and Kikuchi further disclose the electronic device of claim 1, further comprising: a connector, attached to the PCB, including a first pin connected to the first pad for the first path and a second pin connected to the second pad for the second path (See at least paragraph [0035] of Jang et al. discussing usage of a flexible printed circuit board and connectors to connect to the second path (Vo2)).
In regard of claim 15, Jang et al. and Kikuchi further disclose the electronic device of claim 14, wherein signal lines comprise a second signal line between the first pad and the first pin and the first signal line between the second pad and the second pin, wherein the first signal line is electrically separated from at least one signal lines different from the first signal line from among the signal lines, and wherein the second signal line is electrically separated from at least one signal lines different from the second signal line from among the signal lines (See Figures 1 and 5 of Jang et al. illustrating plurality of signal lines (DL) electrically separated from each other).
Conclusion
THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Contact Information
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Olga Aronovich whose telephone number is (571)270-7796. The examiner can normally be reached on Mon-Fri. from 7:30-5:00.
If attempts to reach the examiner by telephone are unsuccessful, the examiner's Supervisor, Benjamin C. Lee can be reached on (571) 272-2963. The fax phone number for the organization where this application or proceeding is assigned is 703-872-9306. Information regarding the status of an application may be obtained from the Patent Application Information Retrieval (PAIR) system. Status information for published applications may be obtained from either Private PAIR or Public PAIR. Status information for unpublished applications is available through Private PAIR only. For more information about the PAIR system, see http://pair-direct.uspto.gov. Should you have questions on access to the Private PAIR system, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free).
/OLGA V MERKOULOVA/Primary Examiner, Art Unit 2629
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