The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
Current Status of Claims
This action is a response to communication of May 1, 2025. Therefore, claims 1 to 20 are currently active in the application.
Priority
Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55.
Information Disclosure Statement
The information disclosure statement (IDS) submitted on May 1, 2025 was filed before a mailing date of the first action on merits. The submission is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Allowable Subject Matter
Claims 2-11 and 16-20 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. No prior art of the record shows the limitation “a regulator including a terminal connected to an input node of the another circuit; and a fifth pad connected to another terminal of the regulator, wherein the PMIC further includes another power supply circuit and a sixth pad connected to the another power supply circuit wherein the PMIC is further configured to provide a third DC signal to the regulator via a third path between the fifth pad and the sixth pad, using the another power supply circuit, wherein the third DC signal is converted to a fourth DC signal via the regulator, and wherein the fourth DC signal is provided from the regulator to the another circuit.”
Claim Rejections - 35 USC § 102
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim(s) 1, 12, 13, 14, 15 is/are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Jang et al. (US Patent Publication Application 2022/0068180 A1).
In regard of claim 1, Jang et al. disclose an electronic device comprising: at least one processor comprising processing circuitry; a display including a display panel and display driver circuitry (See Figure 1 of Jang et al. illustrating a display (100) including processor (150) and display driver circuit (130a, 130m) as discussed in paragraphs [0028-0030] of Jang et al.), the display driver circuitry including: at least one circuit configured to process an image obtained from the at least one processor for displaying via the display panel (See Figure 1 of Jang et al. illustrating the display driver circuitry (130a-130m) including image process circuit from (150) as discussed in paragraph [0030] of Jang et al.), a first pad connected to an of the at least one circuit, and a second pad connected to the input node, wherein the display further includes a capacitor connected to the input node via the first pad (See Figures 5 and 7 of Jang et al. illustrating a first pad connecting a first voltage generating module (510) to input to the display driver (130) and capacitor (Co) as discussed in paragraphs [0078-0080]); and power management integrated circuitry (PMIC, 120c ) including a third pad, a fourth pad, and a power supply circuit respectively connected to the third pad and the fourth pad, wherein the PMIC is configured to: provide a first direct current (DC) signal to the at least one circuit via a first path between the first pad and the third pad, using the power supply circuit; identify a voltage value of the first DC signal at the input node via a second path between the second pad and the fourth pad, using the power supply circuit (See paragraph [0061] of Jang et al. discussing integration of the power management circuit comprising circuits illustrated in Figures 5 to 8 of Jang et al. providing a first DC signal (Vo1) to the circuit (530) as discussed in paragraphs [0065-0066]); and provide a second DC signal obtained based on the voltage value to the at least one circuit via the first path, using the power supply circuit (See Figures 5 to 8 of Jang et al. illustrating second DC signal (Vo2) obtained based on the voltage value of circuit (530) as discussed in paragraphs [0066-0069] of Jang et al.) .
In regard of claim 12, Jang et al. further discloses the electronic device of claim 1, wherein the display driver circuitry further includes another circuit configured to at least temporarily store the image provided from the at least one processor and a fifth pad connected to an input node of the another circuit, and wherein the PMIC is further configured to provide the second DC signal to the another circuit via a third path between the third pad and the fifth pad, using the power supply circuit (See Figures 1 and 5 of Jang et al. illustrating the power management device (120a) and the display driver circuitry (130) configured to store the image (RGB) provided from processor (150) and provide the second DC signal (Vo2) using the power supply circuit (120)) .
In regard of claim 13, Jang et al. further discloses the electronic device of claim 12, wherein the display further includes another capacitor connected to the input node of another circuit via the fifth pad (See Figure 2 of Jang et al. illustrating the part of the display including another capacitor (SE) connected to the input node (SL) as discussed in paragraphs [0032-0033] of Jan et al.).
In regard of claim 14, Jang et al. further discloses the electronic device of claim 1, further comprising: a printed circuit board (PCB), and a connector, attached to the PCB, including a pin connected to the first pad for the first path and another pin connected to the second pad for the second path (See at least paragraph [0035] of Jang et al. discussing usage of a flexible printed circuit board and connectors to connect to the second path (Vo2)).
In regard of claim 15, Jang et al. further discloses the electronic device of claim 14, wherein the PCB includes a plurality of signal lines comprising a first signal line between the first pad and the pin and a second signal line between the second pad and the another pin, wherein the first signal line is electrically separated from signal lines different from the first signal line from among the plurality of signal lines, and wherein the second signal line is electrically separated from signal lines different from the second signal line from among the plurality of signal lines (See Figures 1 and 5 of Jang et al. illustrating plurality of signal lines (DL) electrically separated from each other).
Conclusion
The references found pertinent:
US Patent Publication Application 2018/0096666 to Chung et al.
US Patent Publication Application 20160343293 to Kim et al.
Contact Information
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Olga V. Merkoulova whose telephone number is ((571)270-7796. The examiner can normally be reached on Mon-Fri. from 7:30-5:00.
If attempts to reach the examiner by telephone are unsuccessful, the examiner's Supervisor, LunYi Lao can be reached on (571) 272-7671. The fax phone number for the organization where this application or proceeding is assigned is 703-872-9306. Information regarding the status of an application may be obtained from the Patent Application Information Retrieval (PAIR) system. Status information for published applications may be obtained from either Private PAIR or Public PAIR. Status information for unpublished applications is available through Private PAIR only. For more information about the PAIR system, see http://pair-direct.uspto.gov. Should you have questions on access to the Private PAIR system, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free).
/OLGA V MERKOULOVA/Primary Examiner, Art Unit 2621