DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
This is the initial Office Action based on the application filed 05/01/2025. Claims 1-20 are presented for examination and have been considered below.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claims 1–4, 6–11, 13–18 and 20 are rejected under 35 U.S.C. §103 as being unpatentable over Xinli Gu et al., Realizing High Test Quality Goals with Smart Test Resource Usage, ITC 2004 (“Gu”) in view of Abadir et al., US 2003/0079189 A1 (“Abadir”) and further in view of Xijiang Lin et al., High-Frequency, At-Speed Scan Testing, IEEE Design & Test of Computers, Sept.–Oct. 2003 (“Lin”).
Claim 1: Gu teaches a method, performed by at least one processor, of generating a test pattern, the method comprising:
obtaining design data with respect to a circuit under test (CUT) (e.g., Gu’s disclosed ATPG process operates on an ASIC design and fault lists derived for that circuit. Gu explains that the transition-fault ATPG tool targets each pin in the circuit for slow-to-fall and slow-to-rise transitions, and discusses fault lists presented to the ATPG tool. See §2.1, Delay fault models. Gu’s test-generation methodology is further expressly based on the design requirements and limitations of the device being tested. See §4, A General Test Generation Flow. Thus, the design/netlist information used by the ATPG process constitutes the claimed design data.);
generating, based on the design data, a first test pattern for detecting a transition delay (TD) fault (e.g., Gu states that transition ATPG targets a transition-fault list and generates transition tests. Section 2.1 explains that the transition-fault ATPG tool targets each circuit pin for slow-to-fall and slow-to-rise transitions observable at an observation point. In Section 4, Gu expressly identifies a transition ATPG run targeting the transition fault list F_T. Accordingly, Gu teaches generating the claimed first TD test pattern.) and a pre-detected fault list (PDFL) (e.g., Gu expressly maintains separate fault lists:
F_P: path-delay faults;
F_T: transition faults; and
F_S: stuck-at faults.
Gu further explains that faults are removed from these lists as they are detected. Specifically: “Each time a fault is detected, it will be removed from the fault lists once.” See §4. More importantly, Gu expressly defines F_{S-trans} as the stuck-at faults detected by the transition ATPG run. Gu states: “Transition ATPG run detects F_{T-trans} and F_{S-trans} faults from the transition and stuck-at fault lists, respectively.” Thus, F_{S-trans} is an expressly identified population/list of SA faults already detected before the subsequent SA ATPG operation and therefore corresponds, under BRI, to the claimed pre-detected fault list. Gu’s experimental Section 5.2 confirms the same operation: the stuck-at ATPG is performed on a fault list from which faults detected by the transition test set have already been excluded.);
generating, based on the design data and the PDFL, a second test pattern for detecting SA faults (e.g., Gu’s incremental ATPG approach targets only faults remaining after those detected by earlier ATPG runs are removed. Gu states: “The incremental ATPG run only targets the remaining faults which were not detected by other ATPG runs.” See Page 528. After transition ATPG detects F_{S-trans}, Gu defines the remaining stuck-at fault population as:
F_S-F_{S-LBIST}-F_{S-path}-F_{S-trans}
and then expressly states that the multiple-detect stuck-at ATPG targets that remaining SA population. In the embodiment relevant here, the LBIST and path portions may be omitted, leaving the operative relationship: F_S-F_{S-trans}
Thus Gu directly teaches SA ATPG based upon the SA fault population remaining after subtracting the SA faults already detected by the transition tests.);
generating first SA fault candidates with respect to a modeled circuit of the CUT, based on the design data (e.g., Gu expressly defines the initial stuck-at fault list as F_S along with the initial transition fault list F_T. See Page 528. Under BRI, F_S, the stuck-at faults presented as targets for the circuit, constitutes the claimed first SA fault candidates.);
generating second SA fault candidates, based on the PDFL and the first SA fault candidates (e.g., Gu states that transition ATPG detects F_{S-trans} from the stuck-at fault list and subsequently defines the remaining SA fault population by subtracting F_{S-trans} from F_S. Accordingly:
\text{first SA candidates}=F_S
\text{PDFL}=F_{S-trans}
and
\text{second SA candidates}=F_S-F_{S-trans}
(disregarding optional earlier LBIST/path fault detections). See Section 4 and Section 5.2); and
and wherein the generating the second test pattern comprises: generating the second test pattern based on the second SA fault candidates (e.g., Gu’s step 8 expressly states:
“Multiple-detect ATPG targets stuck-at faults \{F_S-F_{S-LBIST}-F_{S-path}-F_{S-trans}\}…”
Gu §5.2 further confirms that the stuck-at ATPG is performed for the fault list in which faults detected by the transition test sets are excluded. Thus, the second SA test pattern is generated from the second/remaining SA candidate population).
Gu fails to teach:
wherein the PDFL comprises stuck-at (SA) faults, which respectively correspond to detectable TD faults that are included in a detectable TD fault list and are detectable through a simulation.
However, Abadir, in ¶17, expressly teaches that:
detecting a slow-to-rise transition fault is equivalent to detecting a stuck-at-zero fault on the corresponding gate of the transformed circuit; and
detecting a slow-to-fall transition fault is equivalent to detecting a stuck-at-one fault on the corresponding gate.
Abadir, in ¶20, likewise expressly refers to the “corresponding Stuck-at fault” for a transition-delay fault. Abadir therefore establishes precisely the known TD-fault-to-SA-fault correspondence missing from Gu.
Furthermore, Lin expressly teaches generating transition patterns and then performing stuck-at fault simulation of those transition patterns to identify which SA faults are detected. In the example described in the section Merging at-speed patterns with stuck-at pattern, Lin states that stuck-at fault simulation of the 4,000 transition patterns resulted in 93.07% of the stuck-at faults being detected, after which only supplemental SA patterns were needed. See Page 21. Lin’s industrial case study similarly states that: “the transition fault test patterns are fault-simulated for stuck-at test coverage” and reports that 89.4% of SA faults were detected by the transition patterns. See Page 23. Accordingly, Lin expressly supplies determining the relevant fault coverage through simulation.
Therefore, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to employ Abadir’s known TD-to-SA fault correspondence and Lin’s known stuck-at fault-simulation technique within Gu’s incremental ATPG architecture for the following reasons:
Gu expressly seeks to avoid redundant ATPG by removing already-detected faults and directing subsequent ATPG only to remaining faults. Gu also expressly recognizes that transition ATPG detects SA faults, which are thereafter subtracted from the SA target list. Furthermore, Abadir teaches that transition faults conventionally have corresponding SA fault representations, particularly STR→SA0 and STF→SA1. And Lin teaches the conventional technique of fault-simulating transition patterns against the SA fault model to establish which SA faults are already detected before subsequent SA ATPG.
A POSITA therefore would have had reason to use the known TD↔SA correspondence of Abadir and the SA fault-simulation technique of Lin when implementing Gu’s F_T, F_S, and F_{S-trans} fault-list methodology, because doing so provides a known mechanism for associating transition faults with corresponding SA representations and determining their detection status so that already-covered SA targets can be removed before the subsequent SA ATPG run. The combination would predictably achieve Gu’s expressly stated objective: reducing redundant test-generation effort and test-data volume by directing each incremental ATPG run only to the remaining faults.
Claim 2: Gu, Abadir and Li teach the method of claim 1, wherein each of the SA faults included in the PDFL is based on a fault type of each of the detectable TD faults included in the detectable TD fault list being classified as an SA fault. For instance, Abadir, in ¶17, expressly teaches corresponding SA representations for the two transition-fault types. Therefore, using Abadir’s known correspondence to identify the SA representation associated with the TD fault in Gu’s separate TD and SA fault lists would have been an obvious implementation of Gu’s cross-fault-model methodology.
Claim 3: Gu, Abadir and Li teach the method of claim 2, wherein, based on the fault type of each of the detectable TD faults is a slow-to-rise (STR) fault, a fault type of the STR fault is reclassified as an SAG fault, and wherein, based on the fault type of each of the detectable TD faults being a slow-to-fall (STF) fault, a fault type of the STF fault is reclassified as an SA1 fault. For instance, Abadir, in ¶17, expressly teaches:
slow-to-rise (zero-to-one) transition fault → corresponding stuck-at-zero fault;
slow-to-fall (one-to-zero) transition fault → corresponding stuck-at-one fault.
Claim 4: Gu, Abadir and Li teach the method of claim 1, wherein the generating the second SA fault candidates includes removing SA faults included in both the first SA fault candidates and the PDFL from the first SA fault candidates. For instance, Gu teaches that each detected fault is removed from its fault list. After transition ATPG identifies F_{S-trans}, Gu’s remaining SA list expressly subtracts F_{S-trans}: F_S-F_{S-LBIST}-F_{S-path}-F_{S-trans}. See Sections 4 and 5.2.
Clam 5: Gu, Abadir and Li teach the method of claim 1, wherein the generating the second SA fault candidates includes classifying the SA faults included in the PDFL into a detectable (DT) state in the first SA fault candidates.
Claim 6: Gu, Abadir and Li teach the method of claim 1, wherein the second test pattern includes test patterns with respect to detectable SA faults among the second SA fault candidates and does not include test patterns with respect to the SA faults included in the PDFL. For instance, Gu teaches that the subsequent stuck-at ATPG targets the remaining SA faults after subtracting those already detected by the transition test set. Section 5.2 is particularly explicit: stuck-at ATPG is performed on a fault list from which faults detected by the transition test sets are excluded. Thus the second test pattern targets remaining detectable SA faults and does not target the pre-detected/F_{S-trans} SA faults.
Claim 7: Gu, Abadir and Li teach the method of claim 1, wherein the first test pattern includes test patterns capable of detecting the SA faults included in the PDFL. For instance, Gu expressly states that: “Transition ATPG run detects … F_{S-trans} faults from the … stuck-at fault list…” Gu’s experimental results also state that the transition test-vector set detected many stuck-at faults, achieving 85.38% stuck-at coverage. See Section 4.
As per claim 8, the recites essentially claim 1 in device form, with a TD ATPG module and SA ATPG module implemented by at least one processor.
The substantive limitations are taught by Gu/Abadir/Lin for the reasons discussed for claim 1.
Gu expressly describes distinct:
transition ATPG operations; and
stuck-at ATPG operations,
and its Section 4 directs the two ATPG operations to separate respective fault lists. To the extent Gu does not expressly call these software functions “modules” implemented by a processor, Abadir expressly discloses an ATPG architecture including a Multiple Phase ATPG Controller, an ATPG Tool, a fault-simulation/pattern-compression tool, and circuit-model data.
Abadir further states that its methods may be implemented using software instructions, with sets of instructions performing the respective method steps.
Therefore, Implementing Gu’s respective TD and SA ATPG functions as processor-executed functional modules therefore would have been an ordinary and predictable software implementation.
Claims 9–11, 13 and 14 substantially correspond to claims 2–4, 6 and 7 in device form respectively. Accordingly, claims 9-14 are rejected under 35 U.S.C. § 103 for substantially the same reasons set forth above with respect to the corresponding method claims.
As per claim 15, the claim adds to the test-pattern generator:
“a test device configured to test the CUT by using the test pattern.”
Gu expressly concerns generated scan test vectors that are stored/applied using a tester and repeatedly discusses allocation of tester memory and test vectors. Its Section 4 identifies the maximum number of test patterns installable on a tester as a principal constraint governing pattern generation. Gu’s experimental hardware also expressly describes external scan chains connected to a tester and test data obtained from the tester and fed into the internal scan chains. Thus Gu teaches using generated test patterns with a test device/tester to test the CUT.
The remaining limitations are taught by Gu, Abadir, and Lin for the reasons discussed for claim 1.
Claims 16-18 and 20 substantially correspond to claims 2–4, 6 and 7 in system form respectively. Accordingly, claims 16-18 and 20 are rejected under 35 U.S.C. § 103 for substantially the same reasons set forth above with respect to the corresponding method claims.
Claim(s) 5, 12 and 19 are rejected under 35 U.S.C. 103 as being unpatentable over Gu, Abadir and Li as applied to claim 1 above, and further in view of Wei Lin et al., “An on-Chip Clock Controller for Testing Fault in System on Chip” (ICCSEE 2013).
Regarding claim 5, Gu teaches generating the second SA fault candidates by identifying SA faults F_{S-trans} that are detected by the transition ATPG run from the initial stuck-at fault list F_S, and updating the stuck-at fault population based on those detected faults. In particular, Gu teaches that each detected fault is removed from the fault list, or alternatively that a fault attribute may be updated based on detection, and thereafter excludes F_{S-trans} from the remaining SA fault candidates. See Gu, §4.
Gu does not expressly teach classifying the previously detected SA faults into a detectable/detected (DT) state. However, Wei Lin teaches ATPG using both transition-delay and stuck-at fault models and expressly identifies “Detected (DT)” as a fault class/code for stuck-at faults, distinct from PT, UD, AU, and ND fault classes. See Wei Lin, §II.C and Table I.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to classify Gu’s SA faults identified as detected by the transition ATPG operation using the conventional Detected (DT) fault classification taught by Wei Lin, because doing so provides a known ATPG mechanism for representing the detection status of SA faults within the fault population and enables those previously detected faults to be distinguished from faults requiring further ATPG processing. Such use would amount to applying a known fault-status classification to Gu’s already-identified detected SA faults to obtain the predictable result of maintaining their detected status during subsequent ATPG processing.
Claim 12 and 19 are rejected under 35 U.S.C. § 103 for substantially the same reasons set forth above with respect to the corresponding method claim 5 above.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to GUERRIER MERANT whose telephone number is (571)270-1066. The examiner can normally be reached Monday-Friday 8:00 Am - 5:00 PM.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Mark Featherstone can be reached at 571-270-3750. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/GUERRIER MERANT/Primary Examiner, Art Unit 2111 9/10/2026
