Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claims 1, 4-7, 11-12, 16 and 18-20 are rejected under 35 U.S.C. 103 as being unpatentable over Zamir et al. (US 11,456,758), hereinafter Zamir, in view of Kim et al. (US 2022/0164143), hereinafter Kim.
Regarding claim 1, Zamir teaches a memory device (Zamir, Fig. 1, memory 104; col. 4, lines 46-51, “The memory 104 of the data storage device 102 may include a non-volatile memory (e.g., NAND, Bi CS family of memories, or other suitable memory). In some examples, the memory 104 may be any type of flash memory. For example, the memory 104 may be two-dimensional (2D) memory or three-dimensional (3 D) flash memory”), comprising: a memory cell array comprising a plurality of memory units (Zamir, Fig. 1, memory dies 103; col. 4, lines 51-61, “The memory 104 may include one or more memory dies 103. Each of the one or more memory dies 103 may include one or more blocks [e.g., one or more erase blocks]. Each block may include one or more groups of storage elements, such as a representative group of storage elements 107 A-107N. The group of storage elements 107 A-107N may be configured as a word line. The group of storage elements 107 may include multiple storage elements [e.g., memory cells that are referred to herein as a "string"], such as a representative storage elements 109A and 109N, respectively”; col. 6, lines 37-40, “The set of hard bits may represent a single logical page or one or more logical pages. The set of soft-bits may represent a corresponding single logical page or a corresponding one or more logical pages”; the logical pages equate to memory units); a page buffer circuit configured to acquire, using a soft read voltage, soft decision (SD) data (Zamir, Fig. 1, read/write circuitry 140 and set of latches 111, which includes latch 112, 114 & 116; col. 2, lines 8-25, col. 5, lines 2-21, and col. 8, lines 21-25 teach read/write circuitry and associated latches that are configured to acquire soft decision data by sensing soft bits using a determined soft bit delta; the read/write circuitry and associated latches equate to a page buffer circuit) comprising a plurality of SD data segments from the plurality of memory units data (Zamir, col. 6, lines 29-50 teaches soft bits representing corresponding logical pages and the logical pages are divided into fixed sized segments; the logical pages equate to memory units, and the soft-bit portions equate to the SD data segments); and a compression circuit configured to compress the SD data into compressed data (Zamir, Fig. 1, compressed soft-bit circuitry 118; col. 2, lines 21-25, “The compressed soft-bit [CSB] circuitry is further configured to receive the first set of soft-bits, generate a second set of soft-bits from the first set of soft-bits based on the determined compression scheme, and output the second set of soft-bits”; col. 8, lines 26-34, “The method 300 includes generating a second set of soft-bits from the first set of soft-bits that are sensed by the read/write circuitry 140 based on the determined compression scheme (at block 306). For example, the CSB circuitry 118 generates the second set of soft-bits from the first set of soft-bits based on the determined compression scheme. The method 300 includes outputting the second set of soft-bits (at block 308). For example, the CSB circuitry 118 outputs the second set of soft-bits to the controller 120”) comprising a plurality of compressed data segments corresponding to the plurality of SD data segments (Zamir, col. 6, lines 41-50, “The compressed soft-bit (CSB) circuitry 118 allows defined memory spaces, such as pages, to be split into smaller fixed size segments. For example, the adaptive soft-bit compression described below allows the memory controller 120 to read data from the defined memory spaces, i.e., the pages split into 64-bit fixed size segments because the CSB circuitry 118 adaptively compresses soft-bits corresponding to the 64-bit fixed size segments to an even smaller fixed size (e.g. 12 bits) based on NAND conditions 50 and/or system conditions”), wherein the plurality of compressed data segments of the compressed data are generated by compressing the plurality of SD data segments according to a fixed compression ratio (Zamir, col. 6, lines 41-50, col. 10, lines 50-65, and col. 11, lines 26-37 teaches the compressed soft-bit circuitry 118 implementing fixed lossy compression schemes having compression ratio like approximately 18.75%, 25%, and 50%), wherein the fixed compression ratio is determined based on information associated with an error bit to be corrected using the SD data (Zamir, col. 7, lines 43-57, col. 8, lines 13-20 & lines 42-54, and col. 11, lines 26-37 teaches the compressed soft-bit circuitry 118 determining a compression ratio based on bit error rate and selects different fixed lossy compression schemes as the bit error rate changes).
Zamir fails to teach a plurality of variable compression ratios and wherein the plurality of variable compression ratios is respectively applied to the plurality of SD data segments.
However, Kim, in an analogous art, teaches a plurality of variable compression ratios (Kim, para. [0014], [0161], [0171], & [0179]-[0180] teaches soft data being divided into separate portions and respective compression tables after selected for the portions based on error rate information corresponding to each portion; while the reference does not explicitly teach “variable compression ratios”, it teaches different compression tables that can produce different compression ratios, which equates to the limitation) and wherein the plurality of variable compression ratios is respectively applied to the plurality of SD data segments (Kim, para. [0014], [0161], [0179]-[0180], & [0211]-[0213] teaches a compression method selector selecting a respective compression table for each of multiple soft-data portions based on error rate information for the portion, and a compressor generates compressed data for each portion).
Zamir and Kim are both considered to be analogous to the claimed invention because both are in the same field of compression techniques within a memory system/device.
Therefore, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to have modified the memory device taught by Zamir to incorporate the teachings of Kim by including the functionality of applying respective variable compression settings to individual soft decision data segments.
The suggestion/motivation for doing so would be to improve compression efficiency and preserve reliability information needed for error correction.
Regarding claim 4, the combination of Zamir in view of Kim teaches the memory device according to claim 1, wherein the fixed compression ratio decreases as a number of memory units in which a number of error bits occurred during data read is equal to or greater than a threshold decreases, among the plurality of memory units (Zamir, col. 8, lines 42-54 teaches bit error rate conditions can be determined for individual logical pages; col. 11, lines 26-37 teaches compression settings changing according to bit error rate thresholds).
Regarding claim 5, the combination of Zamir in view of Kim teaches the memory device according to claim 1, wherein the page buffer circuit is further configured to acquire, using a hard read voltage, hard decision (HD) data from the memory cell array comprising the plurality of memory units (Zamir, col. 2, lines 14-21 teaches read/write circuitry reading hard bits and senses corresponding soft bits; col. 6, lines 30-40 teaches hard bits and soft bits corresponding to one or more logical pages; col. 8, lines 42-54 teaches bit error rate conditions can be determined for individual logical pages), and wherein the plurality of variable compression ratios are determined based on a number of error bits generated on the HD data for each of the plurality of memory units (Kim, para. [0014] teaches compression tables being selected separately for different soft data portions based on error rate information for each portion; para. [0171] teaches error rate information may include the number of error bits detected through previous error correction decoding).
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to have modified Zamir to incorporate the teachings of Kim by including the functionality of selecting compression tables separately for different soft data portions based on error information.
The suggestion/motivation for doing so would be to adapt the compression of soft decision data to the error characteristics of the memory units and preserve the information needed to correct errors in the hard decision data.
Regarding claim 6, the combination of Zamir in view of Kim teaches the memory device according to claim 5, wherein the plurality of variable compression ratios comprise: a first variable compression ratio applied to a first SD data segment acquired from a first memory unit among the plurality of memory units; and a second variable compression ratio applied to a second SD data segment acquired from a second memory unit among the plurality of memory units, and wherein, based on a number of error bits generated for the first memory unit being greater than a number of error bits generated for the second memory unit (Zamir, col. 7, lines 43-56 and col. 8, lines 42-54 teaches determining error conditions individually for respective logical pages and that a higher bit error rate requires a higher compression ratio to preserve additional error correction information), the first variable compression ratio is determined to be higher than the second variable compression ratio (Kim, para. [0014] and [0179]-[0180] teaches applying respective compression settings to different soft data portions based on error rate information associated with the respective portions).
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to have modified Zamir to incorporate the teachings of Kim by including the functionality of applying different compression settings to different soft data portions based on error information.
The suggestion/motivation for doing so would be to preserve more reliability information for memory units that have higher error counts and reducing the amount of compressed data for memory units that have fewer errors.
Regarding claim 7, the combination of Zamir in view of Kim teaches the memory device according to claim 5, wherein the memory device further comprises a bit counter configured to count a number of error bits generated on the HD data for each of the plurality of memory units, and wherein the plurality of variable compression ratios are determined based on the number of error bits counted by the bit counter (Zamir, col. 8, lines 42-54 teaches determining error conditions individually for respective logical pages and that a higher bit error rate requires a higher compression ratio to preserve additional error correction information; Kim, para. [0014] and [0171] teaches compression selections depending on respective error information, including a number of detected error bits).
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to have modified Zamir to incorporate the teachings of Kim by including the functionality of determining variable compression ratios based on the number of error bits.
The suggestion/motivation for doing so would be to determine compression rations based on error characteristics of each memory unit and improve compression efficiency.
Regarding claim 11, the combination of Zamir in view of Kim teaches the memory device according to claim 1, wherein each of the plurality of memory units is a page (Zamir, col. 6, lines 36-43, “The set of hard bits may represent a single logical page or one or more logical pages. The set of soft-bits may represent a corresponding single logical page or a corresponding one or more logical pages. The compressed soft-bit (CSB) circuitry 118 allows defined memory spaces, such as pages, to be split into smaller fixed size segments”).
Regarding claim 12, the combination of Zamir in view of Kim teaches the memory device according to claim 1, wherein each of the plurality of compressed data segments comprises a bit pattern indicating start information, end information, or size information of each of the plurality of compressed data segments (Kim, para. [0213] teaches generating compressed data by adding end data to the soft data and compressing the resulting data; para. [0218] teaches determining whether decompressed data includes end data at its last portion).
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to have modified Zamir to incorporate the teachings of Kim by including the functionality of separately compressing soft data portion and incorporating end data into compressed soft data.
The suggestion/motivation for doing so would be to identify the boundaries of the data segments and allow for reliable decompression of the compressed segments.
Regarding claim 16, the combination of Zamir in view of Kim teaches the memory device according to claim 1, wherein each of the plurality of memory units comprises a plurality of memory sub-units, each of the plurality of SD data segments comprises a plurality of SD data sub-segments acquired from the plurality of memory sub-units, and the compression circuit is further configured to compress a first SD data segment among the plurality of SD data segments based on a sub-fixed compression ratio and a plurality of sub-variable compression ratios applied to the plurality of SD data sub-segments included in the first SD data segment (Zamir, col. 6, lines 37-50 teaches pages being divided into fixed sized segments and corresponding soft bit segments being compressed; Kim, para. [0014] and [0179]-[0180] teaches soft data being divided into portions and those portions being compressed differently). The references do not explicitly teach the limitation; however, it would have been obvious to apply the same segment specific compression technique to smaller subdivisions of a memory unit to adapt compression at a finer granular level.
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to have modified Zamir to incorporate the teachings of Kim by including the functionality of applying respective compression ratios to soft decision data subsegments.
The suggestion/motivation for doing so would be to adapt compression at a finer granularity based on the error characteristics of individual memory subunits.
Regarding claim 18, the combination of Zamir in view of Kim teaches the memory device according to claim 16, wherein each of the plurality of memory units is a plurality of pages, and each of the plurality of memory sub-units is one page. (Zamir, col. 4, lines 49-61 teaches memory being organized into larger groups or blocks; col. 6, lines 37-50 teaches data being organized into logical pages; a block or the group of pages equates to a memory unit, and each individual logical page equates to memory subunit).
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to have modified Zamir to incorporate the teachings of Kim by including the functionality of organizing memory units as groups of pages and memory subunits as individual pages.
The suggestion/motivation for doing so would be to apply adaptive compression efficiently to page-level portions of data within larger memory groups.
Claim 19 is a method with limitations similar to the device of claim 1, and is rejected under the same rationale.
Regarding claim 20, Zamir teaches a memory system (Zamir, Fig. 1, data storage system 100), comprising: a memory device configured to: acquire hard decision (DD) data from a memory cell array comprising a plurality of memory units using a hard read voltage, (Zamir, col. 2, lines 13-21, col. 5, lines 2-21 and col. 6, lines 29-40 teaches read/write circuitry 140 reading hard bits from storage elements, with the hard bits corresponding to one or more logical pages; the logical pages equate to memory units), acquire soft decision (SD) data comprising a plurality of SD data segments from the plurality of memory units using a soft read voltage (Zamir, Fig. 1, read/write circuitry 140 and set of latches 111, which includes latch 112, 114 & 116; col. 2, lines 11-25, col. 6, lines 29-50, col. 7, lines 2-21, and col. 8, lines 21-25 teach soft bits being sensed using soft bit sensing positions separated from hard bit position by a soft bit delta, and the soft bits correspond to logical pages, with the pages being divided into fixed size segments), determine a fixed compression ratio (Zamir, col. 7, lines 43-56, col. 8, lines 13-20 & lines 42-54, col. 10, lines 50-65, and col. 11, lines 26-37 teaches determining an error dependent fixed compression ratio by selecting a fixed lossy compression scheme based on bit error rate), and generate compressed data comprising a plurality of compressed data segments corresponding to the plurality of SD data segments based on the fixed compression ratio (Zamir, col. 6, lines 41-50 and col. 8, lines 26-34 teaches the compressed soft bit circuitry generating compressed segments corresponding to soft bit data segments); and a memory controller configured to: receive the HD data and the compressed data (Zamir, Fig. 1, col. 6, lines 29-62 teaches controller 120 receiving hard data and compressed soft bit data from memory 104 over bus 106), decompress the compressed data to acquire the SD data (Zamir, Fig. 1, col. 6, lines 4-19 teaches controller memory 124 including a soft bit lossy decompressor 160 configured to decompress the compressed soft bit data to acquire soft bit reliability information), and correct an error in the HD data based on the HD data and the SD data (Zamir, col. 2, lines 21-38, col. 6, lines 4-19, and col. 6, lines 29-40 teaches ECC engine 126 configured to correct errors in hard bit data using the hard bit data and decompressed soft bit reliability information, including by adjusting LLR values based on the quality of the soft bit data).
Zamir fails to teach a plurality of variable compression ratios applied to each of the plurality of SD data segments based on information associated with an error bit to be corrected using the SD data and the plurality of variable compression ratios.
However, Kim, in an analogous art, teaches teach a plurality of variable compression ratios applied to each of the plurality of SD data segments based on information associated with an error bit to be corrected using the SD data (Kim, para. [0014], [0161], [0171], & [0179]-[0180] teaches soft data being divided into separate portions and respective compression tables after selected for the portions based on error rate information corresponding to each portion; while the reference does not explicitly teach “variable compression ratios”, it teaches different compression tables that can produce different compression ratios, which equates to the limitation) and the plurality of variable compression ratios (Kim, para. [0014] and [0211]-[0213] teaches generating compressed data for respective soft data portions using respective compression tables).
Zamir and Kim are both considered to be analogous to the claimed invention because both are in the same field of compression techniques within a memory system/device.
Therefore, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to have modified the memory device taught by Zamir to incorporate the teachings of Kim by including the functionality of applying respective variable compression settings to individual soft decision data segments.
The suggestion/motivation for doing so would be to improve compression efficiency and preserve reliability information needed for correcting the hard decision data.
Claims 13-14 are rejected under 35 U.S.C. 103 as being unpatentable over Zamir in view of Kim, as applied to claim 1 above, and further in view of Sravan et al. (US 2022/0129163), hereinafter Sravan.
Regarding claim 13, the combination of Zamir in view of Kim teaches the memory device according to claim 1, but fails to teach wherein the compression circuit is further configured to generate the compressed data by encoding a position of a bit having a first value among a plurality of bits of the SD data.
However, Sravan, in an analogous art, teaches wherein the compression circuit is further configured to generate the compressed data by encoding a position of a bit having a first value among a plurality of bits of the SD data (Sravan, para. [0105] and [0111]-[0115] teach soft data containing sparse logic-1 values and corresponding indicators identify the byte and bit positions of the logic-1 values).
Zamir, Kim, and Sravan are considered to be analogous to the claimed invention because they are in the same field of soft data compression.
Therefore, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to have modified the combination of Zamir in view of Kim to incorporate the teachings of Sravan by including the functionality of encoding bit positions having a first value on the soft decision data.
The suggestion/motivation for doing so would be to efficiently compress sparse soft decision data by encoding the locations of infrequent bit values, which reduces the amount of data transmitted.
Regarding claim 14, the combination of Zamir in view of Kim, further in view of Sravan teaches the memory device according to claim 13, wherein a bit in the SD data representing the first value corresponds to an area having a relatively low read reliability in threshold voltage distributions of a plurality of memory cells included in the memory cell array, and a bit in the SD data representing a second value different from the first value corresponds to an area having a relatively high read reliability in the threshold voltage distributions (Sravan, para. [0103]-[0105] teaches that a soft data bit having a first value of 1 corresponds to memory cells in overlapping threshold voltage distributions associated with lower read reliability, and a soft data bit having a second value of 0 corresponds to memory cells outside the overlapping distributions associated with higher read reliability).
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to have modified the combination of Zamir in view of Kim to incorporate the teachings of Sravan by including the functionality of soft decision data bits having different first and second values, corresponding to a low read reliability and high read reliability area, respectively, in threshold voltage distributions.
The suggestion/motivation for doing so would be to represent read positions from reliable read position so that error correction circuitry can identify unreliable memory cell data.
Claim 15 is rejected under 35 U.S.C. 103 as being unpatentable over Zamir in view of Kim, as applied to claim 1 above, and further in view of Azuma et al. (US 2025/0342871), hereinafter Azuma.
Regarding claim 15, the combination of Zamir in view of Kim teaches the memory device according to claim 1, but fails to teach wherein the page buffer circuit is further configured to: acquire HD data, using a hard read voltage, from the memory cell array comprising the plurality of memory units; and acquire the SD data based on an uncorrectable error correction code (UECC) event occurred for the HD data.
However, Azuma, in an analogous art, teaches wherein the page buffer circuit is further configured to: acquire HD data, using a hard read voltage, from the memory cell array comprising the plurality of memory units; and acquire the SD data based on an uncorrectable error correction code (UECC) event occurred for the HD data (Azuma, Fig. 13, step S15 teaches reading soft bits only after hard bit decoding processing fails).
Zamir, Kim, and Azuma are considered to be analogous to the claimed invention because they are in the same field of soft data compression.
Therefore, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to have modified the combination of Zamir in view of Kim to incorporate the teachings of Azuma by including the functionality of acquiring soft decision data after hard decision decoding failed.
The suggestion/motivation for doing so would be to reduce unnecessary soft read operations by acquiring soft decision information when hard decision error correction cannot successfully recover stored data.
Allowable Subject Matter
Claims 2, 8-10, and 17 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Tishbi et al. (US 2022/0374308) teaches selecting soft read data parameters and compressing confidence information based on the number of errors that need correcting.
Kaynak et al. (US 2026/0030101) teaches selecting soft read thresholds based on compression ratio, reliability information, and error correction capability.
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/G.V.B./Examiner, Art Unit 2112
/ALBERT DECADY/Supervisory Patent Examiner, Art Unit 2112
