DETAILED ACTION
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1-10, 12 and 14-16 is/are rejected under 35 U.S.C. 103 as being unpatentable over Rhe (US 2019/0339818) in view of Xu (US 2021/0357074).
Regarding claim 1, Rhe discloses a display device, comprising:
a display panel (DISP, fig. 1) including an active area (TSP, fig. 1);
an encapsulation layer (ENCAP, fig. 7) located in the active area;
a transistor (T1, fig. 9) under the encapsulation layer (ENCAP, fig. 9), the transistor including a gate electrode (NE1, fig. 9), a source electrode (NE2, fig. 9), and a drain electrode (NE3, fig. 9);
a plurality of touch electrodes (Y-TE, fig. 8-9) located in the active area of the display panel, and disposed on the encapsulation layer (see fig. 8-9);
a plurality of link lines (se horizontal Y-TL in fig. 8) located outside of the active area (see fig. 8);
a plurality of pads (Y-TP, fig. 8) each electrically connected to a corresponding one of the plurality of link lines (see fig. 8);
a plurality of pad lines (see vertical Y-TL directly connected to Y-TP in fig. 8) each electrically connected to a corresponding one of the plurality of pads (fig. 8)
wherein the plurality of pads include:
a plurality of first pads (Y-TP, fig. 8) located in a first region (see Y pad location in fig. 8), each of the plurality of first pads being electrically coupled to a corresponding one of a plurality of first pad lines among the plurality of pad lines (see fig. 8),
a plurality of second pads (X-TP in fig. 8) located in a second region different from the first region (see X pad location in fig. 8), each of the plurality of second pads being electrically coupled to a corresponding one of a plurality of second pad lines (X-TL in fig. 8) among the plurality of pad lines (see fig. 8).
Rhe fails to disclose in insulation layer located between first and second pad lines.
Xu discloses the plurality of first pad lines (20, fig. 1) and the plurality of first pads (302 in fig. 1-2) disposed on a same layer (para. 50); and wherein a layer of the plurality of second pad lines (26, fig. 1) is different from a layer of the plurality of first pad lines (para. 50-51), and wherein the display device further comprises a first insulation layer (see insulating layer in para. 50, 52) between the layer of the plurality of first pad lines and the layer of the plurality of second pad lines (para. 50-51).
When the invention was made (pre-AIA ) or before the effective filing date of the claimed invention (AIA ), it would have been obvious to one of ordinary skill in the art to include the teachings of Xu in the device of Rhe. The motivation for doing so would have been to form a first pad and line located on the same first layer using a first patterning process and to form a second pad and line located same second layer using a second pattern process (Rhe; para. 50-51, wherein by having separate layers, noise is reduced, resulting in more accurate touch detection).
Regarding claim 2, Rhe discloses wherein the plurality of first pad lines and the plurality of second pad lines are not exposed to outside (para. 60; wherein all the pad lines are located inside of the display device).
Regarding claim 3, Rhe discloses wherein a layer where at least a portion of the plurality of first pads is disposed is the same layer as the source electrode or the drain electrode of the transistor (see fig. 9; wherein Y-TP and both the source electrode NE2 and the drain electrode NE3 are located on the INS layer).
Regarding claim 4, Xu discloses wherein a layer where at least a portion of the plurality of first pad lines is disposed is the same as the layer where the at least a portion of the plurality of first pads is disposed (para. 50-51). Wherein the same ration used to combine Rhe and Xu stated in claim 1 applies to claim 4.
Regarding claim 5, Xu discloses wherein a layer where at least a portion of the plurality of second pad lines is disposed is the same as a layer where at least a portion of the plurality of second pads is disposed (para. 50-51). Wherein the same ration used to combine Rhe and Xu stated in claim 1 applies to claim 5.
Regarding claim 6, Xu discloses wherein a layer where at least a portion of the plurality of link lines is disposed is the same as a layer where at least a portion of the plurality of first pads or at least a portion of the plurality of second pads is disposed (para. 50-51). Wherein the same ration used to combine Rhe and Xu stated in claim 1 applies to claim 5.
Regarding claim 7, Rhe discloses wherein a layer where at least a portion of the plurality of first pads is disposed is the same layer as a layer where at least a portion of the plurality of second pads is disposed (see X-TP and Y-TP in fig. 8-9).
Regarding claim 8, Rhe discloses wherein the first insulation layer (INS, fig. 9) overlaps with the transistor (T1, fig. 9).
Regarding claim 9, Rhe discloses wherein at least a portion of at least one of at least one of the plurality of first pads and at least one of the plurality of second pads extends parallel to a surface of a substrate on which the active area is defined 9see 302 and 304 in fig. 1-2).
Regarding claim 10, Rhe discloses wherein in a pad area at which at least one of the plurality of pads is coupled to corresponding one of the plurality of pad lines (see fig. 9), the at least one of the plurality of pads is disposed in a layer same as a layer where at least one of the gate electrode, the source electrode, and the drain electrode of the transistor is disposed (see fig. 9 wherein Y-TP and NE2 are both on the INS layer).
Regarding claim 12, Rhe discloses a first metal layer (NE1, fig. 9), a second metal layer (NE2, fig. 9), and a third metal layer (NE3, fig. 9), which are disposed in layers lower than a layer where the encapsulation layer is disposed in a cross-sectional view (see fig. 9),
wherein the first metal layer is the same as the gate electrode of the transistor, and the second metal layer is the same as one of the source electrode and the drain electrode of the transistor (see fig. 9).
Regarding claim 14, Rhe discloses a protective film (PAC, fig. 9) disposed in at least some area on the plurality of first pad lines (Y-TL in fig. 9) and the plurality of second pad lines (as applied to X-TL in fig. .8),
wherein the plurality of first pad lines are located in an area overlapping with the protective film (see fig. 9 and para. 151).
Regarding claim 15, Rhe discloses wherein: the protective film is disposed in at least some area of an area except for an area where the plurality of first pads are disposed (see fig. 9 and para. 151); and
a part of an outer boundary of the protective film (right side of PAC in fig. 9) overlaps an inner outer boundary (right curved side of ENCAP in fig. 9) adjacent to the plurality of first pad lines (Y-TL in fig. 9) among an outer boundary (Bank, fig. 9) of each of the plurality of first pads.
Regarding claim 16. Rhe discloses an insulating film (ILD, fig. 9) disposed on the second pad line in an area where the protective film is not disposed (see fig. 9).
Allowable Subject Matter
Claims 11 and 13 objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Conclusion
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/ROBIN J MISHLER/Primary Examiner, Art Unit 2628