DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
1. This action is responsive to the application filed on 05/01/2025.
2. Claims 1-20 are pending.
3. Claims 1-20 are rejected.
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 02/24/2025 is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Claim Rejections - 35 USC § 103
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claims XXX are rejected under 35 U.S.C. 103 as being unpatentable over Yilong Geng et al (US 20220345412 A1), hereinafter “Geng” in view of Hans-Juergen Schmidtke et al (WO 2022221459 A1), hereinafter “Schmidtke”.
Regarding Claim 1 and Claim 15, Geng discloses a method and a system comprising:
memory with instructions encoded thereon (Geng, Paragraph 0045, memory to perform instructions);
and one or more processors of one or more machines connected by a network that, when executing the instructions (Geng, Paragraph 0045, one or more processors), are caused to perform operations comprising:
capturing, by a sender host, timestamp of a system clock of the sender host (Geng, Paragraphs 0016-0017, sender includes a buffer which stores data related to data transmissions, including a time stamp);
writing, by the sender host, the system clock timestamp to memory of the system host (Geng, Paragraph 0017, buffer stores a byte stamp may be stored rather than the packet itself, the byte stamp indicating an identifier of the packet and/or flow identifier and a time stamp at which the packet (or aggregate data flow) was sent);
reading directly from the memory, by a component of the sender host, the timestamp (Geng, Paragraph 0025, sender host sends the timestamp to the receiver host);
writing, by the component of the receiver host, the timestamp to memory of the receiver host (Geng, Paragraph 0025, receiver host receives the timestamp from the sender host and applies the receiver timestamp);
calculating, by the receiver host, a one-way delay (OWD) between the sender host and the receiver host using the timestamp (Geng, Paragraph 0026, receiver host calculates the one-way delay using the received timestamp);
and outputting a control signal based on the one-way delay (Geng, Paragraphs 0027-0028, after determining the one-way delay, netcam module instructs the sender/receiver to take one or more actions, wherein the one or more actions include pausing transmission from that sender host when one-way delay is high, which reduces congestion and thereby reduces packet drops on network in general).
However, Geng fails to explicitly disclose transmitting, from the component of the sender host to a component of a receiver host, the timestamp over a Remote Direct Memory Access (RDMA) network.
Schmidtke, from the same or similar field of endeavor, discloses transmitting, from the component of the sender host to a component of a receiver host, the timestamp over a Remote Direct Memory Access (RDMA) network (Schmidtke, Paragraph 0013, transaction module assigns the timestamp to each of the one or more transactions utilizing remote direct memory access (RDMA) packets to timestamp the transactions).
Therefore, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to modify Geng in view of Schmidtke in order to further modify the method of clock-synchronized edge-based data flow priority assignment from the teachings of Geng with the method of using high-bandwidth memory to implement a precision time memory processing system from the teachings of Schmidtke.
One of ordinary skill in the art would have been motivated because by using a RDMA transactions the system will be able to preserve a timing accuracy when the packets are being sent to their destination (Schmidtke – Abstract, Paragraphs 0002-0006).
Regarding Claim 2, the combination of Geng and Schmidtke disclose the method of claim 1 above, where Geng further discloses wherein the component of the sender host is a network interface card (NIC) of the sender host (Geng, Paragraph 0021, components of both sender host and receiver host include a NIC).
Regarding Claim 3, the combination of Geng and Schmidtke disclose the method of claim 1 above, where Geng further discloses wherein the component of the receiver host is a network interface card (NIC) of the receiver host (Geng, Paragraph 0021, components of both sender host and receiver host include a NIC).
Regarding Claim 4, the combination of Geng and Schmidtke disclose the method of claim 1 above, where Schmidtke further discloses wherein reading, directly from memory, by the component of the sender host, the timestamp comprises bypassing an operating system (OS) kernel stack of the system host (Schmidtke, Paragraph 0038, memory of both source computing device and destination computing device include high-bandwidth memory devices capable of providing direct memory access (RDMA), which refers to a direct memory access from the memory of one computing device into that of another without involving either computing device's operating system, thereby permitting high-throughput and low-latency networking).
Regarding Claim 5, the combination of Geng and Schmidtke disclose the method of claim 1 above, where Schmidtke further discloses wherein transmitting the timestamp to the component of the receiver host occurs as part of a RDMA operation performed by the receiver host requesting the timestamp (Schmidtke, Paragraph 0038, performing transaction messages between source computing device and destination computing device through the use of the RDMA of both devices. Paragraph 0042, using RDMA packets to timestamp the transactions on the devices).
Regarding Claim 7, the combination of Geng and Schmidtke disclose the method of claim 1 above, where Schmidtke further discloses wherein the control signal is for synchronizing clocks of the sender host and the receiver host (Schmidtke, Paragraphs 0039-0042, assigning timestamps to clock synchronization protocol transactions in order to achieve synchronization between source computing device and destination computing device).
Claim 8 carries similar limitations as discussed with regards to Claim 1 above and therefore is rejected for the same reason.
Regarding Claim 9, this claimed limitation is the same as the limitation addressed to Claim 2 above. Therefore, it is rejected under the same rationale.
Regarding Claim 10, this claimed limitation is the same as the limitation addressed to Claim 3 above. Therefore, it is rejected under the same rationale.
Regarding Claim 11, this claimed limitation is the same as the limitation addressed to Claim 4 above. Therefore, it is rejected under the same rationale.
Regarding Claim 12, this claimed limitation is the same as the limitation addressed to Claim 5 above. Therefore, it is rejected under the same rationale.
Regarding Claim 14, this claimed limitation is the same as the limitation addressed to Claim 7 above. Therefore, it is rejected under the same rationale.
Regarding Claim 16, this claimed limitation is the same as the limitation addressed to Claim 2 and Claim 9 above. Therefore, it is rejected under the same rationale.
Regarding Claim 17, this claimed limitation is the same as the limitation addressed to Claim 3 and Claim 10 above. Therefore, it is rejected under the same rationale.
Regarding Claim 18, this claimed limitation is the same as the limitation addressed to Claim 4 and Claim 11 above. Therefore, it is rejected under the same rationale.
Regarding Claim 19, this claimed limitation is the same as the limitation addressed to Claim 5 and Claim 12 above. Therefore, it is rejected under the same rationale.
Claims XXX are rejected under 35 U.S.C. 103 as being unpatentable over Geng et al and in view of Schmidtke, as applied to claims 1, 8, and 15 above, and further in view of Diego Crupnicoff et al (WO 2019046603 A1), hereinafter “Crupnicoff”.
Regarding Claim 6, the combination of Geng and Schmidtke disclose the method of claim 1 above.
However, the combination of Geng and Schmidtke fail to explicitly disclose wherein the control signal is for performing congestion control dependent on clock synchronization in the RDMA network.
Crupnicoff, from the same or similar field of endeavor, discloses wherein the control signal is for performing congestion control dependent on clock synchronization in the RDMA network (Crupnicoff, Paragraph 0005, providing congestion control management using RDMA).
Therefore, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to modify Geng in view of Schmidtke and in further view of Crupnicoff in order to further modify the method of clock-synchronized edge-based data flow priority assignment from the teachings of Geng and the method of using high-bandwidth memory to implement a precision time memory processing system from the teachings of Schmidtke with the method of XXXX from the teachings of Crupnicoff.
One of ordinary skill in the art would have been motivated because XXXX (Crupnicoff – XXXX).
Regarding Claim 13, this claimed limitation is the same as the limitation addressed to Claim 6 above. Therefore, it is rejected under the same rationale.
Regarding Claim 20, this claimed limitation is the same as the limitation addressed to Claim 6 and Claim 13 above. Therefore, it is rejected under the same rationale.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. All the references listed on 892 are related to the subject matter of synchronizing system clocks on RDMA networks.
Some of the prior art include:
US 12627460 B2, which discloses a method of clock synchronization between networked devices based on packet congestion information.
WO 2019046603 A1, which discloses a method of network congestion management.
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/JAVIER O GUZMAN/ Primary Examiner, Art Unit 2496
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