Detailed Action
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
This application claims the benefit of U.S. Provisional Application No. 63/710,591, filed on October 22nd, 2024. claims 1-14 are pending for examination.
Specification
The lengthy specification has not been checked to the extent necessary to determine the presence of all possible minor errors. Applicant's cooperation is requested in correcting any errors of which applicant may become aware in the specification.
Claim Rejections - 35 USC § 102
the following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1-6, 12-14 are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Weinberg et al., US 2024/0028244 A1.
Regarding claims 1 and 12, Weinberg teaches a method for performing access control of a memory device with aid of expander architecture (Fig.1 and abstract; Methods of operating memory systems with input/output expanders for multi-channel status reads (and associated systems and devices) are disclosed), the method being at least applicable to a memory controller within the memory device, the memory device comprising the memory controller (controller 106 in Fig.1) and a non-volatile (NV) memory (Fig.1; a memory package 102), the NV memory comprising a plurality of NV memory elements (logical units 120; section 0015; the logical units 120 can be individual memory dies arranged in a memory package 102), the method comprising:
sending at least one command from the memory controller to the NV memory (section 0008; a memory controller issues a multi-channel status read command to an I/O expander over a front-end channel. The multi-channel status read command prompts the I/O expander to transmit status read commands to logical units (e.g., memory packages, memory dies) over two or more back-end channels) through an input-output-expander (IO-expander) circuit (Fig.1; I/O expander 104), with the IO-expander circuit being coupled between the memory controller and the NV memory (Fig.1), in order to start performing at least one access operation on the plurality of NV memory elements via multiple channels, respectively (Fig.1; abstract and section 0043; the I/O expander 104 can cycle through the first and second back-end channels 118a and 118b to transmit the first and second status read data, respectively, to the controller 106 via the front-end channel 117); and
during performing any access operation among the at least one access operation, utilizing the IO-expander circuit to expand IO control of the memory controller over the NV memory (Fig.1; section 0023; the I/O expander 104 is configured to selectively couple the front-end channel 117 to one or more of the back-end channels 118 to facilitate transmitting communications between (a) the controller 106 and (b) one or more of the logical units 120 or one or more groups of the logical units 120), for accessing at least one NV memory element corresponding to any sub-channel among a plurality of sub-channels (Fig.1 and section 0020; the controller 106 communicates with the logical units 120 via the I/O expander 104. More specifically, a front-end channel 117 (e.g., a single front-end channel, only one front-end channel, one of a plurality of front-end channels) operably couples the controller 106 to a front-end (of first) interface of the I/O expander 104, and a plurality of back-end channels 118 (identified individually in FIG. 1 as first back-end channel 118a, second back-end channel 118b, third back-end channel 118c, and fourth back-end channel 118d) operably couple a back-end (or second) interface of the I/O expander 104 to corresponding logical units 120), the plurality of sub-channels split from a single channel among the multiple channels under control of the IO-expander circuit (section 0020 and 0060; the I/O expanders can be configured to transmit status read commands to logical units over each of the two or more back-end channels in response to a single multi-channel status read command).
For claim 12, Weinberg further teaches a processing circuit, arranged to control the memory controller according to a plurality of host commands from a host device (Fig.1 and section 0008; The multi-channel status read command prompts the I/O expander to transmit status read commands to logical units (e.g., memory packages, memory dies) over two or more back-end channels), to allow the host device to access the NV memory through the memory controller (Fig.1).
Regarding claim 2, Weinberg teaches the any sub-channel among the plurality of sub-channels is configured for coupling multiple NV memory elements acting as multiple loads (Fig.1 and section 0008; the multi-channel status read command prompts the I/O expander to transmit status read commands to logical units (e.g., memory packages, memory dies) over two or more back-end channels), wherein the at least one NV memory element corresponding to the any sub-channel belongs to the multiple NV memory elements acting as the multiple loads (section 0008; the I/O expander cycles through the individual back-end channels of the two or more back-end channels to feed the status read data from a corresponding back-end channel to the memory controller over the front-end channel).
Regarding claim 3, Weinberg teaches regarding the single channel, multiple branches of circuits are formed with a combination of multiple one-to-many interface sub-circuits and all NV memory elements acting as loads of the multiple one-to-many interface sub-circuits (Fig.1 and abstract; receiving, via a controller-side communication channel, a multi-channel status read command at a first interface of an input/output expander), wherein said all NV memory elements acting as the loads of the multiple one-to-many interface sub-circuits comprise the multiple NV memory elements acting as the multiple loads (Fig.1 and abstract; the method further comprises, based at least in part on receiving the multi-channel status read command, (a) transmitting, via a second interface of the input/output expander, a status read command to logical units over each of two or more memory-side channels; (b) receiving, at the second interface, status read data from the logical units over each memory-side channel of the two or more memory-side channels).
Regarding claim 4, Weinberg teaches regarding the single channel, multiple branches of circuits are formed with a combination of multiple one-to-many interface sub-circuits and all NV memory elements acting as loads of the multiple one-to-many interface sub-circuits (Fig.1 and abstract; receiving, via a controller-side communication channel, a multi-channel status read command at a first interface of an input/output expander).
Regarding claim 5, Weinberg teaches transferred data between the memory controller and IO-expander circuit comprises a message but does not include any low-density parity-check (LDPC)-parity, thereby saving transferring overhead at the memory controller (section 0052; The read enable signal fe_re # can be used to instruct the I/O expander 104 to begin outputting communications (e.g., data or other information) to the controller 106 via the front-end channel 117).
Regarding claim 6, Weinberg teaches further comprising: offloading LDPC coder and decoder (LDPC-codec) processing into the IO-expander circuit to make the IO-expander circuit handle the LDPC-codec processing regarding the transferred data (section 0016; The logical units 120 (or a memory package 102 including the logical units 120) can include other circuit components or memory subsystems (not shown), such as multiplexers, decoders, buffers, read/write drivers, address registers, data out/data in registers, etc., for accessing and/or programming (e.g., writing) the memory cells 122 and other functionality, such as for processing information and/or communicating with the controller 106 via the I/O expander 104).
Regarding claim 13, Weinberg teaches the memory device (Fig.1; memory device 100) comprises: the NV memory (Fig.1; a memory package 102), configured to store information (section 0002; Memory devices are widely used to store information related to various electronic devices such as computers, wireless communication devices, cameras, digital displays, and the like); the memory controller (controller 106), configured to control operations of the memory device (Fig.1); and the IO-expander circuit (Fig.1 I/O expander 104), coupled between the memory controller and the NV memory (Fig.1), configured to expand the IO control of the memory controller over the NV memory (Fig.1; section 0023; the I/O expander 104 is configured to selectively couple the front-end channel 117 to one or more of the back-end channels 118 to facilitate transmitting communications between (a) the controller 106 and (b) one or more of the logical units 120 or one or more groups of the logical units 120).
Regarding claim 14, Weinberg teaches further comprising: the host device (Fig.1; host 108), coupled to the memory device (Fig.1; memory device 100), wherein the host device comprises: at least one processor, arranged for controlling operations of the host device; and a power supply circuit, coupled to the at least one processor, arranged for providing power to the at least one processor and the memory device; wherein the memory device provides the host device with storage space (section 0002 and Fig.4 ).
Allowable Subject Matter
Claims 7-11 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is an examiner’s statement of reasons for allowance:
The limitations not found in the prior art of record include utilizing two sets of channel buffers within the any one-to-many interface sub-circuit to buffer information on the single channel, wherein among the two sets of channel buffers, a set of channel buffers corresponding to a downlink direction are arranged to buffer transferred data from the memory controller, and a set of channel buffers corresponding to an uplink direction are arranged to buffer transferred data toward the memory controller; and utilizing two sets of sub-channel buffers within the any one-to-many interface sub-circuit to buffer information on a set of sub-channels among the plurality of sub-channels, wherein among the two sets of sub-channel buffers, a set of sub-channel buffers corresponding to the downlink direction are arranged to buffer transferred data toward multiple NV memory element groups corresponding to the set of sub-channels, and a set of sub-channel buffers corresponding to the uplink direction are arranged to buffer transferred data from the multiple NV memory element groups corresponding to the set of sub-channels in combination with the other claimed limitations as described in the claim 7 (claim 8 is depended on claim 7).
The limitations not found in the prior art of record include at least one one-to-many interface sub-circuit, wherein any one-to-many interface sub-circuit among the at least one one-to-many interface sub-circuit comprises: two sets of channel buffers, arranged to buffer information on the single channel, wherein among the two sets of channel buffers, a set of channel buffers corresponding to a downlink direction are arranged to buffer transferred data from the memory controller, and a set of channel buffers corresponding to an uplink direction are arranged to buffer transferred data toward the memory controller; and two sets of sub-channel buffers, arranged to buffer information on a set of sub-channels among the plurality of sub-channels, wherein among the two sets of sub-channel buffers, a set of sub-channel buffers corresponding to the downlink direction are arranged to buffer transferred data toward multiple NV memory element groups corresponding to the set of sub-channels, and a set of sub-channel buffers corresponding to the uplink direction are arranged to buffer transferred data from the multiple NV memory element groups corresponding to the set of sub-channels in combination with the other claimed limitations as described in the claim 9 (claims 10-11 are depended on claim 9).
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Alverson et al., US 2024/0053891 A1 teaches Random access memory (RAM) is attached to an input/output (I/O) controller of a chipset (e.g., on a motherboard). This chipset attached RAM is optionally used as part of a tiered storage solution with other tiers including, for example, nonvolatile memory (e.g., a solid state drive (SSD)) or a hard disk drive. The chipset attached RAM is separate from the system memory, allowing the chipset attached RAM to be used to speed up access to frequently used data stored in the tiered storage solution without reducing the amount of system memory available to an operating system running on the one or more processing units.
Alveson does not clearly teach the limitations such as during performing any access operation among the at least one access operation, utilizing theIO-expander circuit to expand IO control of thememory controller over the NV memory, for accessing at least one NVmemory element corresponding to any sub-channel among a plurality of sub-channels, the plurality of sub-channels split from a single channel among the multiple channels under control of the IO-expander circuit in the claims 1 and 12.
When responding to the office action, Applicant is advised to clearly point out the patentable novelty which he or she thinks the claims present in view of the state of the art disclosed by the references cited or the objections made. He or she must also show how the amendments avoid such references or objections. See 37 C.F.R. 1.111 (c).
When responding to the office action, Applicants are advised to provide the examiner with the line numbers and page numbers in the application and/or references cited to assist examiner to locate the appropriate paragraphs.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to HUA JASMINE SONG whose telephone number is (571)272-4213. The examiner can normally be reached on 9:00am to 5:30pm.
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/HUA J SONG/Primary Examiner, Art Unit 2133
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