DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claim 10 is rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 10 recites the limitation "the voltage control circuit” and “the second node control circuit" in lines 50 and 52. There is no prior recitation of “a voltage control circuit” or “a second node control circuit” as claimed. There is insufficient antecedent basis for this limitation in the claim.
Allowable Subject Matter
Claims 1-9 and 11-20 are allowed.
The following is an examiner’s statement of reasons for allowance:
As to independent claim 1, Ma (U.S. Pub. No. 2018/0211716) discloses a driving circuit (Ma, shift register, Figure 2a), comprising a driving signal generation circuit (Ma, input module 1, first control module 2, and second control module 3, Figure 2a), an output control circuit (Ma, first output module 4 and second output module 5, Figure 2a), a gating circuit (Ma, input module 1, Figure 2a), and an output circuit (Ma, first output module 4 and second output module 5, Figure 2a); wherein
the driving signal generation circuit (Ma, input module 1, first control module 2, and second control module 3, Figure 2a) is electrically connected to a first control node (Ma, first clock signal CK1, Figure 2a), a second control node (Ma, second clock signal CK2, Figure 2a) and an Nth stage of driving signal output terminal (Ma, input signal Input, Figure 2a) respectively, and is configured to generate and output an Nth stage of driving signal through the Nth stage of driving signal output terminal under the control of a potential of the first control node and a potential of the second control node; N is a positive integer; As shown in figure 2a of Ma, the input module 1, first control module 2, and second control module 3 are controlled based on the signals provided by the first clock signal CK1 and the second clock signal CK2.
the output control circuit (Ma, first output module 4 and second output module 5, Figure 2a) is electrically connected to a first node (Ma, first node A, Figure 2a), the first control node and a second node respectively, and is configured to control to connect the first control node (Ma, connected to the first clock signal CK1 through various intervening components, Figure 2a) and the second node (Ma, second node B, Figure 2a) under the control of a potential of the first node (Ma, gate of seventh switching transistor M7 (within first output module 4) is connected to the first node A, Figure 2a);
the gating circuit (Ma, input module 1, Figure 2a) is electrically connected to the first node (Ma, first node A, Figure 2a), a gating input terminal (Ma, input signal Input, Figure 2a) and a gating control terminal (Ma, first clock signal CK1, Figure 2a), and is configured to write a gating input signal provided by the gating input terminal into the first node (Ma, first node A, Figure 2a) under the control of a gating control signal provided by the gating control terminal; As shown in figure 2a of Ma, the input module 1 is controlled by the first clock signal CK1 to send the input signal Input to first node A.
the output circuit (Ma, first output module 4 and second output module 5, Figure 2a) is electrically connected to the second node (Ma, second node B, Figure 2a), the second control node (Ma, second clock signal CK2, Figure 2a), the first node (Ma, first node A, Figure 2a), the first voltage terminal (Ma, first DC signal V1, Figure 2a), a second voltage terminal (Ma, second DC signal V2, Figure 2a) and an output driving terminal (Ma, output terminal Output, Figure 2a), and is configured to control to connect the output driving terminal (Ma, output terminal Output, Figure 2a) and the first voltage terminal (Ma, first DC signal V1, Figure 2a) under the control of a potential of the second node, and control to connect control the output driving terminal and the second voltage terminal under the control of the potential of the second control node; As shown in figure 2a of Ma, the first node A controls seventh switching transistor M7 to connect the second DC signal V2 to the output terminal Output.
wherein the output control circuit includes a third transistor (Ma, eight switching transistor M8, Figure 2a);
wherein the output circuit includes a fifth transistor (Ma, fifth switching transistor M5, Figure 2a), a sixth transistor (Ma, fourth switching transistor M4, Figure 2a), a seventh transistor (Ma, sixth switching transistor M6, Figure 2a), and a second capacitor (Ma, third capacitor C3, Figure 2a);
a first end of the second capacitor (Ma, third capacitor C3, Figure 2a) is electrically connected to the second node (Ma, second node B, Figure 2a), and a second end of the second capacitor is electrically connected to the first voltage terminal (Ma, first DC signal V1, Figure 2a). The capacitor C3 connects to the first DC signal V1 through the eight switching transistor M8.
Ma does not expressly teach wherein the output circuit is configured to control to connect the output driving terminal and the first voltage terminal under the control of a potential of the second node, and control to connect control the output driving terminal and the second voltage terminal under the control of the potential of the second control node;
a gate electrode of the third transistor is electrically connected to the first node, a first electrode of the third transistor is electrically connected to the first control node, and a second electrode of the third transistor is electrically connected to the second node;
a gate electrode of the fifth transistor is electrically connected to the second node, a first electrode of the fifth transistor is electrically connected to the first voltage terminal, and a second electrode of the fifth transistor is electrically connected to the output driving terminal;
a gate electrode of the sixth transistor is electrically connected to the second control node, a first electrode of the sixth transistor is electrically connected to the output driving terminal, and a second electrode of the sixth transistor is electrically connected to the second voltage terminal;
Specifically, Ma does not teach the same circuit configuration claimed.
Additional prior art of Zhang et al. (U.S. Pub. No. 2018/0350315) teaches a drive circuit with a similar configuration but does not teach the configuration of the circuit components and nodes as claimed.
Additional prior art of Zhang et al. (U.S. Pub. No. 2019/0340967) teaches a shift register unit and circuit with a similar configuration but does not teach the configuration of the circuit components and nodes as claimed.
Additional prior art of Zhichong (CN 106971692 A) teaches a drive circuit but does not teach recited circuit configuration with the control nodes connected to the input and output circuit as claimed.
In addition, no other prior art was found which teaches, alone or in combination, the cited limitations.
As to dependent claims 2-9, these claims are allowable as they depend upon allowable independent claim 1.
Examiner includes reasons for allowable subject matter for claim 10 in case the 35 USC 112(b) rejection for this claim is overcome.
As to independent claim 10, Ma (U.S. Pub. No. 2018/0211716) discloses a driving method applied to a driving circuit (Ma, shift register, Figure 2a), wherein the driving circuit comprises a driving signal generation circuit (Ma, input module 1, first control module 2, and second control module 3, Figure 2a), an output control circuit (Ma, first output module 4 and second output module 5, Figure 2a), a gating circuit (Ma, input module 1, Figure 2a), and an output circuit (Ma, first output module 4 and second output module 5, Figure 2a); wherein
the driving signal generation circuit (Ma, input module 1, first control module 2, and second control module 3, Figure 2a) is electrically connected to a first control node (Ma, first clock signal CK1, Figure 2a), a second control node (Ma, second clock signal CK2, Figure 2a) and an Nth stage of driving signal output terminal (Ma, input signal Input, Figure 2a) respectively, and is configured to generate and output an Nth stage of driving signal through the Nth stage of driving signal output terminal under the control of a potential of the first control node and a potential of the second control node; N is a positive integer; As shown in figure 2a of Ma, the input module 1, first control module 2, and second control module 3 are controlled based on the signals provided by the first clock signal CK1 and the second clock signal CK2.
the output control circuit (Ma, first output module 4 and second output module 5, Figure 2a) is electrically connected to a first node (Ma, first node A, Figure 2a), the first control node and a second node respectively, and is configured to control to connect the first control node (Ma, connected to the first clock signal CK1 through various intervening components, Figure 2a) and the second node (Ma, second node B, Figure 2a) under the control of a potential of the first node (Ma, gate of seventh switching transistor M7 (within first output module 4) is connected to the first node A, Figure 2a);
the gating circuit (Ma, input module 1, Figure 2a) is electrically connected to the first node (Ma, first node A, Figure 2a), a gating input terminal (Ma, input signal Input, Figure 2a) and a gating control terminal (Ma, first clock signal CK1, Figure 2a), and is configured to write a gating input signal provided by the gating input terminal into the first node (Ma, first node A, Figure 2a) under the control of a gating control signal provided by the gating control terminal; As shown in figure 2a of Ma, the input module 1 is controlled by the first clock signal CK1 to send the input signal Input to first node A.
the output circuit (Ma, first output module 4 and second output module 5, Figure 2a) is electrically connected to the second node (Ma, second node B, Figure 2a), the second control node (Ma, second clock signal CK2, Figure 2a), the first node (Ma, first node A, Figure 2a), the first voltage terminal (Ma, first DC signal V1, Figure 2a), a second voltage terminal (Ma, second DC signal V2, Figure 2a) and an output driving terminal (Ma, output terminal Output, Figure 2a), and is configured to control to connect the output driving terminal (Ma, output terminal Output, Figure 2a) and the first voltage terminal (Ma, first DC signal V1, Figure 2a) under the control of a potential of the second node, and control to connect control the output driving terminal and the second voltage terminal under the control of the potential of the second control node; As shown in figure 2a of Ma, the first node A controls seventh switching transistor M7 to connect the second DC signal V2 to the output terminal Output.
wherein the output control circuit includes a third transistor (Ma, eight switching transistor M8, Figure 2a);
wherein the output circuit includes a fifth transistor (Ma, fifth switching transistor M5, Figure 2a), a sixth transistor (Ma, fourth switching transistor M4, Figure 2a), a seventh transistor (Ma, sixth switching transistor M6, Figure 2a), and a second capacitor (Ma, third capacitor C3, Figure 2a);
a first end of the second capacitor (Ma, third capacitor C3, Figure 2a) is electrically connected to the second node (Ma, second node B, Figure 2a), and a second end of the second capacitor is electrically connected to the first voltage terminal (Ma, first DC signal V1, Figure 2a). The capacitor C3 connects to the first DC signal V1 through the eight switching transistor M8.
wherein the driving method comprises:
generating and outputting, by the driving signal generation circuit (Ma, input module 1, first control module 2, and second control module 3, Figure 2a), the Nth stage of driving signal through the Nth stage of driving signal output terminal (Ma, output terminal Output, Figure 2a) under the control of the potential of the first control node (Ma, first clock signal CK1, Figure 2a) and the potential of the second control node (Ma, second clock signal CK2, Figure 2a); wherein N is a positive integer;
controlling, by the gating circuit (Ma, input module 1, Figure 2a), to write the gating input signal (Ma, input signal Input, Figure 2a) into the first node (Ma, first node A, Figure 2a) under the control of the gating control signal (Ma, first clock signal CK1, Figure 2a);
Ma does not expressly teach wherein the output circuit is configured to control to connect the output driving terminal and the first voltage terminal under the control of a potential of the second node, and control to connect control the output driving terminal and the second voltage terminal under the control of the potential of the second control node;
a gate electrode of the third transistor is electrically connected to the first node, a first electrode of the third transistor is electrically connected to the first control node, and a second electrode of the third transistor is electrically connected to the second node;
a gate electrode of the fifth transistor is electrically connected to the second node, a first electrode of the fifth transistor is electrically connected to the first voltage terminal, and a second electrode of the fifth transistor is electrically connected to the output driving terminal;
a gate electrode of the sixth transistor is electrically connected to the second control node, a first electrode of the sixth transistor is electrically connected to the output driving terminal, and a second electrode of the sixth transistor is electrically connected to the second voltage terminal;
controlling, by the output control circuit , to connect the first control node and the second node under the control of the potential of the first node;
controlling, by the voltage control circuit, the potential of the second node according to the potential of the first node;
controlling, by the second node control circuit, to connect the second node and the first voltage terminal under the control of the potential of the first node;
controlling, by the output circuit, to connect the output driving terminal and the first voltage terminal under the control of the potential of the second node, and controlling, by the output circuit, to connect the output driving terminal and the second voltage terminal under the control of the potential of the second control node, controlling, by the output circuit, to connect the output driving terminal and the second voltage terminal under the control of the potential of the first node.
Specifically, Ma does not teach the same circuit configuration claimed.
Additional prior art of Zhang et al. (U.S. Pub. No. 2018/0350315) teaches a drive circuit with a similar configuration but does not teach the configuration of the circuit components and nodes as claimed.
Additional prior art of Zhang et al. (U.S. Pub. No. 2019/0340967) teaches a shift register unit and circuit with a similar configuration but does not teach the configuration of the circuit components and nodes as claimed.
Additional prior art of Zhichong (CN 106971692 A) teaches a drive circuit but does not teach recited circuit configuration with the control nodes connected to the input and output circuit as claimed.
In addition, no other prior art was found which teaches, alone or in combination, the cited limitations.
As to independent claim 11, Ma (U.S. Pub. No. 2018/0211716) discloses a driving module, comprising a plurality of stages of driving circuits (Ma, shift register, Figure 2a); wherein the driving circuit (Ma, shift register, Figure 2a), comprises a driving signal generation circuit (Ma, input module 1, first control module 2, and second control module 3, Figure 2a), an output control circuit (Ma, first output module 4 and second output module 5, Figure 2a), a gating circuit (Ma, input module 1, Figure 2a), and an output circuit (Ma, first output module 4 and second output module 5, Figure 2a); wherein
the driving signal generation circuit (Ma, input module 1, first control module 2, and second control module 3, Figure 2a) is electrically connected to a first control node (Ma, first clock signal CK1, Figure 2a), a second control node (Ma, second clock signal CK2, Figure 2a) and an Nth stage of driving signal output terminal (Ma, input signal Input, Figure 2a) respectively, and is configured to generate and output an Nth stage of driving signal through the Nth stage of driving signal output terminal under the control of a potential of the first control node and a potential of the second control node; N is a positive integer; As shown in figure 2a of Ma, the input module 1, first control module 2, and second control module 3 are controlled based on the signals provided by the first clock signal CK1 and the second clock signal CK2.
the output control circuit (Ma, first output module 4 and second output module 5, Figure 2a) is electrically connected to a first node (Ma, first node A, Figure 2a), the first control node and a second node respectively, and is configured to control to connect the first control node (Ma, connected to the first clock signal CK1 through various intervening components, Figure 2a) and the second node (Ma, second node B, Figure 2a) under the control of a potential of the first node (Ma, gate of seventh switching transistor M7 (within first output module 4) is connected to the first node A, Figure 2a);
the gating circuit (Ma, input module 1, Figure 2a) is electrically connected to the first node (Ma, first node A, Figure 2a), a gating input terminal (Ma, input signal Input, Figure 2a) and a gating control terminal (Ma, first clock signal CK1, Figure 2a), and is configured to write a gating input signal provided by the gating input terminal into the first node (Ma, first node A, Figure 2a) under the control of a gating control signal provided by the gating control terminal; As shown in figure 2a of Ma, the input module 1 is controlled by the first clock signal CK1 to send the input signal Input to first node A.
the output circuit (Ma, first output module 4 and second output module 5, Figure 2a) is electrically connected to the second node (Ma, second node B, Figure 2a), the second control node (Ma, second clock signal CK2, Figure 2a), the first node (Ma, first node A, Figure 2a), the first voltage terminal (Ma, first DC signal V1, Figure 2a), a second voltage terminal (Ma, second DC signal V2, Figure 2a) and an output driving terminal (Ma, output terminal Output, Figure 2a), and is configured to control to connect the output driving terminal (Ma, output terminal Output, Figure 2a) and the first voltage terminal (Ma, first DC signal V1, Figure 2a) under the control of a potential of the second node, and control to connect control the output driving terminal and the second voltage terminal under the control of the potential of the second control node; As shown in figure 2a of Ma, the first node A controls seventh switching transistor M7 to connect the second DC signal V2 to the output terminal Output.
wherein the output control circuit includes a third transistor (Ma, eight switching transistor M8, Figure 2a);
wherein the output circuit includes a fifth transistor (Ma, fifth switching transistor M5, Figure 2a), a sixth transistor (Ma, fourth switching transistor M4, Figure 2a), a seventh transistor (Ma, sixth switching transistor M6, Figure 2a), and a second capacitor (Ma, third capacitor C3, Figure 2a);
a first end of the second capacitor (Ma, third capacitor C3, Figure 2a) is electrically connected to the second node (Ma, second node B, Figure 2a), and a second end of the second capacitor is electrically connected to the first voltage terminal (Ma, first DC signal V1, Figure 2a). The capacitor C3 connects to the first DC signal V1 through the eight switching transistor M8.
an Nth stage of driving circuit is electrically connected to a driving signal output terminal of an (N-1)th stage of driving circuit; N is a positive integer (Ma, the gate driving circuit comprises a plurality of cascaded shift register SR(1), SR(2),... , SR(N−1) and SR(N) (totally, N shift registers, 1≤n≤N), ¶ [0177]).
Ma does not expressly teach wherein the output circuit is configured to control to connect the output driving terminal and the first voltage terminal under the control of a potential of the second node, and control to connect control the output driving terminal and the second voltage terminal under the control of the potential of the second control node;
a gate electrode of the third transistor is electrically connected to the first node, a first electrode of the third transistor is electrically connected to the first control node, and a second electrode of the third transistor is electrically connected to the second node;
a gate electrode of the fifth transistor is electrically connected to the second node, a first electrode of the fifth transistor is electrically connected to the first voltage terminal, and a second electrode of the fifth transistor is electrically connected to the output driving terminal;
a gate electrode of the sixth transistor is electrically connected to the second control node, a first electrode of the sixth transistor is electrically connected to the output driving terminal, and a second electrode of the sixth transistor is electrically connected to the second voltage terminal;
Specifically, Ma does not teach the same circuit configuration claimed.
Additional prior art of Zhang et al. (U.S. Pub. No. 2018/0350315) teaches a drive circuit with a similar configuration but does not teach the configuration of the circuit components and nodes as claimed.
Additional prior art of Zhang et al. (U.S. Pub. No. 2019/0340967) teaches a shift register unit and circuit with a similar configuration but does not teach the configuration of the circuit components and nodes as claimed.
Additional prior art of Zhichong (CN 106971692 A) teaches a drive circuit but does not teach recited circuit configuration with the control nodes connected to the input and output circuit as claimed.
In addition, no other prior art was found which teaches, alone or in combination, the cited limitations.
As to dependent claims 12-20, these claims are allowable as they depend upon allowable independent claim 11.
Any comments considered necessary by applicant must be submitted no later than the payment of the issue fee and, to avoid processing delays, should preferably accompany the issue fee. Such submissions should be clearly labeled “Comments on Statement of Reasons for Allowance.”
Conclusion
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/BRENT D CASTIAUX/Primary Examiner, Art Unit 2623