Notice of Pre-AIA or AIA Status
1. The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
2. Claims 1-21 are pending.
Claim Rejections - 35 USC § 102
3. In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1-3, 6-7, 12, 14 and 19 is/are rejected under 35 U.S.C. 102a1 as being anticipated by Jun et al. (US Patent Application 2024/0138219), herein after referred to as Jun.
Regarding independent claim 1, Jun discloses an electronic device (Figures 1A-1B 100), comprising:
a sensor (11 and/or 12 as described in paragraph [0071]); and
a display (110) comprising pixels (SPCG) (Figures 3, 6, and 10-13 depict pixel circuits SPC which can be arranged as a pixel circuit group SPCG (figure 11 SPCG1, figure 12 SPCG2, and figure 13 SPCG3) comprising TFTs arranged to control red, green, and blue LEDs as described in paragraph [0336]. Herein after generically pixels will be referred to as SPCG.), wherein:
the pixels (SPCG1) comprise subpixels (SPC_R1, SPC_G1, and SPC_B1 as described in paragraph [0337], herein after subpixels in general will be referred to as SPC);
the subpixels (SPC) comprise emissive subpixels that emit light (Figures 11-12 (specific reference numerals regard figure 11) and paragraph [0335] describes SPC_R1 to comprise ED_R1a and ED_R1b, SPC_G1 to comprise ED_G1a through ED_G1d, and SPC_B1 to comprise ED_B1a and ED_B1b, wherein ED is a light emitting element of the subpixel SPC. Herein after emissive subpixels in general will be referred to as ED.) and thin-film transistor subpixels that control the emissive sub-pixels (ED) (Figures 3 and 11-12 (specific reference numerals regard figure 11) depict the pixel circuit SPC comprising a plurality of transistors TFTs including a driving transistor DT described in paragraphs [0147]-[0149] to drive/control the light emitting element ED (in the light emissive sub-pixel area EA). Figure 11 depicts each subpixel SPC_R1, SPC_G1, and SPC_B1 each comprise their own respective driving TFT DT_R1, DR_G1, and DT_B1 that are directly connected to their own emissive sub-pixels ED_R1, ED_G1, and ED_B1. Herein after each thin-film transistor subpixel in general is referred to as SPC_RGB.);
the emissive subpixels (ED) are arranged in a regular grid of rows and columns (Figures 4-5 depicts EA to be arranged in rows and columns as described in paragraph [0206]. Paragraph [0114] describes the rows and columns to be arranged in accordance with data lines DL and gate lines GL of the pixel circuits (figure 2).);
the display (Figures 1A-1B and 4 100) has a first portion (OA1+OB1) that overlaps the sensor (11) ([0078] OA1 overlaps sensor 11) and a second portion (NA) that does not overlap the sensor (11) ([0078] NA doesn’t overlap 11);
the first portion (OA1+OB1) comprises a plurality of subpixel groups (SPCG1+SPCG2) that each include at least one subpixel (SPC) (Figures 11-12 depicts subpixel groups SPCG1 and SPCG2 each comprising a plurality of portions corresponding to the emission subpixels ED (emission groups EDG1 and EDG2) disposed in optical area/first portion OA1 as described in paragraphs [0335] and [0338].);
each one of the plurality of subpixel groups (SPCG1+SPCG2) in the first portion (OA1+OB1) comprises a thin-film transistor subpixel (SPC_RGB) that controls two or more emissive subpixels (ED) (Figures 3 and 11 (specific reference numerals regard figure 11) depict the pixel circuit SPC comprising a plurality of transistors TFTs including a driving transistor DT described in paragraphs [0147]-[0149] to drive/control the light emitting element ED. Figure 11 depicts each subpixel SPC_R1, SPC_G1, and SPC_B1 each comprise their own respective driving TFT DT_R1, DR_G1, and DT_B1 that are directly connected to their own two or more emissive sub-pixels ED_R1, ED_G1, and ED_B1.);
a total number of emissive subpixels (ED) per unit area is lower in the first portion (OA1+OB1) than in the second portion (NA) (Paragraphs [0090] and [0092] describes the number of pixels, measured as pixels per square inch PPI, in OA1 is lower than the number of pixels in NA.); and
the emissive subpixels (ED) in the subpixel groups (SPCG1+SPCG2) are part of the regular grid of rows and columns (Figures 11-12 each depict SPCG1+SPCG2 to each comprise a driving transistor DT depicted in figure 3 to be connected, via ST, to data lines DL and gate lines GL in which the regular grid of rows and columns are arranged.).
Regarding claim 2, Jun discloses the electronic device defined in claim 1, wherein (Figures 10-12) the thin-film transistor subpixel (SPC_RGB) that controls two or more emissive subpixels (ED) controls two or more emissive subpixels of a same color (SPC_R depicted to control ED_Ra+ED_Rb, SPC_G depicted to control ED_Ga through ED_Gd, and SPC_B depicted to control ED_Ba+ED_Bb as described in paragraphs [0335]-[0340].).
Regarding claim 3, Jun discloses the electronic device defined in claim 1, wherein (Figures 10-12) the thin-film transistor subpixel (SPC_RGB) is a first thin-film transistor subpixel (SPC_B1 and SPC_B2) that controls two blue emissive subpixels (SPC_B1: ED_B1a+ED_B1b and SPC_B2: ED_B2a+ED_B2b) and wherein each one of the plurality of subpixel groups (SPCG1+SPCG2) in the first portion (OA1) comprises a second thin-film transistor subpixel (SPC_R1 and SPC_R2) that controls two red emissive subpixels (SPC_R1: ED_R1a+ED_R1b and SPC_R2: ED_R2a+ED_R2b).
Regarding claim 6, Jun discloses the electronic device defined in claim 3, wherein (Figures 10-12) each one of the plurality of subpixel groups (SPCG1+SPCG2) in the first portion (OA1+OB1) comprises a third thin-film transistor subpixel (SPC_G1 and SPC_G2) that controls three green emissive subpixels (SPC_G1: ED_G1a through ED_G1d and SPC_G2: ED_G2a through ED_G2d).
Regarding claim 7, Jun discloses the electronic device defined in claim 3, wherein (Figures 10-12) each one of the plurality of subpixel groups (SPCG1+SPCG2) in the first portion (OA1+OB1) comprises a third thin-film transistor subpixel (SPC_G1 and SPC_G2) that controls two green emissive subpixels (SPC_G1: ED_G1a through ED_G1d and SPC_G2: ED_G2a through ED_G2d).
Regarding claim 12, Jun discloses the electronic device defined in claim 1, wherein (Figures 10-12) each one of the plurality of subpixel groups (SPCG1+SPCG2) comprises seven emissive subpixels (ED) (Figures 11-12 depicts 8 ED, which includes seven, including ED_R1a, ED_R1b, ED_G1a, ED_G1b, ED_G1c, ED_G1d, ED_B1a, and ED_B1b. Paragraph [0335] notes that the group may include N light emitting element wherein N is greater than 2 and relates to the ratio of 1:N of paragraphs [0214]-[0215] regarding the number of driving transistors.).
Regarding claim 14, Jun discloses the electronic device defined in claim 12, wherein (Figures 10-12) each one of the plurality of subpixel groups (SPCG1+SPCG2) comprises three total thin-film transistor subpixels (SPC_R1, SPC_G1, SPC_B1).
Regarding independent claim 19, Jun discloses an electronic device (Figures 1A-1B 100), comprising:
a sensor (11 and/or 12 as described in paragraph [0071]); and
a display (110) comprising subpixels (SPC) (Figures 3, 6, and 10-13 depict pixel circuits SPC which can be arranged as a pixel circuit group SPCG (figure 11 SPCG1, figure 12 SPCG2, and figure 13 SPCG3) comprising TFTs arranged to control red, green, and blue LEDs as described in paragraph [0336]. Paragraph [0337] describes the pixels SPCG to comprise subpixels SPC_R1, SPC_G1, and SPC_B1, herein after subpixels in general will be referred to as SPC)), wherein:
the subpixels (SPC) comprise emissive subpixels that emit light (Figures 11-12 (specific reference numerals regard figure 11) and paragraph [0335] describes SPC_R1 to comprise ED_R1a and ED_R1b, SPC_G1 to comprise ED_G1a through ED_G1d, and SPC_B1 to comprise ED_B1a and ED_B1b, wherein ED is a light emitting element of the subpixel SPC. Herein after emissive subpixels in general will be referred to as ED.) and thin-film transistor subpixels that control the emissive sub-pixels (EA) (Figures 3 and 11-12 (specific reference numerals regard figure 11) depict the pixel circuit SPC comprising a plurality of transistors TFTs including a driving transistor DT described in paragraphs [0147]-[0149] to drive/control the light emitting element ED (in the light emissive sub-pixel area EA). Figure 11 depicts each subpixel SPC_R1, SPC_G1, and SPC_B1 each comprise their own respective driving TFT DT_R1, DR_G1, and DT_B1 that are directly connected to their own emissive sub-pixels ED_R1, ED_G1, and ED_B1. Herein after each thin-film transistor subpixel in general is referred to as SPC_RGB.);
the emissive subpixels (ED) are arranged in a regular grid of rows and columns (Figures 4-5 depicts EA to be arranged in rows and columns as described in paragraph [0206]. Paragraph [0114] describes the rows and columns to be arranged in accordance with data lines DL and gate lines GL of the pixel circuits (figure 2).);
the display (Figures 1A-1B and 4 100) has a first portion (OA1+OB1) that overlaps the sensor (11) ([0078] OA1 overlaps sensor 11) and a second portion (NA) that does not overlap the sensor (11) ([0078] NA doesn’t overlap 11);
the first portion (OA1+OB1) comprises a plurality of subpixel groups (SPCG1+SPCG2) that each include a first thin-film transistor (DT_R1 and DT_R2) subpixel (SPC_R1 and SPC_R2) that controls two red emissive subpixels (ED_R1a+ ED_R1b and ED_R2a+ED_R2b), a second thin-film transistor (DT_B1 and DT_B2) subpixel (SPC_B1 and SPC_B2) that controls two blue emissive subpixels (ED_B1a+ ED_B1b and ED_B2a+ED_B2b), and a third thin-film transistor (DT_G1 and DT_G2) subpixel that controls three green emissive subpixels (ED_G1a+ ED_G1b+ED_G1c and ED_G2a+ED_G2b+ED_G2c);
a total number of emissive subpixels (ED) per unit area is lower in the first portion (OA1+OB1) than in the second portion (NA) (Paragraphs [0090] and [0092] describes the number of pixels, measured as pixels per square inch PPI, in OA1 is lower than the number of pixels in NA.); and the emissive subpixels (ED) in the subpixel groups (SPCG1+SPCG2) are part of the regular grid of rows and columns (Figures 11-12 each depict SPCG1+SPCG2 to each comprise a driving transistor DT depicted in figure 3 to be connected, via ST, to data lines DL and gate lines GL in which the regular grid of rows and columns are arranged.).
Claim Rejections - 35 USC § 103
4. The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 4-5 and 13 is/are rejected under 35 U.S.C. 103 as being obvious over Jun.
Regarding claim 4, Jun discloses the electronic device defined in claim 3, wherein (Figures 10-12) each one of the plurality of subpixel groups (SPCG1 and SPCG2) in the first portion (OA1) comprises a third thin-film transistor subpixel (SPC_G1 and SPC_G2) that controls a first green emissive subpixel (SPC_G1: ED_G1a and SPC_G2: ED_G2a), a fourth thin-film transistor subpixel that controls a second green emissive subpixel, and a fifth thin-film transistor subpixel that controls a third green emissive subpixel.
Jun discloses a single thin-film transistor subpixel (Figures 11-12: SPC_G1 and SPC_G2) to control a first green emissive subpixel (ED_G1a and ED_G2a), second green emissive subpixel (ED_G1b and ED_G2b), and third green emissive subpixel (ED_G1c and ED_G2c). However, Jun does not specifically disclose one of the plurality of subpixel groups in the first portion comprises a third thin-film transistor subpixel that controls a first green emissive subpixel, a fourth thin-film transistor subpixel that controls a second green emissive subpixel, and a fifth thin-film transistor subpixel that controls a third green emissive subpixel.
Jun does disclose wherein a TFT subpixel may be connected to a emissive subpixel in a 1:1 fashion (Figure 5 and paragraph [0186]) or a single TFT emissive subpixel may be connected to a plurality of emissive subpixels as a 1:N ratio (Figure 6 paragraphs [0214]-[0216].).
It would have been obvious to one skilled in the art before the effective filing date of the current application to enable Jun’s figures 11-12 green emissive subpixels ED_G with the known technique of a third thin-film transistor subpixel that controls a first green emissive subpixel, a fourth thin-film transistor subpixel that controls a second green emissive subpixel, and a fifth thin-film transistor subpixel that controls a third green emissive subpixel yielding the predictable results of maintaining transmittance in the optical area without being reduced (paragraphs [0189]-[0190]) and increasing individualized control of each emissive element (each subpixel controlled by its own DT) as disclosed by Jun.
Regarding claim 5, Jun discloses the electronic device defined in claim 3, wherein (Figures 10-12) each one of the plurality of subpixel groups (SPCG1+SPCG2) in the first portion (OA1) comprises a third thin-film transistor subpixel (SPC_G1 and SPC_G2) that controls a first green emissive subpixel (SPC_G1: ED_G1a and SPC_G2: ED_G2a) and [ ] that controls a second green emissive subpixel (SPC_G1: ED_G1b and SPC_G2: ED_G2b).
Jun does not specifically disclose a fourth thin-film transistor subpixel that controls a second green emissive subpixel.
Jun does disclose wherein a TFT subpixel may be connected to a emissive subpixel in a 1:1 fashion (Figure 5 and paragraph [0186]) or a single TFT emissive subpixel may be connected to a plurality of emissive subpixels as a 1:N ratio (Figure 6 paragraphs [0214]-[0216].).
It would have been obvious to one skilled in the art before the effective filing date of the current application to enable Jun’s figures 11-12 green emissive subpixels ED_G with the known technique of a third thin-film transistor subpixel that controls a first green emissive subpixel and a fourth thin-film transistor subpixel that controls a second green emissive subpixel yielding the predictable results of maintaining transmittance in the optical area without being reduced (paragraphs [0189]-[0190]) and increasing individualized control of each emissive element (each subpixel controlled by its own DT) as disclosed by Jun.
Regarding claim 13, Jun discloses the electronic device defined in claim 12, wherein (Figures 10-12) each one of the plurality of subpixel groups (SPCG1+SPCG2) comprises three total thin-film transistor subpixels (SPC_R1, SPC_G1, SPC_B1).
Jun does not specifically disclose wherein each one of the plurality of subpixel groups comprises five total thin-film transistor subpixels.
Jun does disclose wherein a TFT subpixel may be connected to a emissive subpixel in a 1:1 fashion (Figure 5 and paragraph [0186]) or a single TFT emissive subpixel may be connected to a plurality of emissive subpixels as a 1:N ratio (Figure 6 paragraphs [0214]-[0216].).
It would have been obvious to one skilled in the art before the effective filing date of the current application to enable Jun’s plurality of subpixel groups with the known technique of comprising three total thin0film transistor subpixels yielding the predictable results of maintaining transmittance in the optical area without being reduced (paragraphs [0189]-[0190]) and increasing individualized control of each emissive element (each subpixel controlled by its own DT) as disclosed by Jun.
5. Claim(s) 8-11 and 21 is/are rejected under 35 U.S.C. 103 as being obvious over Jun in view of Credelle (US Patent Application Publication 2005/0083277).
Regarding claim 8, Jun discloses the electronic device defined in claim 1.
Jun does not specifically disclose wherein the plurality of subpixel groups is arranged in a checkerboard layout and wherein each one of the plurality of subpixel groups has emissive subpixels in a same layout.
Credelle discloses wherein (Figure 2) the plurality of subpixel groups (202) is arranged in a checkerboard layout (paragraph [0017]) and wherein each one of the plurality of subpixel groups (202) has emissive subpixels (104, 106, 108) in a same layout (Figure 2 depicts 104, 106, 108 in the same layout for each grouping 202 of the checkboard arrangement.).
It would have been obvious to one skilled in the art before the effective filing date of the current application to enable Jun’s subpixel groups with the known technique of being arranged in a checkerboard layout and wherein each one of the plurality of subpixel groups has emissive subpixels in a same layout yielding the predictable results of preventing visual degradation of the display as disclosed by Credelle (paragraph [0017]).
Regarding claim 9, Jun discloses the electronic device defined in claim 1.
Jun does not specifically disclose wherein the plurality of subpixel groups is arranged in a checkerboard layout, wherein the plurality of subpixel groups comprises a first subset and a second subset, wherein each one of the first subset of the plurality of subpixel groups has emissive subpixels in a first layout, and wherein each one of the second subset of the plurality of subpixel groups has emissive subpixels in a second layout that is different than the first layout.
Credelle discloses wherein the plurality of subpixel groups (Figure 2 specifically a single row comprising four subpixels including a single red 104, single blue 108, and two green 106 subpixels. This interpretation does not utilize the grouping of 202.) is arranged in a checkerboard layout (paragraph [0017]), wherein the plurality of subpixel groups (single row of four pixels) comprises a first subset (odd rows) and a second subset (even rows), wherein each one of the first subset (odd rows) of the plurality of subpixel groups (single row of four pixels) has emissive subpixels in a first layout (rows 1 and 3: RGBG), and wherein each one of the second subset (even rows) of the plurality of subpixel groups (single row of four pixels) has emissive subpixels in a second layout (BGRB) that is different than the first layout (RGBG) (figure 2 RGBG is different from BGRB).
It would have been obvious to one skilled in the art before the effective filing date of the current application to enable Jun’s subpixel groups with the known technique of being arranged in a checkerboard layout wherein the plurality of subpixel groups comprises a first subset and a second subset, wherein each one of the first subset of the plurality of subpixel groups has emissive subpixels in a first layout, and wherein each one of the second subset of the plurality of subpixel groups has emissive subpixels in a second layout that is different than the first layout yielding the predictable results of preventing visual degradation of the display as disclosed by Credelle (paragraph [0017]).
Regarding claim 10, Credelle discloses the electronic device defined in claim 9, wherein blue emissive subpixels (Figure 2 108) in the first layout (RGBG) are changed to red emissive subpixels (104) in the second layout (BGRG) and wherein red emissive subpixels (104) in the first layout (RGBG) are changed to blue emissive subpixels (108) in the second layout (BGRG) (Figure 2 First layout: RGBG second layout: BGRG depicts a change between the red and blue subpixels in the four subpixel grouping.).
Regarding claim 11, Credelle discloses the electronic device defined in claim 9, wherein the first subset (Figure 2 odd Rows) of the plurality of subpixel groups (single row of four pixels) comprises every other row of subpixel groups in the checkerboard layout (figure 2 only odd rows) and wherein the second subset (even rows) of the plurality of subpixel groups (single row of four pixels) comprises remaining rows of subpixel groups in the checkerboard layout (only even rows).
Regarding independent claim 21, Jun discloses an electronic device (Figures 1A-1B 100), comprising:
a sensor (11 and/or 12 as described in paragraph [0071]); and
a display (110) comprising subpixels (SPC) (Figures 3, 6, and 10-13 depict pixel circuits SPC which can be arranged as a pixel circuit group SPCG (figure 11 SPCG1, figure 12 SPCG2, and figure 13 SPCG3) comprising TFTs arranged to control red, green, and blue LEDs as described in paragraph [0336]. SPC_R1, SPC_G1, and SPC_B1 as described in paragraph [0337], herein after subpixels in general will be referred to as SPC), wherein:
the subpixels (SPC) comprise emissive subpixels that emit light (Figures 11-12 (specific reference numerals regard figure 11) and paragraph [0335] describes SPC_R1 to comprise ED_R1a and ED_R1b, SPC_G1 to comprise ED_G1a through ED_G1d, and SPC_B1 to comprise ED_B1a and ED_B1b, wherein ED is a light emitting element of the subpixel SPC. Herein after emissive subpixels in general will be referred to as ED.) and thin-film transistor subpixels that control the emissive sub-pixels (ED) (Figures 3 and 11-12 (specific reference numerals regard figure 11) depict the pixel circuit SPC comprising a plurality of transistors TFTs including a driving transistor DT described in paragraphs [0147]-[0149] to drive/control the light emitting element ED (in the light emissive sub-pixel area EA). Figure 11 depicts each subpixel SPC_R1, SPC_G1, and SPC_B1 each comprise their own respective driving TFT DT_R1, DR_G1, and DT_B1 that are directly connected to their own emissive sub-pixels ED_R1, ED_G1, and ED_B1. Herein after each thin-film transistor subpixel in general is referred to as SPC_RGB.);
the emissive subpixels (ED) are arranged in a regular grid of rows and columns (Figures 4-5 depicts EA to be arranged in rows and columns as described in paragraph [0206]. Paragraph [0114] describes the rows and columns to be arranged in accordance with data lines DL and gate lines GL of the pixel circuits (figure 2).);
the display (Figures 1A-1B and 4 100) has a first portion (OA1+OB1) that overlaps the sensor (11) ([0078] OA1 overlaps sensor 11) and a second portion (NA) that does not overlap the sensor (11) ([0078] NA doesn’t overlap 11);
the first portion (OA1+OB1) comprises a plurality of subpixel groups (SPCG1+SPCG2) that are arranged in a [ ] layout, wherein no unoccupied rows of subpixels (SPC) are interposed between adjacent rows of subpixel groups (SPCG1+SPCG2) in the [ ] layout and wherein no unoccupied columns of subpixels (SPC) are interposed between adjacent columns of subpixel groups (SPCG1+SPCG2) in the [ ] layout (Figures 2-3 depict no unoccupied rows or columns of subpixels SPC.);
a total number of emissive subpixels (ED) per unit area is lower in the first portion (OA1+OB1) than in the second portion (NA) (Paragraphs [0090] and [0092] describes the number of pixels, measured as pixels per square inch PPI, in OA1 is lower than the number of pixels in NA.); and
the emissive subpixels (ED) in the subpixel groups (SPCG1+SPCG2) are part of the regular grid of rows and columns (Figures 11-12 each depict SPCG1+SPCG2 to each comprise a driving transistor DT depicted in figure 3 to be connected, via ST, to data lines DL and gate lines GL in which the regular grid of rows and columns are arranged.).
Jun does not specifically disclose the layout is a checkboard layout.
Credelle discloses a portion (Figure 2) comprises a plurality of subpixel groups (202) that are arranged in a checkerboard layout (paragraph [0017]), wherein no unoccupied rows of subpixels are interposed between adjacent rows of subpixel groups in the checkerboard layout and wherein no unoccupied columns of subpixels are interposed between adjacent columns of subpixel groups in the checkerboard layout (Figure 2 depicts no unoccupied rows or columns of subpixels.).
It would have been obvious to one skilled in the art before the effective filing date of the current application to enable Jun’s subpixel groups with the known technique of a plurality of subpixel groups that are arranged in a checkerboard layout, wherein no unoccupied rows of subpixels are interposed between adjacent rows of subpixel groups in the checkerboard layout and wherein no unoccupied columns of subpixels are interposed between adjacent columns of subpixel groups in the checkerboard layout yielding the predictable results of preventing visual degradation of the display as disclosed by Credelle (paragraph [0017]).
6. Claim(s) 15 and 17-18 is/are rejected under 35 U.S.C. 103 as being obvious over Jun in view of Qui et al. (US Patent Application Publication 2024/0321178), herein after referred to as Qui’178.
Regarding claim 15, Jun discloses the electronic device defined in claim 1, wherein the display (Figures 2 and 3 110) comprises: a plurality of signal lines (DL+GL+ELVDD) that provide signals ([0113]) to thin-film transistor subpixels (SPC) in the second portion (Figures 10-12 NA) of the display (110), wherein the plurality of signal lines (DL+GL+ELVDD) comprises a first subset that also provides signals to thin-film transistor subpixels in the first portion (OA1+OB1) of the display (Figures 2-3 depict the data line DL and gate lines GL provide signals across the entire column or row including both area NA and OA1+OB1.), and [ ].
Jun does not specifically disclose wherein the plurality of signal lines comprises a second subset that is aligned with the first portion of the display but do not provide signals to any thin-film transistor subpixels in the first portion of the display.
Qui’178 discloses, wherein the display (Figures 1 and 8 and paragraph [0050]) comprises: a plurality of signal lines (1+4) that provide signals ([0057]) to thin-film transistor subpixels (figure 8 pixel circuits A11-A2n (in BB) and 3 (in AA2); with pixel circuit detailed in figure 3) in the second portion (AA2) of the display (figure 1), wherein the plurality of signal lines (1+4) comprises a first subset (1) that also provides signals ([0069]) to thin-film transistor subpixels (A11-A2n) in the first portion (AA1+BB) of the display, and wherein the plurality of signal lines (1+4) comprises a second subset (4) that is aligned (Figure 8 depicts 1 and 4 aligned) with the first portion (AA1+BB) of the display but do not provide signals to any thin-film transistor subpixels (A11-A2n) in the first portion (AA1+BB) of the display (Figure 8 and paragraph [0057] describes control lines 1 to only provide signals to pixel circuits A11-A2n that control emission subpixels EL11-EL2N in area AA1 (that is over the camera area as described in paragraph [0050]). Control lines 4 provide signals to pixel circuits 3 only in area AA2 that also comprise their emission subpixels 5.).
It would have been obvious to one skilled in the art before the effective filing date of the current application to enable Jun’s signal lines with the known technique of comprising a second subset that is aligned with the first portion of the display but do not provide signals to any thin-film transistor subpixels in the first portion of the display yielding the predictable results of sharing a first drive circuit without reducing the transmittance of the area over the sensor as disclosed by Qui’178 (paragraphs [0050] and [0066]).
Regarding claim 17, Qui’178 discloses the electronic device defined in claim 15, wherein the second subset (Figure 8 control line 4) of the plurality of signal lines (1+4) is routed around the first portion (AA1) of the display (Figure 8 depicts control lines 4 are not routed through AA1 and therefore considered to be routed around.).
Regarding claim 18, Jun discloses the electronic device defined in claim 1.
Jun does not specifically disclose wherein each one of the plurality of subpixel groups in the first portion comprises at least one dummy subpixel.
Qui’178 discloses wherein each one of the plurality of subpixel groups in the first portion comprises at least one dummy subpixel.
It would have been obvious to one skilled in the art before the effective filing date of the current application to enable Jun with the known technique of wherein each one of the plurality of subpixel groups in the first portion comprises at least one dummy subpixel yielding the predictable results of uniformity of the display picture as disclosed by Qui’178 (paragraph [0099]).
7. Claim(s) 16 is/are rejected under 35 U.S.C. 103 as being obvious over Jun-Qui’178 in view of Qui et al. (US Patent Application Publication 2022/0123094), herein after referred to as Qui’094.
Regarding claim 16, Jun and Qui discloses the electronic device defined in claim 15,
However, neither Jun or Qui’178 disclose wherein the second subset of the plurality of signal lines is routed through the first portion of the display.
Qui’094 discloses wherein the second subset (Figure 5 signal lines 171/172) of the plurality of signal lines (171+161+181) is routed through the first portion (10) of the display (Figure 3A depicts area 10 to correspond to a display area over a sensor, paragraph [0062].).
It would have been obvious to one skilled in the art before the effective filing date of the current application to enable Jun-Qui’178 second subset of the plurality of signal lines with the known technique of being routed through the first portion of the display yielding the predictable results of reducing the wiring space and ensure light transmittance of the first portion 10 as disclosed by Qui’094 (paragraph [0083]).
8. Claim(s) 20 is/are rejected under 35 U.S.C. 103 as being obvious over Jun in view of Lahav et al. (US Patent Application Publication 2008/0062290), herein after referred to as Lahav.
Regarding claim 20, Jun discloses the electronic device defined in claim 19.
Jun does not specifically disclose wherein each subpixel group comprises four rows of subpixels and five columns of subpixels.
Lahav discloses wherein each subpixel group comprises four rows of subpixels and five columns of subpixels (Figure 16 and paragraph [0014]).
It would have been obvious to one skilled in the art before the effective filing date of the current application to enable Jun’s subpixel group with the known technique of wherein each subpixel group comprises four rows of subpixels and five columns of subpixels yielding the predictable results of arranging the pixels in a Bayer Pattern for simplest demosaicing algorithm for imaging sensors as disclosed by Lahav (paragraph [0015]).
Conclusion
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/CHRISTOPHER E LEIBY/Primary Examiner, Art Unit 2621
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