Notice of Pre-AIA or AIA Status
1. The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
2. Claims 1-3, 5, 7, 9-12, 15-26 are pending. Bolded claim language below regards newly amended subject matter with a corresponding new rejection citation. Newly amended subject matter that is not bolded does not comprise a new rejection citation (utilizes previous interpretation that is unchanged in view of the new language) or is a newly added claim.
Response to Argument
3. Applicant's arguments filed 7/13/2026 have been fully considered and relate towards newly amended subject matter with exceptions noted below. In regards to arguments pertaining towards newly amended subject matter please refer to the below office action utilizing newly cited art Nam, Zhao, and Lim as rebuttal.
In regards to the argument, page 15, that Jun does not disclose signals lines DL, GL, and ELVDD to provide signals to TFTs in OA1. Please note the interpretation taken by the office action is the first portion is OA1+OBA1. Arguing that Jun does not provide signals to OA1 implies that OA1 is singularly utilized in the interpretation of the claimed first portion. Said argument is moot in view of OA1+OBA1 utilized in the interpretation of the claimed first portion. Secondly, OBA1 (part of the first portion) is depicted in figure 5 to directly receive ELVDD to DT. Figure 3 and paragraph [0153] describes transistor ST to directly receive data signal from data line DL and scan signal from gate line GL. Paragraph [0208] specifically describes that scan transistor ST and storage capacitor Cst is omitted from figure 5 for convenience of description. This describes figures 5-6 pixels SP to include ST (and directly connected lines DL and GL) even though they are not depicted.
Further, in view of previously claimed subject matter of claim 18 is newly amended into independent claim 19. Said subject matter states that each subpixel group in the first portion comprises at least one dummy subpixel. Support for the subject matter is found in figure 23 of the current application. Said figure identifies dummy pixels as B-D, G-D, and R-D and pixel groups as 102. Dummy pixels are defined by the specification as subpixels which do not emit light and may be referred to as non-functional ([0145]). Reference numeral 102 is a mental practice of grouping pixels which emit light via transistors (figure 24A-24B 404) in the sensor area (claimed first portion).
Beyond the original claim 18 language, the words “group” (and any iteration thereof) is not found within the same paragraph as “dummy”. This supports the interpretation that the subpixels which emit light (in figure 23) can be considered grouped with pixels that do not emit light simply because they are physically located directly adjacent. Therefore, a mental practice of a bounding box surrounding a group of pixels that emit light in the sensor area (first portion) may include some dummy pixels so as to continue the same grid like pattern found in the main display/second portion ([0146]).
The interview filed 5/29/2026 originally stated that it is agreed that secondary art Qiu’178 figure 15 dummy pixels 300 are not found in the first portion identified as Aa1 warranting further search and consideration and that this is not an agreement of allowability. However, after further consideration in view of the above interpretation, the claim language does define how the subpixel groups comprise dummy pixels. Additionally, a mental practice of grouping pixels comprises a broad scope of interpretation. The implied limited scope of interpretation described by the specification (directly adjacent inside of the first portion) is not claimed.
In re Prater, 415 F.2d 1393, 1404-05, 162 USPQ 541, 550-51 (CCPA 1969) (MPEP 2111 Claim interpretation; BRI) the court explained that “reading a claim in light of the specification, to thereby interpret limitations explicitly recited in the claim, is a quite different thing from ‘reading limitations of the specification into a claim,’ to thereby narrow the scope of the claim by implicitly adding disclosed limitations which have no express basis in the claim.
Since the claim does not limit how a pixel can comprise a dummy pixel and in light of the specification the “comprising” is a mental practice Qiu is still found to disclose the subject matter. Please note that Claim 18 rejection is maintained and newly amended subject matter to independent claim 19 is newly presented in view of a scope leading towards pixel arrangement (claim 20) that is different as compared to independent claim 1. Therefore, the newly presented subject matter to claim 19 necessitates further search and consideration.
Newly cited art Zhao is found to disclose the subject matter limited in scope to the unclaimed limitations of the current application and is applied in combination with Jun to reject the subject matter of claim 19. It should be noted that paragraph [0177] of the current application specifically states that dummy pixels, as described in connection with figure 23, may be utilized with any display embodiments described in the specification.
This action is final necessitated by amendment.
Claim Rejections - 35 USC § 103
4. In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1-3, 5, 7, 12, and 15-17 is/are rejected under 35 U.S.C. 103 as being unpatentable over Jun et al. (US Patent Application 2024/0138219), herein after referred to as Jun, in view of Nam et al. (US Patent Application Publication 2025/0324872), herein after referred to as Nam.
Regarding independent claim 1, Jun discloses an electronic device (Figures 1A-1B 100), comprising:
a sensor (11 and/or 12 as described in paragraph [0071]); and
a display (110) that emits light in a direction (Z) (Figure 1A depicts front view with two dimensions, X vertical and Y vertical. The side view depicts the emission Z direction and vertical Y directions, [0111], herein after referred to as Z.), wherein the display comprises pixels (SPCG) (Figures 3, 6, and 10-13 depict pixel circuits SP which can be arranged as a pixel circuit group SPCG (figure 11 SPCG1, figure 12 SPCG2, and figure 13 SPCG3) comprising TFTs arranged to control red, green, and blue LEDs as described in paragraph [0336]. Herein after generically pixels will be referred to as SPCG.) and a plurality of signal lines (DL+GL+DVL) that provide signals (image, scan, and driving signals) to the pixels (SPCG) (Figures 2 and 3 depict data lines DL, gate lines GL, driving voltage line DVL described in paragraphs [0113]-[0114] and [0148] to respectively provide signals including data voltage/image signal, scan signals, and driving voltage to the pixels SP.) and wherein:
the pixels (SPCG1) comprise subpixels (SPC_R1, SPC_G1, and SPC_B1 as described in paragraph [0337], herein after subpixels in general will be referred to as SPC);
the subpixels (SPC) comprise emissive subpixels that emit light (Figures 11-12 (specific reference numerals regard figure 11) and paragraph [0335] describes SPC_R1 to comprise ED_R1a and ED_R1b, SPC_G1 to comprise ED_G1a through ED_G1d, and SPC_B1 to comprise ED_B1a and ED_B1b, wherein ED is a light emitting element of the subpixel SPC. Herein after emissive subpixels in general will be referred to as ED.) and thin-film transistor subpixels that control the emissive sub-pixels (ED) (Figures 3 and 11-12 (specific reference numerals regard figure 11) depict the pixel circuit SPC comprising a plurality of transistors TFTs including a driving transistor DT described in paragraphs [0147]-[0149] to drive/control the light emitting element ED (in the light emissive sub-pixel area EA). Figure 11 depicts each subpixel SPC_R1, SPC_G1, and SPC_B1 each comprise their own respective driving TFT DT_R1, DR_G1, and DT_B1 that are directly connected to their own emissive sub-pixels ED_R1, ED_G1, and ED_B1. Herein after each thin-film transistor subpixel in general is referred to as SPC_RGB.);
the emissive subpixels (ED) are arranged in a regular grid of rows and columns (Figures 4-5 depicts EA to be arranged in rows and columns as described in paragraph [0206]. Paragraph [0114] describes the rows and columns to be arranged in accordance with data lines DL and gate lines GL of the pixel circuits (figure 2).);
the display (Figures 1A-1B and 4 100) has a first portion (OA1+OB1) that overlaps the sensor (11) ([0078] OA1 overlaps sensor 11) in the direction (Z) and a second portion (NA) that does not overlap the sensor (11) ([0078] NA doesn’t overlap 11) in the direction (Z);
the first portion (OA1+OB1) comprises a plurality of subpixel groups (SPCG1+SPCG2) that each include at least one subpixel (SPC) (Figures 11-12 depicts subpixel groups SPCG1 and SPCG2 each comprising a plurality of portions corresponding to the emission subpixels ED (emission groups EDG1 and EDG2) disposed in optical area/first portion OA1 as described in paragraphs [0335] and [0338].);
each one of the plurality of subpixel groups (SPCG1+SPCG2) in the first portion (OA1+OB1) comprises a thin-film transistor subpixel (SPC_RGB) that controls two or more emissive subpixels (ED) (Figures 3 and 11 (specific reference numerals regard figure 11) depict the pixel circuit SPC comprising a plurality of transistors TFTs including a driving transistor DT described in paragraphs [0147]-[0149] to drive/control the light emitting element ED. Figure 11 depicts each subpixel SPC_R1, SPC_G1, and SPC_B1 each comprise their own respective driving TFT DT_R1, DR_G1, and DT_B1 that are directly connected to their own two or more emissive sub-pixels ED_R1, ED_G1, and ED_B1.);
the plurality of signal lines (DL+GL+DVL) comprises a first subset (SPC1, SPC2, and SPC4) with first signal lines (DL+GL+DVL) that provide the signals (image, scan, and driving signals) to thin-film transistor (ST+DT) subpixels (SPC1, SPC2, and SPC4) in the first (OA1+OB1) and second portions (NA) of the display (110) and a second subset (SPC3) with second signal lines (DL+GL+DVL) that provide signals (image, scan, and driving signals) to thin-film transistor (ST+DT) subpixels (SPC3) in the second portion (NA) of the display (110) (Figures 5 depicts an example of subpixel SP arrangement within the first portion OA1+OB1 and second portion NA in which signal lines DL+GL+DVL are arranged to apply signals to each subpixel, [0186]-[0187].);
[ ];
a total number of emissive subpixels (ED) per unit area is lower in the first portion (OA1+OB1) than in the second portion (NA) (Paragraphs [0090] and [0092] describes the number of pixels, measured as pixels per square inch PPI, in OA1 is lower than the number of pixels in NA.); and
the emissive subpixels (ED) in the subpixel groups (SPCG1+SPCG2) are part of the regular grid of rows and columns (Figures 11-12 each depict SPCG1+SPCG2 to each comprise a driving transistor DT depicted in figure 3 to be connected, via ST, to data lines DL and gate lines GL in which the regular grid of rows and columns are arranged.).
Jun does not specifically disclose that the second signal lines do not provide signals to any thin-film transistor subpixels in the first portion of the display.
Nam discloses the second signal lines (Figure 8 DL1) do not provide signals to any thin-film transistor subpixels (PG1-PG4) in the first portion (CA) of the display (Figure 8 second portion MDA comprises data first signal lines DL1 which is utilized in both MDA and first portion CA. Second data signal lines DL2 do not provide signals to any TFTs subpixels in the second portion CA by bypassing CA, [0169]. Figure 15 depicts substantially similar subject matter but in regards to gate lines GL, [0227]-[0228].).
It would have been obvious to one skilled in the art before the effective filing date of the current application to enable Jun’s data DL signal lines with the known technique of not providing signals to any thin-film transistor subpixels in the first portion of the display yielding the predictable results of improving light transmittance of the second portion (utilized for the camera) as disclosed by Nam ([0169] and [0070]-[0071]).
Regarding claim 2, Jun discloses the electronic device defined in claim 1, wherein (Figures 10-12) the thin-film transistor subpixel (SPC_RGB) that controls two or more emissive subpixels (ED) controls two or more emissive subpixels of a same color (SPC_R depicted to control ED_Ra+ED_Rb, SPC_G depicted to control ED_Ga through ED_Gd, and SPC_B depicted to control ED_Ba+ED_Bb as described in paragraphs [0335]-[0340].).
Regarding claim 3, Jun discloses the electronic device defined in claim 1, wherein (Figures 10-12) the thin-film transistor subpixel (SPC_RGB) is a first thin-film transistor subpixel (SPC_B1 and SPC_B2) that controls two blue emissive subpixels (SPC_B1: ED_B1a+ED_B1b and SPC_B2: ED_B2a+ED_B2b) and wherein each one of the plurality of subpixel groups (SPCG1+SPCG2) in the first portion (OA1) comprises a second thin-film transistor subpixel (SPC_R1 and SPC_R2) that controls two red emissive subpixels (SPC_R1: ED_R1a+ED_R1b and SPC_R2: ED_R2a+ED_R2b).
Regarding claim 5, Jun discloses the electronic device defined in claim 3, wherein (Figures 10-12) each one of the plurality of subpixel groups (SPCG1+SPCG2) in the first portion (OA1) comprises a third thin-film transistor subpixel (SPC_G1 and SPC_G2) that controls a first green emissive subpixel (SPC_G1: ED_G1a and SPC_G2: ED_G2a) and [ ] that controls a second green emissive subpixel (SPC_G1: ED_G1b and SPC_G2: ED_G2b).
Jun does not specifically disclose a fourth thin-film transistor subpixel that controls a second green emissive subpixel.
Jun does disclose wherein a TFT subpixel may be connected to a emissive subpixel in a 1:1 fashion (Figure 5 and paragraph [0186]) or a single TFT emissive subpixel may be connected to a plurality of emissive subpixels as a 1:N ratio (Figure 6 paragraphs [0214]-[0216].).
It would have been obvious to one skilled in the art before the effective filing date of the current application to enable Jun’s figures 11-12 green emissive subpixels ED_G with the known technique of a third thin-film transistor subpixel that controls a first green emissive subpixel and a fourth thin-film transistor subpixel that controls a second green emissive subpixel yielding the predictable results of maintaining transmittance in the optical area without being reduced (paragraphs [0189]-[0190]) and increasing individualized control of each emissive element (each subpixel controlled by its own DT) as disclosed by Jun.
Regarding claim 7, Jun discloses the electronic device defined in claim 3, wherein (Figures 10-12) each one of the plurality of subpixel groups (SPCG1+SPCG2) in the first portion (OA1+OB1) comprises a third thin-film transistor subpixel (SPC_G1 and SPC_G2) that controls two green emissive subpixels (SPC_G1: ED_G1a through ED_G1d and SPC_G2: ED_G2a through ED_G2d).
Regarding claim 12, Jun discloses the electronic device defined in claim 1, wherein (Figures 10-12) each one of the plurality of subpixel groups (SPCG1+SPCG2) comprises seven emissive subpixels (ED) (Figures 11-12 depicts 8 ED, which includes seven, including ED_R1a, ED_R1b, ED_G1a, ED_G1b, ED_G1c, ED_G1d, ED_B1a, and ED_B1b. Paragraph [0335] notes that the group may include N light emitting element wherein N is greater than 2 and relates to the ratio of 1:N of paragraphs [0214]-[0215] regarding the number of driving transistors.) and wherein each of the plurality of subpixel groups (figure 11 SPCG1 and/or figure 12 SPCG2) comprises three or five total thin-film transistor subpixel ([0213]-[0215] describes a single TFT may drive N light emitting elements ED with a ratio of 1:N with N= ED that is 2 or greater. Figures 11-12 depicts an example of 3 TFTs to drive 8 ED (which include 7).).
Regarding claim 15, Nam discloses the electronic device defined in claim 1, wherein at least one second signal line (Figure 8 DL1) is interposed between at least two first signal lines (DL2) (Figure 8 depicts CA to include areas AU1 and AU2 which utilize DL2 and bypassing DL1. Figure 9 depicts CA to additional include columns with areas AU3 and AU4, in correspondence with figure 8, depicting the DL1 of AU1 and AU2 to be interposed between the DL2 of AU1 and AU3.).
Regarding claim 16, Nam discloses the electronic device defined in claim 1, wherein the first signal lines (Figures 8-9 DL2) alternate with the second signal lines (DL1) (Figure 8 depicts CA to include areas AU1 and AU2 which utilize DL2 and bypassing DL1. Figure 9 depicts CA to additional include columns with areas AU3 and AU4. Figure 9, in correspondence with figure 8, depicts MDA DL2 of AU3 and AU4 to be interposed between the DL1 of AU1+AU2 and AU3+AU4.).
Regarding claim 17, Jun discloses the electronic device defined in claim 1, wherein at least one first signal line (Figures 8-9 DL2) is interposed between at least two second signal lines (DL1) (Figure 8 depicts CA to include areas AU1 and AU2 which utilize 3 data lines for DL2 and 5 data lines bypassing for DL1. Figure 9 depicts CA to additional include columns with areas AU3 and AU4. Figure 9, in correspondence with figure 8, depicts MDA DL2 of AU3 and AU4 to be interposed between the DL1 of AU1+AU2 and AU3+AU4.).
5. Claim(s) 9-11 and 21 is/are rejected under 35 U.S.C. 103 as being obvious over Jun-Nam in view of Credelle (US Patent Application Publication 2005/0083277).
Regarding claim 9, Jun discloses the electronic device defined in claim 1.
Jun does not specifically disclose wherein the plurality of subpixel groups is arranged in a checkerboard layout, wherein the plurality of subpixel groups comprises a first subset and a second subset, wherein each one of the first subset of the plurality of subpixel groups has emissive subpixels in a first layout, and wherein each one of the second subset of the plurality of subpixel groups has emissive subpixels in a second layout that is different than the first layout.
Credelle discloses wherein the plurality of subpixel groups (Figure 2 specifically a single row comprising four subpixels including a single red 104, single blue 108, and two green 106 subpixels. This interpretation does not utilize the grouping of 202.) is arranged in a checkerboard layout (paragraph [0017]), wherein the plurality of subpixel groups (single row of four pixels) comprises a first subset (odd rows) and a second subset (even rows), wherein each one of the first subset (odd rows) of the plurality of subpixel groups (single row of four pixels) has emissive subpixels in a first layout (rows 1 and 3: RGBG), and wherein each one of the second subset (even rows) of the plurality of subpixel groups (single row of four pixels) has emissive subpixels in a second layout (BGRB) that is different than the first layout (RGBG) (figure 2 RGBG is different from BGRB).
It would have been obvious to one skilled in the art before the effective filing date of the current application to enable Jun’s subpixel groups with the known technique of being arranged in a checkerboard layout wherein the plurality of subpixel groups comprises a first subset and a second subset, wherein each one of the first subset of the plurality of subpixel groups has emissive subpixels in a first layout, and wherein each one of the second subset of the plurality of subpixel groups has emissive subpixels in a second layout that is different than the first layout yielding the predictable results of preventing visual degradation of the display as disclosed by Credelle (paragraph [0017]).
Regarding claim 10, Credelle discloses the electronic device defined in claim 9, wherein blue emissive subpixels (Figure 2 108) in the first layout (RGBG) are changed to red emissive subpixels (104) in the second layout (BGRG) and wherein red emissive subpixels (104) in the first layout (RGBG) are changed to blue emissive subpixels (108) in the second layout (BGRG) (Figure 2 First layout: RGBG second layout: BGRG depicts a change between the red and blue subpixels in the four subpixel grouping.).
Regarding claim 11, Credelle discloses the electronic device defined in claim 9, wherein the first subset (Figure 2 odd Rows) of the plurality of subpixel groups (single row of four pixels) comprises every other row of subpixel groups in the checkerboard layout (figure 2 only odd rows) and wherein the second subset (even rows) of the plurality of subpixel groups (single row of four pixels) comprises remaining rows of subpixel groups in the checkerboard layout (only even rows).
6. Claim(s) 18 is/are rejected under 35 U.S.C. 103 as being obvious over Jun in view of Qui et al. (US Patent Application Publication 2024/0321178), herein after referred to as Qui’178.
Regarding claim 18, Jun discloses the electronic device defined in claim 1.
Jun does not specifically disclose wherein each one of the plurality of subpixel groups in the first portion comprises at least one dummy subpixel.
Qui’178 discloses wherein each one of the plurality of subpixel groups in the first portion comprises at least one dummy subpixel (paragraph [0099]).
It would have been obvious to one skilled in the art before the effective filing date of the current application to enable Jun with the known technique of wherein each one of the plurality of subpixel groups in the first portion comprises at least one dummy subpixel yielding the predictable results of uniformity of the display picture as disclosed by Qui’178 (paragraph [0099]).
7. Claim(s) 19-20 and 24-25 is/are rejected under 35 U.S.C. 103 as being obvious over Jun in view of Zhao et al. (US Patent Application Publication 2020/0111401), herein after referred to as Zhao.
Regarding independent claim 19, Jun discloses an electronic device (Figures 1A-1B 100), comprising:
a sensor (11 and/or 12 as described in paragraph [0071]); and
a display (110) that emits light in a direction (Z) (Figure 1A depicts front view with two dimensions, X vertical and Y vertical. The side view depicts the emission Z direction and vertical Y directions, [0111], herein after referred to as Z.) and comprises subpixels (SPC) (Figures 3, 6, and 10-13 depict pixel circuits SPC which can be arranged as a pixel circuit group SPCG (figure 11 SPCG1, figure 12 SPCG2, and figure 13 SPCG3) comprising TFTs arranged to control red, green, and blue LEDs as described in paragraph [0336]. Paragraph [0337] describes the pixels SPCG to comprise subpixels SPC_R1, SPC_G1, and SPC_B1, herein after subpixels in general will be referred to as SPC)), wherein:
the subpixels (SPC) comprise emissive subpixels that emit light (Figures 11-12 (specific reference numerals regard figure 11) and paragraph [0335] describes SPC_R1 to comprise ED_R1a and ED_R1b, SPC_G1 to comprise ED_G1a through ED_G1d, and SPC_B1 to comprise ED_B1a and ED_B1b, wherein ED is a light emitting element of the subpixel SPC. Herein after emissive subpixels in general will be referred to as ED.) and thin-film transistor subpixels that control the emissive sub-pixels (EA) (Figures 3 and 11-12 (specific reference numerals regard figure 11) depict the pixel circuit SPC comprising a plurality of transistors TFTs including a driving transistor DT described in paragraphs [0147]-[0149] to drive/control the light emitting element ED (in the light emissive sub-pixel area EA). Figure 11 depicts each subpixel SPC_R1, SPC_G1, and SPC_B1 each comprise their own respective driving TFT DT_R1, DR_G1, and DT_B1 that are directly connected to their own emissive sub-pixels ED_R1, ED_G1, and ED_B1. Herein after each thin-film transistor subpixel in general is referred to as SPC_RGB.);
the emissive subpixels (ED) are arranged in a regular grid of rows and columns (Figures 4-5 depicts EA to be arranged in rows and columns as described in paragraph [0206]. Paragraph [0114] describes the rows and columns to be arranged in accordance with data lines DL and gate lines GL of the pixel circuits (figure 2).);
the display (Figures 1A-1B and 4 100) has a first portion (OA1+OB1) that overlaps the sensor (11) in the direction (Z) ([0078] OA1 overlaps sensor 11) and a second portion (NA) that does not overlap the sensor (11) in the direction (Z) ([0078] NA doesn’t overlap 11);
the first portion (OA1+OB1) comprises a plurality of subpixel groups (SPC) that each include at least one emissive subpixel (ED in OBA1+OA1) [ ];
a total number of emissive subpixels (ED) per unit area is lower in the first portion (OA1+OB1) than in the second portion (NA) (Paragraphs [0090] and [0092] describes the number of pixels, measured as pixels per square inch PPI, in OA1 is lower than the number of pixels in NA.); and the emissive subpixels (ED) in the subpixel groups (SPC) are part of the regular grid of rows and columns (Figures 11-12 each depict SPCG1+SPCG2 to each comprise a driving transistor DT depicted in figure 3 to be connected, via ST, to data lines DL and gate lines GL in which the regular grid of rows and columns are arranged.).
Jun does not specifically disclose the first portion comprises a plurality of subpixel groups that each include at least one emissive subpixel and at least one dummy subpixel.
Zhao discloses the first portion (Figure 2 210 [0054]-[0055] an area on a display 200 that comprises a camera disposed on the rear side. Figure 3, first display area 310 described in paragraphs [0081]-[0082] to be the area that comprises a camera on the rear side. ) comprises a plurality of subpixel groups (Figure 3 reference four depicted pixel groups each comprising A1-A4) that each include at least one emissive subpixel (A4) and at least one dummy subpixel (A1-A3) ([0066] described A4 as the emissive pixel and A1-A3 as the dummy pixels. [0027]-[0029] describes the example of figure 3 is a ratio of one emissive pixel to three dummy pixels. Please note [0101] further discloses that the dummy pixels are electrically disconnected from any data line.).
It would have been obvious to one skilled in the art before the effective filing date of the current application to enable Jun with the known technique of the first portion comprises a plurality of subpixel groups that each include at least one emissive subpixel and at least one dummy subpixel yielding the predictable results of uniform brightness of the full screen that the human eye cannot feel the change as disclosed by Zhao ([0093]).
Regarding claim 20, Jun discloses electronic device defined in claim 19, wherein the at least one emissive subpixel comprises two red emissive subpixels (ED_R1a+ ED_R1b and ED_R2a+ED_R2b), two blue emissive subpixels (ED_B1a+ ED_B1b and ED_B2a+ED_B2b), and three green emissive subpixels (ED_G1a+ ED_G1b+ED_G1c and ED_G2a+ED_G2b+ED_G2c) and wherein each subpixel group (SPC) further includes a first thin-film transistor (DT_R1 and DT_R2) subpixel (SPC_R1 and SPC_R2) that controls the two red emissive subpixels (ED_R1a+ ED_R1b and ED_R2a+ED_R2b), a second thin-film transistor (DT_B1 and DT_B2) subpixel (SPC_B1 and SPC_B2) that controls the two blue emissive subpixels (ED_B1a+ ED_B1b and ED_B2a+ED_B2b), and a third thin-film transistor (DT_G1 and DT_G2) subpixel that controls the three green emissive subpixels (ED_G1a+ ED_G1b+ED_G1c and ED_G2a+ED_G2b+ED_G2c).
Regarding claim 24, Jun and Zhao disclose the electronic device defined in claim 19, wherein the at least one emissive subpixel comprises an organic light-emitting diode (OLED) layer (Jun: [0111]) and wherein the at least one dummy subpixel comprises the OLED layer (Zhao: [0080]).
Regarding claim 25, Jun discloses the electronic device defined in claim 24, wherein the OLED layer is selected form the group consisting of: a hole injection layer, a hole transport layer, an emissive layer ([0152]), an electron transport layer, an electron injection layer, an electron blocking layer, a charge generation layer, and a hole blocking layer.
8. Claim(s) 21-23 is/are rejected under 35 U.S.C. 103 as being obvious over Jun in view Credelle and further in view of Nam.
Regarding independent claim 21, Jun discloses an electronic device (Figures 1A-1B 100), comprising:
a sensor (11 and/or 12 as described in paragraph [0071]); and
a display (110) that emits light in a direction (Z) (Figure 1A depicts front view with two dimensions, X vertical and Y vertical. The side view depicts the emission Z direction and vertical Y directions, [0111], herein after referred to as Z.) and comprises subpixels (SPC) (Figures 3, 6, and 10-13 depict pixel circuits SPC which can be arranged as a pixel circuit group SPCG (figure 11 SPCG1, figure 12 SPCG2, and figure 13 SPCG3) comprising TFTs arranged to control red, green, and blue LEDs as described in paragraph [0336]. SPC_R1, SPC_G1, and SPC_B1 as described in paragraph [0337], herein after subpixels in general will be referred to as SPC), wherein:
the subpixels (SPC) comprise emissive subpixels that emit light (Figures 11-12 (specific reference numerals regard figure 11) and paragraph [0335] describes SPC_R1 to comprise ED_R1a and ED_R1b, SPC_G1 to comprise ED_G1a through ED_G1d, and SPC_B1 to comprise ED_B1a and ED_B1b, wherein ED is a light emitting element of the subpixel SPC. Herein after emissive subpixels in general will be referred to as ED.) and thin-film transistor subpixels that control the emissive sub-pixels (ED) (Figures 3 and 11-12 (specific reference numerals regard figure 11) depict the pixel circuit SPC comprising a plurality of transistors TFTs including a driving transistor DT described in paragraphs [0147]-[0149] to drive/control the light emitting element ED (in the light emissive sub-pixel area EA). Figure 11 depicts each subpixel SPC_R1, SPC_G1, and SPC_B1 each comprise their own respective driving TFT DT_R1, DR_G1, and DT_B1 that are directly connected to their own emissive sub-pixels ED_R1, ED_G1, and ED_B1. Herein after each thin-film transistor subpixel in general is referred to as SPC_RGB.);
the emissive subpixels (ED) are arranged in a regular grid of rows and columns (Figures 4-5 depicts EA to be arranged in rows and columns as described in paragraph [0206]. Paragraph [0114] describes the rows and columns to be arranged in accordance with data lines DL and gate lines GL of the pixel circuits (figure 2).);
the display (Figures 1A-1B and 4 100) has a first portion (OA1+OB1) that overlaps the sensor (11) ([0078] OA1 overlaps sensor 11) in the direction (Z) and a second portion (NA) that does not overlap the sensor (11) ([0078] NA doesn’t overlap 11) in the direction (Z);
the first portion (OA1+OB1) comprises a plurality of subpixel groups (SPCG1+SPCG2) that are arranged in a [ ] layout, wherein no unoccupied rows of subpixels (SPC) are interposed between adjacent rows of subpixel groups (SPCG1+SPCG2) in the [ ] layout and wherein no unoccupied columns of subpixels (SPC) are interposed between adjacent columns of subpixel groups (SPCG1+SPCG2) in the [ ] layout (Figures 2-3 depict no unoccupied rows or columns of subpixels SPC.);
[ ];
a total number of emissive subpixels (ED) per unit area is lower in the first portion (OA1+OB1) than in the second portion (NA) (Paragraphs [0090] and [0092] describes the number of pixels, measured as pixels per square inch PPI, in OA1 is lower than the number of pixels in NA.); and
the emissive subpixels (ED) in the subpixel groups (SPCG1+SPCG2) are part of the regular grid of rows and columns (Figures 11-12 each depict SPCG1+SPCG2 to each comprise a driving transistor DT depicted in figure 3 to be connected, via ST, to data lines DL and gate lines GL in which the regular grid of rows and columns are arranged.).
Jun does not specifically disclose the layout is a checkboard layout.
Credelle discloses a portion (Figure 2) comprises a plurality of subpixel groups (202) that are arranged in a checkerboard layout (paragraph [0017]), wherein no unoccupied rows of subpixels are interposed between adjacent rows of subpixel groups in the checkerboard layout and wherein no unoccupied columns of subpixels are interposed between adjacent columns of subpixel groups in the checkerboard layout (Figure 2 depicts no unoccupied rows or columns of subpixels.).
It would have been obvious to one skilled in the art before the effective filing date of the current application to enable Jun’s subpixel groups with the known technique of a plurality of subpixel groups that are arranged in a checkerboard layout, wherein no unoccupied rows of subpixels are interposed between adjacent rows of subpixel groups in the checkerboard layout and wherein no unoccupied columns of subpixels are interposed between adjacent columns of subpixel groups in the checkerboard layout yielding the predictable results of preventing visual degradation of the display as disclosed by Credelle (paragraph [0017]).
Jun does not specifically disclose two adjacent subpixel groups of the plurality of subpixels groups are separated by at least three grid squares (Support for the subject matter is found, for example, in the current application’s figure 4 [0098] describing 1 out of every 2 grid squares are occupied by a subpixel implying each “grid square” to regard an intersection of a data and gate line or intersection of the row and column of the grid.) that are unoccupied by any subpixels.
Nam discloses two adjacent subpixel groups of the plurality of subpixels groups are separated by at least three grid squares that are unoccupied by any subpixels (Figure 9 depicts subpixel groups PG1-PG7 each arranged in a grid (Data column x Scan row). For example, PG1 is listed as occupying columns 1-3 in row 3 which is separated by three rows from PG3 and five columns from PG5.).
It would have been obvious to one skilled in the art before the effective filing date of the current application to enable Jun-Credelle with the known technique of two adjacent subpixel groups of the plurality of subpixels groups are separated by at least three grid squares that are unoccupied by any subpixels yielding the predictable results of improving the light transmittance areas TA that are provided in the unoccupied grid squares as disclosed by Nam ([0169]).
Regarding claim 22, Jun discloses the electronic device defined in claim 21, wherein each subpixel group (figure 11 SPCG1 and/or figure 12 SPCG2) comprises at least six emissive subpixels ([0213]-[0215] describes a single TFT may drive N light emitting elements ED with a ratio of 1:N with N= ED that is 2 or greater. Figures 11-12 depicts an example of 3 TFTs to drive 8 ED (which include at least six).).
Regarding claim 23, Jun and Nam disclose the electronic device defined in claim 21, further comprising:
a plurality of gate lines (Jun: Figure 3 GL and Nam: Figure 15 GL) that provide signals (Jun: scan signals [0113]) to thin-film transistor (Jun: ST [0187]) subpixels (Jun: Figure 5 SPC3; Nam: Figure 15: Pm) in the second portion (Jun: NA; Nam: MDA) of the display (Jun: 110), wherein a first portion (Nam: GL3) of the plurality of gate lines (Jun + Nam: GL) also provides signals (Jun: scan signals) to thin-film transistor (Jun: ST) subpixels (Jun: SPC1, SPC2, and SPC4; Nam: figure 15 Pa) in the first portion (Jun: OA1+OB1; Nam: CA) of the display (Jun: 110), and wherein a second portion (Nam: GL1 and GL2) of the plurality of gate lines (Jun and Nam: GL) does not provide signals to any thin-film transistor subpixels in the first portion (Jun: OA1+OB1; Nam: CA) of the display (Nam: [0227]-[0228] GL1 and GL2 are not connected to pixels in area CA).
9. Claim(s) 26 is/are rejected under 35 U.S.C. 103 as being obvious over Jun-Zhao in view of Lim et al. (US Patent Application Publication 2023/0209921), herein after referred to as Lim.
Regarding claim 26, Jun and Zhao discloses the electronic device defined in claim 24.
Neither Jun or Zhao specifically disclose wherein the at least one dummy subpixel further comprises an anode and a spacer interposed between the anode and the OLED layer.
Lim discloses wherein the at least one dummy subpixel (Figure 13 DP [0128]) further comprises an anode (122) and a spacer (CL1) interposed between the anode (122) and the OLED layer (130) ([0129]).
It would have been obvious to one skilled in the art before the effective filing date of the current application to enable Jun-Zhao with the known technique of disclose wherein the at least one dummy subpixel further comprises an anode and a spacer interposed between the anode and the OLED layer yielding the predictable results of proving a light sensor area without increasing the size of the bezel as disclosed by Lim ([0132]).
Conclusion
10. Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/CHRISTOPHER E LEIBY/Primary Examiner, Art Unit 2621
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